[Feature] add GA346 baseline version
Change-Id: Ic62933698569507dcf98240cdf5d9931ae34348f
diff --git a/src/kernel/modules/netsys_driver/nat/include/mii_mgr.h b/src/kernel/modules/netsys_driver/nat/include/mii_mgr.h
new file mode 100755
index 0000000..f8e0517
--- /dev/null
+++ b/src/kernel/modules/netsys_driver/nat/include/mii_mgr.h
@@ -0,0 +1,27 @@
+/* Copyright 2016 MediaTek Inc.
+ * Author: Carlos Huang <carlos.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netdevice.h>
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+
+#include "raether.h"
+
+extern struct net_device *dev_raether;
+
+#define PHY_CONTROL_0 0x0004
+#define MDIO_PHY_CONTROL_0 (RALINK_ETH_MAC_BASE + PHY_CONTROL_0)
+#define enable_mdio(x)
+
diff --git a/src/kernel/modules/netsys_driver/nat/include/ra_dbg_proc.h b/src/kernel/modules/netsys_driver/nat/include/ra_dbg_proc.h
new file mode 100755
index 0000000..38e6037
--- /dev/null
+++ b/src/kernel/modules/netsys_driver/nat/include/ra_dbg_proc.h
@@ -0,0 +1,96 @@
+/* Copyright 2016 MediaTek Inc.
+ * Author: Nelson Chang <nelson.chang@mediatek.com>
+ * Author: Carlos Huang <carlos.huang@mediatek.com>
+ * Author: Harry Huang <harry.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef RA_DBG_PROC_H
+#define RA_DBG_PROC_H
+
+#include <linux/ctype.h>
+#include <linux/proc_fs.h>
+#include "raeth_config.h"
+
+extern struct net_device *dev_raether;
+
+void dump_qos(void);
+void dump_reg(struct seq_file *s);
+void dump_cp0(void);
+
+int debug_proc_init(void);
+void debug_proc_exit(void);
+
+int tso_len_update(int tso_len);
+int num_of_txd_update(int num_of_txd);
+void rtk_hal_dump_mib(void);
+#ifdef CONFIG_RAETH_LRO
+int lro_stats_update(struct net_lro_mgr *lro_mgr, bool all_flushed);
+#endif
+extern unsigned int M2Q_table[64];
+extern struct QDMA_txdesc *free_head;
+extern struct SFQ_table *sfq0;
+extern struct SFQ_table *sfq1;
+extern struct SFQ_table *sfq2;
+extern struct SFQ_table *sfq3;
+extern int init_schedule;
+extern int working_schedule;
+struct raeth_int_t {
+ unsigned int RX_COHERENT_CNT;
+ unsigned int RX_DLY_INT_CNT;
+ unsigned int TX_COHERENT_CNT;
+ unsigned int TX_DLY_INT_CNT;
+ unsigned int RING3_RX_DLY_INT_CNT;
+ unsigned int RING2_RX_DLY_INT_CNT;
+ unsigned int RING1_RX_DLY_INT_CNT;
+ unsigned int RXD_ERROR_CNT;
+ unsigned int ALT_RPLC_INT3_CNT;
+ unsigned int ALT_RPLC_INT2_CNT;
+ unsigned int ALT_RPLC_INT1_CNT;
+ unsigned int RX_DONE_INT3_CNT;
+ unsigned int RX_DONE_INT2_CNT;
+ unsigned int RX_DONE_INT1_CNT;
+ unsigned int RX_DONE_INT0_CNT;
+ unsigned int TX_DONE_INT3_CNT;
+ unsigned int TX_DONE_INT2_CNT;
+ unsigned int TX_DONE_INT1_CNT;
+ unsigned int TX_DONE_INT0_CNT;
+};
+
+int int_stats_update(unsigned int int_status);
+
+#define DUMP_EACH_PORT(base) \
+ for (i = 0; i < 7; i++) { \
+ mii_mgr_read(31, (base) + (i * 0x100), &pkt_cnt); \
+ seq_printf(seq, "%8u ", pkt_cnt); \
+ } \
+
+/* HW LRO functions */
+int hwlro_debug_proc_init(struct proc_dir_entry *proc_reg_dir);
+void hwlro_debug_proc_exit(struct proc_dir_entry *proc_reg_dir);
+
+int rss_debug_proc_init(struct proc_dir_entry *proc_reg_dir);
+void rss_debug_proc_exit(struct proc_dir_entry *proc_reg_dir);
+
+/* HW IO-Coherent functions */
+#ifdef CONFIG_RAETH_HW_IOCOHERENT
+void hwioc_debug_proc_init(struct proc_dir_entry *proc_reg_dir);
+void hwioc_debug_proc_exit(struct proc_dir_entry *proc_reg_dir);
+#else
+static inline void hwioc_debug_proc_init(struct proc_dir_entry *proc_reg_dir)
+{
+}
+
+static inline void hwioc_debug_proc_exit(struct proc_dir_entry *proc_reg_dir)
+{
+}
+#endif /* CONFIG_RAETH_HW_IOCOHERENT */
+
+#endif
diff --git a/src/kernel/modules/netsys_driver/nat/include/ra_ethtool.h b/src/kernel/modules/netsys_driver/nat/include/ra_ethtool.h
new file mode 100755
index 0000000..cff52e2
--- /dev/null
+++ b/src/kernel/modules/netsys_driver/nat/include/ra_ethtool.h
@@ -0,0 +1,34 @@
+/* Copyright 2016 MediaTek Inc.
+ * Author: Harry Huang <harry.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef RA_ETHTOOL_H
+#define RA_ETHTOOL_H
+
+extern struct net_device *dev_raether;
+
+/* ethtool related */
+void ethtool_init(struct net_device *dev);
+int et_get_settings(struct net_device *dev, struct ethtool_cmd *cmd);
+u32 et_get_link(struct net_device *dev);
+unsigned char get_current_phy_address(void);
+int mdio_read(struct net_device *dev, int phy_id, int location);
+void mdio_write(struct net_device *dev, int phy_id, int location, int value);
+
+/* for pseudo interface */
+void ethtool_virt_init(struct net_device *dev);
+int et_virt_get_settings(struct net_device *dev, struct ethtool_cmd *cmd);
+u32 et_virt_get_link(struct net_device *dev);
+int mdio_virt_read(struct net_device *dev, int phy_id, int location);
+void mdio_virt_write(struct net_device *dev, int phy_id, int location,
+ int value);
+
+#endif
diff --git a/src/kernel/modules/netsys_driver/nat/include/ra_ioctl.h b/src/kernel/modules/netsys_driver/nat/include/ra_ioctl.h
new file mode 100755
index 0000000..b94cb33
--- /dev/null
+++ b/src/kernel/modules/netsys_driver/nat/include/ra_ioctl.h
@@ -0,0 +1,179 @@
+/* Copyright 2016 MediaTek Inc.
+ * Author: Nelson Chang <nelson.chang@mediatek.com>
+ * Author: Carlos Huang <carlos.huang@mediatek.com>
+ * Author: Harry Huang <harry.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef _RAETH_IOCTL_H
+#define _RAETH_IOCTL_H
+
+/* ioctl commands */
+#define RAETH_SW_IOCTL 0x89F0
+#define RAETH_ESW_REG_READ 0x89F1
+#define RAETH_ESW_REG_WRITE 0x89F2
+#define RAETH_MII_READ 0x89F3
+#define RAETH_MII_WRITE 0x89F4
+#define RAETH_ESW_INGRESS_RATE 0x89F5
+#define RAETH_ESW_EGRESS_RATE 0x89F6
+#define RAETH_ESW_PHY_DUMP 0x89F7
+#define RAETH_QDMA_IOCTL 0x89F8
+#define RAETH_EPHY_IOCTL 0x89F9
+#define RAETH_MII_READ_CL45 0x89FC
+#define RAETH_MII_WRITE_CL45 0x89FD
+#define RAETH_QDMA_SFQ_WEB_ENABLE 0x89FE
+#define RAETH_SET_LAN_IP 0x89FF
+
+/* switch ioctl commands */
+#define SW_IOCTL_SET_EGRESS_RATE 0x0000
+#define SW_IOCTL_SET_INGRESS_RATE 0x0001
+#define SW_IOCTL_SET_VLAN 0x0002
+#define SW_IOCTL_DUMP_VLAN 0x0003
+#define SW_IOCTL_DUMP_TABLE 0x0004
+#define SW_IOCTL_ADD_L2_ADDR 0x0005
+#define SW_IOCTL_DEL_L2_ADDR 0x0006
+#define SW_IOCTL_ADD_MCAST_ADDR 0x0007
+#define SW_IOCTL_DEL_MCAST_ADDR 0x0008
+#define SW_IOCTL_DUMP_MIB 0x0009
+#define SW_IOCTL_ENABLE_IGMPSNOOP 0x000A
+#define SW_IOCTL_DISABLE_IGMPSNOOP 0x000B
+#define SW_IOCTL_SET_PORT_TRUNK 0x000C
+#define SW_IOCTL_GET_PORT_TRUNK 0x000D
+#define SW_IOCTL_SET_PORT_MIRROR 0x000E
+#define SW_IOCTL_GET_PHY_STATUS 0x000F
+#define SW_IOCTL_READ_REG 0x0010
+#define SW_IOCTL_WRITE_REG 0x0011
+#define SW_IOCTL_QOS_EN 0x0012
+#define SW_IOCTL_QOS_SET_TABLE2TYPE 0x0013
+#define SW_IOCTL_QOS_GET_TABLE2TYPE 0x0014
+#define SW_IOCTL_QOS_SET_PORT2TABLE 0x0015
+#define SW_IOCTL_QOS_GET_PORT2TABLE 0x0016
+#define SW_IOCTL_QOS_SET_PORT2PRI 0x0017
+#define SW_IOCTL_QOS_GET_PORT2PRI 0x0018
+#define SW_IOCTL_QOS_SET_DSCP2PRI 0x0019
+#define SW_IOCTL_QOS_GET_DSCP2PRI 0x001a
+#define SW_IOCTL_QOS_SET_PRI2QUEUE 0x001b
+#define SW_IOCTL_QOS_GET_PRI2QUEUE 0x001c
+#define SW_IOCTL_QOS_SET_QUEUE_WEIGHT 0x001d
+#define SW_IOCTL_QOS_GET_QUEUE_WEIGHT 0x001e
+#define SW_IOCTL_SET_PHY_TEST_MODE 0x001f
+#define SW_IOCTL_GET_PHY_REG 0x0020
+#define SW_IOCTL_SET_PHY_REG 0x0021
+#define SW_IOCTL_VLAN_TAG 0x0022
+#define SW_IOCTL_CLEAR_TABLE 0x0023
+#define SW_IOCTL_CLEAR_VLAN 0x0024
+#define SW_IOCTL_SET_VLAN_MODE 0x0025
+
+/*****************QDMA IOCTL DATA*************/
+#define RAETH_QDMA_REG_READ 0x0000
+#define RAETH_QDMA_REG_WRITE 0x0001
+#define RAETH_QDMA_QUEUE_MAPPING 0x0002
+#define RAETH_QDMA_READ_CPU_CLK 0x0003
+/*********************************************/
+/******************EPHY IOCTL DATA************/
+/*MT7622 10/100 phy cal*/
+#define RAETH_VBG_IEXT_CALIBRATION 0x0000
+#define RAETH_TXG_R50_CALIBRATION 0x0001
+#define RAETH_TXG_OFFSET_CALIBRATION 0x0002
+#define RAETH_TXG_AMP_CALIBRATION 0x0003
+#define GE_TXG_R50_CALIBRATION 0x0004
+#define GE_TXG_OFFSET_CALIBRATION 0x0005
+#define GE_TXG_AMP_CALIBRATION 0x0006
+/*********************************************/
+#define REG_ESW_WT_MAC_MFC 0x10
+#define REG_ESW_ISC 0x18
+#define REG_ESW_WT_MAC_ATA1 0x74
+#define REG_ESW_WT_MAC_ATA2 0x78
+#define REG_ESW_WT_MAC_ATWD 0x7C
+#define REG_ESW_WT_MAC_ATC 0x80
+
+#define REG_ESW_TABLE_TSRA1 0x84
+#define REG_ESW_TABLE_TSRA2 0x88
+#define REG_ESW_TABLE_ATRD 0x8C
+
+#define REG_ESW_VLAN_VTCR 0x90
+#define REG_ESW_VLAN_VAWD1 0x94
+#define REG_ESW_VLAN_VAWD2 0x98
+
+#if defined(CONFIG_MACH_MT7623)
+#define REG_ESW_VLAN_ID_BASE 0x100
+#else
+#define REG_ESW_VLAN_ID_BASE 0x50
+#endif
+#define REG_ESW_VLAN_MEMB_BASE 0x70
+#define REG_ESW_TABLE_SEARCH 0x24
+#define REG_ESW_TABLE_STATUS0 0x28
+#define REG_ESW_TABLE_STATUS1 0x2C
+#define REG_ESW_TABLE_STATUS2 0x30
+#define REG_ESW_WT_MAC_AD0 0x34
+#define REG_ESW_WT_MAC_AD1 0x38
+#define REG_ESW_WT_MAC_AD2 0x3C
+
+#if defined(CONFIG_MACH_MT7623)
+#define REG_ESW_MAX 0xFC
+#else
+#define REG_ESW_MAX 0x16C
+#endif
+#define REG_HQOS_MAX 0x3FFF
+
+struct esw_reg {
+ unsigned int off;
+ unsigned int val;
+};
+
+struct ra_mii_ioctl_data {
+ __u32 phy_id;
+ __u32 reg_num;
+ __u32 val_in;
+ __u32 val_out;
+ __u32 port_num;
+ __u32 dev_addr;
+ __u32 reg_addr;
+};
+
+struct ra_switch_ioctl_data {
+ unsigned int cmd;
+ unsigned int on_off;
+ unsigned int port;
+ unsigned int bw;
+ unsigned int vid;
+ unsigned int fid;
+ unsigned int port_map;
+ unsigned int rx_port_map;
+ unsigned int tx_port_map;
+ unsigned int igmp_query_interval;
+ unsigned int reg_addr;
+ unsigned int reg_val;
+ unsigned int mode;
+ unsigned int qos_queue_num;
+ unsigned int qos_type;
+ unsigned int qos_pri;
+ unsigned int qos_dscp;
+ unsigned int qos_table_idx;
+ unsigned int qos_weight;
+ unsigned char mac[6];
+};
+
+struct qdma_ioctl_data {
+ unsigned int cmd;
+ unsigned int off;
+ unsigned int val;
+};
+
+struct ephy_ioctl_data {
+ unsigned int cmd;
+};
+
+struct esw_rate {
+ unsigned int on_off;
+ unsigned int port;
+ unsigned int bw; /*Mbps */
+};
+#endif /* _RAETH_IOCTL_H */
diff --git a/src/kernel/modules/netsys_driver/nat/include/ra_mac.h b/src/kernel/modules/netsys_driver/nat/include/ra_mac.h
new file mode 100755
index 0000000..c329703
--- /dev/null
+++ b/src/kernel/modules/netsys_driver/nat/include/ra_mac.h
@@ -0,0 +1,30 @@
+/* Copyright 2016 MediaTek Inc.
+ * Author: Nelson Chang <nelson.chang@mediatek.com>
+ * Author: Carlos Huang <carlos.huang@mediatek.com>
+ * Author: Harry Huang <harry.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef RA_MAC_H
+#define RA_MAC_H
+
+void ra2880stop(struct END_DEVICE *ei_local);
+void set_mac_address(unsigned char p[6]);
+void set_mac2_address(unsigned char p[6]);
+int str_to_ip(unsigned int *ip, const char *str);
+void enable_auto_negotiate(struct END_DEVICE *ei_local);
+void set_ge1_force_1000(void);
+void set_ge2_force_1000(void);
+void set_ge1_an(void);
+void set_ge2_an(void);
+void set_ge2_gmii(void);
+void set_ge0_gmii(void);
+void set_ge2_force_link_down(void);
+#endif
diff --git a/src/kernel/modules/netsys_driver/nat/include/ra_switch.h b/src/kernel/modules/netsys_driver/nat/include/ra_switch.h
new file mode 100755
index 0000000..201a697
--- /dev/null
+++ b/src/kernel/modules/netsys_driver/nat/include/ra_switch.h
@@ -0,0 +1,101 @@
+/* Copyright 2016 MediaTek Inc.
+ * Author: Carlos Huang <carlos.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef RA_SWITCH_H
+#define RA_SWITCH_H
+
+#include "./rtl8367c/include/rtk_switch.h"
+#include "./rtl8367c/include/rtk_hal.h"
+#include "./rtl8367c/include/port.h"
+#include "./rtl8367c/include/vlan.h"
+#include "./rtl8367c/include/rtl8367c_asicdrv_port.h"
+
+extern struct net_device *dev_raether;
+#define ANACAL_INIT 0x01
+#define ANACAL_ERROR 0xFD
+#define ANACAL_SATURATION 0xFE
+#define ANACAL_FINISH 0xFF
+#define ANACAL_PAIR_A 0
+#define ANACAL_PAIR_B 1
+#define ANACAL_PAIR_C 2
+#define ANACAL_PAIR_D 3
+#define DAC_IN_0V 0x000
+#define DAC_IN_2V 0x0f0
+#define TX_AMP_OFFSET_0MV 0x20
+#define TX_AMP_OFFSET_VALID_BITS 6
+#define FE_CAL_P0 0
+#define FE_CAL_P1 1
+#if defined(CONFIG_MACH_LEOPARD)
+#define FE_CAL_COMMON 1
+#else
+#define FE_CAL_COMMON 0
+#endif
+
+void fe_sw_init(void);
+void fe_sw_preinit(struct END_DEVICE *ei_local);
+void fe_sw_deinit(struct END_DEVICE *ei_local);
+void sw_ioctl(struct ra_switch_ioctl_data *ioctl_data);
+irqreturn_t esw_interrupt(int irq, void *resv);
+irqreturn_t gsw_interrupt(int irq, void *resv);
+
+/* struct mtk_gsw - the structure that holds the SoC specific data
+ * @dev: The Device struct
+ * @base: The base address
+ * @piac_offset: The PIAC base may change depending on SoC
+ * @irq: The IRQ we are using
+ * @port4: The port4 mode on MT7620
+ * @autopoll: Is MDIO autopolling enabled
+ * @ethsys: The ethsys register map
+ * @pctl: The pin control register map
+ * @clk_trgpll: The trgmii pll clock
+ */
+struct mtk_gsw {
+ struct mtk_eth *eth;
+ struct device *dev;
+ void __iomem *base;
+ u32 piac_offset;
+ int irq;
+ int port4;
+ unsigned long int autopoll;
+
+ struct regmap *ethsys;
+ struct regmap *pctl;
+
+ int trgmii_force;
+ bool wllll;
+ bool mcm;
+ struct pinctrl *pins;
+ struct pinctrl_state *ps_default;
+ struct pinctrl_state *ps_reset;
+ int reset_pin;
+ struct regulator *supply;
+ struct regulator *b3v;
+};
+
+extern u8 fe_cal_flag;
+extern u8 fe_cal_flag_mdix;
+extern u8 fe_cal_tx_offset_flag;
+extern u8 fe_cal_tx_offset_flag_mdix;
+extern u8 fe_cal_r50_flag;
+extern u8 fe_cal_vbg_flag;
+void fe_cal_r50(u8 port_num, u32 delay);
+void fe_cal_tx_amp(u8 port_num, u32 delay);
+void fe_cal_tx_amp_mdix(u8 port_num, u32 delay);
+void fe_cal_tx_offset(u8 port_num, u32 delay);
+void fe_cal_tx_offset_mdix(u8 port_num, u32 delay);
+void fe_cal_vbg(u8 port_num, u32 delay);
+/*giga port calibration*/
+void ge_cal_r50(u8 port_num, u32 delay);
+void ge_cal_tx_amp(u8 port_num, u32 delay);
+void ge_cal_tx_offset(u8 port_num, u32 delay);
+void do_ge_phy_all_analog_cal(u8 phyaddr);
+#endif
diff --git a/src/kernel/modules/netsys_driver/nat/include/raeth_config.h b/src/kernel/modules/netsys_driver/nat/include/raeth_config.h
new file mode 100755
index 0000000..d9eed66
--- /dev/null
+++ b/src/kernel/modules/netsys_driver/nat/include/raeth_config.h
@@ -0,0 +1,328 @@
+/* Copyright 2016 MediaTek Inc.
+ * Author: Nelson Chang <nelson.chang@mediatek.com>
+ * Author: Carlos Huang <carlos.huang@mediatek.com>
+ * Author: Harry Huang <harry.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef RAETH_CONFIG_H
+#define RAETH_CONFIG_H
+
+/* compile flag for features */
+#define DELAY_INT
+
+#define CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
+/*#define CONFIG_QDMA_QOS_WEB*/
+#define CONFIG_QDMA_QOS_MARK
+
+#if !defined(CONFIG_SOC_MT7621)
+#define CONFIG_RAETH_NAPI
+#define CONFIG_RAETH_TX_RX_INT_SEPARATION
+/*#define CONFIG_RAETH_NAPI_TX_RX*/
+#define CONFIG_RAETH_NAPI_RX_ONLY
+#endif
+
+#if defined(CONFIG_SOC_MT7621)
+#define CONFIG_GE1_RGMII_FORCE_1000
+#define CONFIG_GE1_RGMII_FORCE_1200
+#define CONFIG_RA_NETWORK_TASKLET_BH
+#endif
+/*CONFIG_RA_NETWORK_TASKLET_BH*/
+/*CONFIG_RA_NETWORK_WORKQUEUE_BH*/
+/*CONFIG_RAETH_SPECIAL_TAG*/
+#define CONFIG_RAETH_CHECKSUM_OFFLOAD
+#if !defined(CONFIG_SOC_MT7621)
+#define CONFIG_RAETH_HW_LRO
+#endif
+/* #define CONFIG_RAETH_HW_LRO_FORCE */
+/* #define CONFIG_RAETH_HW_LRO_DVT */
+#define CONFIG_RAETH_HW_VLAN_TX
+/*CONFIG_RAETH_HW_VLAN_RX*/
+#define CONFIG_RAETH_TSO
+/*#define CONFIG_RAETH_ETHTOOL*/
+#define CONFIG_RAETH_QDMA
+/*CONFIG_RAETH_QDMATX_QDMARX*/
+/*CONFIG_HW_SFQ*/
+#define CONFIG_RAETH_HW_IOCOHERENT
+#define CONFIG_RAETH_GMAC2
+/*#define CONFIG_RAETH_RSS_4RING*/
+/*#define CONFIG_RAETH_RSS_2RING*/
+/* definitions */
+#ifdef DELAY_INT
+#define FE_DLY_INT BIT(0)
+#else
+#define FE_DLY_INT (0)
+#endif
+#ifdef CONFIG_RAETH_HW_LRO
+#define FE_HW_LRO BIT(1)
+#else
+#define FE_HW_LRO (0)
+#endif
+#ifdef CONFIG_RAETH_HW_LRO_FORCE
+#define FE_HW_LRO_FPORT BIT(2)
+#else
+#define FE_HW_LRO_FPORT (0)
+#endif
+#ifdef CONFIG_RAETH_LRO
+#define FE_SW_LRO BIT(3)
+#else
+#define FE_SW_LRO (0)
+#endif
+#ifdef CONFIG_RAETH_QDMA
+#define FE_QDMA BIT(4)
+#else
+#define FE_QDMA (0)
+#endif
+#ifdef CONFIG_RAETH_NAPI
+#define FE_INT_NAPI BIT(5)
+#else
+#define FE_INT_NAPI (0)
+#endif
+#ifdef CONFIG_RA_NETWORK_WORKQUEUE_BH
+#define FE_INT_WORKQ BIT(6)
+#else
+#define FE_INT_WORKQ (0)
+#endif
+#ifdef CONFIG_RA_NETWORK_TASKLET_BH
+#define FE_INT_TASKLET BIT(7)
+#else
+#define FE_INT_TASKLET (0)
+#endif
+#ifdef CONFIG_RAETH_TX_RX_INT_SEPARATION
+#define FE_IRQ_SEPARATE BIT(8)
+#else
+#define FE_IRQ_SEPARATE (0)
+#endif
+#define FE_GE2_SUPPORT BIT(9)
+#ifdef CONFIG_RAETH_ETHTOOL
+#define FE_ETHTOOL BIT(10)
+#else
+#define FE_ETHTOOL (0)
+#endif
+#ifdef CONFIG_RAETH_CHECKSUM_OFFLOAD
+#define FE_CSUM_OFFLOAD BIT(11)
+#else
+#define FE_CSUM_OFFLOAD (0)
+#endif
+#ifdef CONFIG_RAETH_TSO
+#define FE_TSO BIT(12)
+#else
+#define FE_TSO (0)
+#endif
+#ifdef CONFIG_RAETH_TSOV6
+#define FE_TSO_V6 BIT(13)
+#else
+#define FE_TSO_V6 (0)
+#endif
+#ifdef CONFIG_RAETH_HW_VLAN_TX
+#define FE_HW_VLAN_TX BIT(14)
+#else
+#define FE_HW_VLAN_TX (0)
+#endif
+#ifdef CONFIG_RAETH_HW_VLAN_RX
+#define FE_HW_VLAN_RX BIT(15)
+#else
+#define FE_HW_VLAN_RX (0)
+#endif
+#ifdef CONFIG_RAETH_QDMA
+#define FE_QDMA_TX BIT(16)
+#else
+#define FE_QDMA_TX (0)
+#endif
+#ifdef CONFIG_RAETH_QDMATX_QDMARX
+#define FE_QDMA_RX BIT(17)
+#else
+#define FE_QDMA_RX (0)
+#endif
+#ifdef CONFIG_HW_SFQ
+#define FE_HW_SFQ BIT(18)
+#else
+#define FE_HW_SFQ (0)
+#endif
+#define FE_HW_IOCOHERENT BIT(19)
+
+#ifdef CONFIG_MTK_FPGA
+#define FE_FPGA_MODE BIT(20)
+#else
+#define FE_FPGA_MODE (0)
+#endif
+
+#ifdef CONFIG_RAETH_RSS_4RING
+#define FE_RSS_4RING BIT(20)
+#else
+#define FE_RSS_4RING (0)
+#endif
+
+#ifdef CONFIG_RAETH_RSS_2RING
+#define FE_RSS_2RING BIT(2)
+#else
+#define FE_RSS_2RING (0)
+#endif
+
+#ifdef CONFIG_RAETH_HW_LRO_REASON_DBG
+#define FE_HW_LRO_DBG BIT(21)
+#else
+#define FE_HW_LRO_DBG (0)
+#endif
+#ifdef CONFIG_RAETH_INT_DBG
+#define FE_RAETH_INT_DBG BIT(22)
+#else
+#define FE_RAETH_INT_DBG (0)
+#endif
+#ifdef CONFIG_USER_SNMPD
+#define USER_SNMPD BIT(23)
+#else
+#define USER_SNMPD (0)
+#endif
+#ifdef CONFIG_TASKLET_WORKQUEUE_SW
+#define TASKLET_WORKQUEUE_SW BIT(24)
+#else
+#define TASKLET_WORKQUEUE_SW (0)
+#endif
+#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
+#define FE_HW_NAT BIT(25)
+#else
+#define FE_HW_NAT (0)
+#endif
+#ifdef CONFIG_RAETH_NAPI_TX_RX
+#define FE_INT_NAPI_TX_RX BIT(26)
+#else
+#define FE_INT_NAPI_TX_RX (0)
+#endif
+#ifdef CONFIG_QDMA_MQ
+#define QDMA_MQ BIT(27)
+#else
+#define QDMA_MQ (0)
+#endif
+#ifdef CONFIG_RAETH_NAPI_RX_ONLY
+#define FE_INT_NAPI_RX_ONLY BIT(28)
+#else
+#define FE_INT_NAPI_RX_ONLY (0)
+#endif
+#ifdef CONFIG_QDMA_SUPPORT_QOS
+#define FE_QDMA_FQOS BIT(29)
+#else
+#define FE_QDMA_FQOS (0)
+#endif
+
+#ifdef CONFIG_QDMA_QOS_WEB
+#define QDMA_QOS_WEB BIT(30)
+#else
+#define QDMA_QOS_WEB (0)
+#endif
+
+#ifdef CONFIG_QDMA_QOS_MARK
+#define QDMA_QOS_MARK BIT(31)
+#else
+#define QDMA_QOS_MARK (0)
+#endif
+
+#define MT7626_FE (7626)
+#define MT7623_FE (7623)
+#define MT7622_FE (7622)
+#define MT7621_FE (7621)
+#define LEOPARD_FE (1985)
+
+#define GMAC2 BIT(0)
+#define LAN_WAN_SUPPORT BIT(1)
+#define WAN_AT_P0 BIT(2)
+#define WAN_AT_P4 BIT(3)
+#if defined(CONFIG_GE1_RGMII_FORCE_1000)
+#define GE1_RGMII_FORCE_1000 BIT(4)
+#define GE1_TRGMII_FORCE_2000 (0)
+#define GE1_TRGMII_FORCE_2600 (0)
+#define MT7530_TRGMII_PLL_25M (0x0A00)
+#define MT7530_TRGMII_PLL_40M (0x0640)
+#elif defined(CONFIG_GE1_TRGMII_FORCE_2000)
+#define GE1_TRGMII_FORCE_2000 BIT(5)
+#define GE1_RGMII_FORCE_1000 (0)
+#define GE1_TRGMII_FORCE_2600 (0)
+#define MT7530_TRGMII_PLL_25M (0x1400)
+#define MT7530_TRGMII_PLL_40M (0x0C80)
+#elif defined(CONFIG_GE1_TRGMII_FORCE_2600)
+#define GE1_TRGMII_FORCE_2600 BIT(6)
+#define GE1_RGMII_FORCE_1000 (0)
+#define GE1_TRGMII_FORCE_2000 (0)
+#define MT7530_TRGMII_PLL_25M (0x1A00)
+#define MT7530_TRGMII_PLL_40M (0x1040)
+#define TRGMII
+#else
+#define GE1_RGMII_FORCE_1000 (0)
+#define GE1_TRGMII_FORCE_2000 (0)
+#define GE1_TRGMII_FORCE_2600 (0)
+#define MT7530_TRGMII_PLL_25M (0)
+#define MT7530_TRGMII_PLL_40M (0)
+#endif
+
+#define GE1_RGMII_AN BIT(7)
+#define GE1_SGMII_AN BIT(8)
+#define GE1_SGMII_FORCE_2500 BIT(9)
+#define GE1_RGMII_ONE_EPHY BIT(10)
+#define RAETH_ESW BIT(11)
+#define GE1_RGMII_NONE BIT(12)
+#define GE2_RGMII_FORCE_1000 BIT(13)
+#define GE2_RGMII_AN BIT(14)
+#define GE2_INTERNAL_GPHY BIT(15)
+#define GE2_SGMII_AN BIT(16)
+#define GE2_SGMII_FORCE_2500 BIT(17)
+#define MT7622_EPHY BIT(18)
+#define RAETH_SGMII BIT(19)
+#define GE2_RAETH_SGMII BIT(20)
+#define LEOPARD_EPHY BIT(21)
+#define SGMII_SWITCH BIT(22)
+#define LEOPARD_EPHY_GMII BIT(23)
+/* /#ifndef CONFIG_MAC_TO_GIGAPHY_MODE_ADDR */
+/* #define CONFIG_MAC_TO_GIGAPHY_MODE_ADDR (0) */
+/* #endif */
+/* #ifndef CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2 */
+/* #define CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2 (0) */
+/* #endif */
+
+/* macros */
+#define fe_features_config(end_device) \
+{ \
+end_device->features = 0; \
+end_device->features |= FE_DLY_INT; \
+end_device->features |= FE_HW_LRO; \
+end_device->features |= FE_HW_LRO_FPORT;\
+end_device->features |= FE_HW_LRO_DBG; \
+end_device->features |= FE_SW_LRO; \
+end_device->features |= FE_QDMA; \
+end_device->features |= FE_INT_NAPI; \
+end_device->features |= FE_INT_WORKQ; \
+end_device->features |= FE_INT_TASKLET; \
+end_device->features |= FE_IRQ_SEPARATE;\
+end_device->features |= FE_ETHTOOL; \
+end_device->features |= FE_CSUM_OFFLOAD;\
+end_device->features |= FE_TSO; \
+end_device->features |= FE_TSO_V6; \
+end_device->features |= FE_HW_VLAN_TX; \
+end_device->features |= FE_HW_VLAN_RX; \
+end_device->features |= FE_QDMA_TX; \
+end_device->features |= FE_QDMA_RX; \
+end_device->features |= FE_HW_SFQ; \
+end_device->features |= FE_FPGA_MODE; \
+end_device->features |= FE_HW_NAT; \
+end_device->features |= FE_INT_NAPI_TX_RX; \
+end_device->features |= FE_INT_NAPI_RX_ONLY; \
+end_device->features |= FE_QDMA_FQOS; \
+end_device->features |= QDMA_QOS_WEB; \
+end_device->features |= QDMA_QOS_MARK; \
+end_device->features |= FE_RSS_4RING; \
+end_device->features |= FE_RSS_2RING; \
+}
+
+#define fe_architecture_config(end_device) \
+{ \
+end_device->architecture = 0; \
+end_device->architecture |= GE1_TRGMII_FORCE_2000; \
+end_device->architecture |= GE1_TRGMII_FORCE_2600; \
+}
+#endif
diff --git a/src/kernel/modules/netsys_driver/nat/include/raeth_reg.h b/src/kernel/modules/netsys_driver/nat/include/raeth_reg.h
new file mode 100755
index 0000000..8078ccf
--- /dev/null
+++ b/src/kernel/modules/netsys_driver/nat/include/raeth_reg.h
@@ -0,0 +1,1352 @@
+/* Copyright 2016 MediaTek Inc.
+ * Author: Nelson Chang <nelson.chang@mediatek.com>
+ * Author: Carlos Huang <carlos.huang@mediatek.com>
+ * Author: Harry Huang <harry.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef RAETH_REG_H
+#define RAETH_REG_H
+
+#include <linux/mii.h> /* for struct mii_if_info in ra2882ethreg.h */
+#include <linux/version.h> /* check linux version */
+#include <linux/interrupt.h> /* for "struct tasklet_struct" */
+#include <linux/ip.h>
+#include <linux/ipv6.h>
+#include <linux/workqueue.h>
+#include <linux/inet_lro.h>
+#include <linux/netdevice.h>
+#include <linux/if_vlan.h>
+
+#include "raether.h"
+
+#define MAX_PACKET_SIZE 1514
+#define MIN_PACKET_SIZE 60
+#if defined(CONFIG_MACH_MT7623) || defined(CONFIG_SOC_MT7621)
+#define MAX_PTXD_LEN 0x3fff /* 16k */
+#define MAX_QTXD_LEN 0x3fff /* 16k */
+#else
+#define MAX_PTXD_LEN 0x3fff /* 16k */
+#define MAX_QTXD_LEN 0xffff
+#endif
+
+#define phys_to_bus(a) (a)
+
+extern void __iomem *ethdma_sysctl_base;
+extern void __iomem *ethdma_frame_engine_base;
+
+/* bits range: for example BITS(16,23) = 0xFF0000
+ * ==> (BIT(m)-1) = 0x0000FFFF ~(BIT(m)-1) => 0xFFFF0000
+ * ==> (BIT(n+1)-1) = 0x00FFFFFF
+ */
+#define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n)))
+
+#define ETHER_ADDR_LEN 6
+
+/* Phy Vender ID list */
+
+#define EV_ICPLUS_PHY_ID0 0x0243
+#define EV_ICPLUS_PHY_ID1 0x0D90
+#define EV_MARVELL_PHY_ID0 0x0141
+#define EV_MARVELL_PHY_ID1 0x0CC2
+#define EV_VTSS_PHY_ID0 0x0007
+#define EV_VTSS_PHY_ID1 0x0421
+
+#define ETHSYS_BASE 0x1b000000
+#define SGMII_CONFIG_0 BIT(9) /*SGMII path enable of GMAC1*/
+#define SGMII_CONFIG_1 BIT(8) /*SGMII path enable of GMAC1*/
+
+#if defined(CONFIG_PINCTRL_MT7622)
+#define SGMII_REG_BASE0 (0x1b128000)
+#define SGMII_REG_PHYA_BASE0 (0x1b12a000)
+#define SGMII_REG_BASE1 (0)
+#define SGMII_REG_PHYA_BASE1 (0)
+#elif defined(CONFIG_MACH_LEOPARD)
+#define SGMII_REG_BASE0 (0x1b128000)
+#define SGMII_REG_PHYA_BASE0 (0x1b128100)
+#define SGMII_REG_BASE1 (0x1b130000)
+#define SGMII_REG_PHYA_BASE1 (0x1b130100)
+#else
+#define SGMII_REG_BASE0 (0)
+#define SGMII_REG_PHYA_BASE0 (0)
+#define SGMII_REG_BASE1 (0)
+#define SGMII_REG_PHYA_BASE1 (0)
+#endif
+#define ETHSYS_MAC_BASE (0x1b110000)
+
+#if defined(CONFIG_MACH_LEOPARD)
+#define FE_RSTCTL 0x1B000034
+#define INFRA_BASE 0x1000070C
+#define GEPHY_CTRL0 0x10000710
+#define GPIO_GO_BASE GEPHY_CTRL0
+#define GPIO_MODE_BASE 0x10217300
+#else
+#define INFRA_BASE 0
+#define FE_RSTCTL 0
+#define GPIO_GO_BASE 0x10211800
+#define GPIO_MODE_BASE 0x10211300
+#endif
+
+/* ETHDMASYS base address
+ * for I2S/PCM/GDMA/HSDMA/FE/GMAC
+ */
+#define ETHDMASYS_BASE ethdma_sysctl_base
+#define ETHDMASYS_FRAME_ENGINE_BASE ethdma_frame_engine_base
+
+#define ETHDMASYS_SYSCTL_BASE ETHDMASYS_BASE
+#define ETHDMASYS_PPE_BASE (ETHDMASYS_FRAME_ENGINE_BASE + 0x0C00)
+#define ETHDMASYS_ETH_MAC_BASE (ETHDMASYS_FRAME_ENGINE_BASE + 0x10000)
+#if defined(CONFIG_MACH_MT7623) || defined(CONFIG_SOC_MT7621)
+#define ETHDMASYS_ETH_SW_BASE (ETHDMASYS_FRAME_ENGINE_BASE + 0x10000)
+#else
+#define ETHDMASYS_ETH_SW_BASE (ETHDMASYS_FRAME_ENGINE_BASE + 0x18000)
+#endif
+
+#define RALINK_FRAME_ENGINE_BASE ETHDMASYS_FRAME_ENGINE_BASE
+#define RALINK_PPE_BASE ETHDMASYS_PPE_BASE
+#define RALINK_SYSCTL_BASE ETHDMASYS_SYSCTL_BASE
+#define RALINK_ETH_MAC_BASE ETHDMASYS_ETH_MAC_BASE
+#define RALINK_ETH_SW_BASE ETHDMASYS_ETH_SW_BASE
+
+#define RSTCTL_FE_RST BIT(6)
+#define RALINK_FE_RST RSTCTL_FE_RST
+
+#define RSTCTL_ETH_RST BIT(23)
+#define RALINK_ETH_RST RSTCTL_ETH_RST
+
+/* FE_INT_STATUS */
+#define RX_COHERENT BIT(31)
+#define RX_DLY_INT BIT(30)
+#define TX_COHERENT BIT(29)
+#define TX_DLY_INT BIT(28)
+#define RING3_RX_DLY_INT BIT(27)
+#define RING2_RX_DLY_INT BIT(26)
+#define RING1_RX_DLY_INT BIT(25)
+#define RING0_RX_DLY_INT BIT(30)
+
+#define RSS_RX_INT0 (RX_DONE_INT0 | RX_DONE_INT1 | \
+ RING0_RX_DLY_INT | RING1_RX_DLY_INT)
+
+#define RSS_RX_RING0 (RX_DONE_INT0 | RING0_RX_DLY_INT)
+#define RSS_RX_RING1 (RX_DONE_INT1 | RING1_RX_DLY_INT)
+#define RSS_RX_RING2 (RX_DONE_INT2 | RING2_RX_DLY_INT)
+#define RSS_RX_RING3 (RX_DONE_INT3 | RING3_RX_DLY_INT)
+
+#define RSS_RX_INT1 (RX_DONE_INT2 | RX_DONE_INT3 | \
+ RING2_RX_DLY_INT | RING3_RX_DLY_INT)
+
+#define RSS_RX_DLY_INT0 (RING0_RX_DLY_INT | RING1_RX_DLY_INT)
+#define RSS_RX_DLY_INT1 (RING2_RX_DLY_INT | RING3_RX_DLY_INT)
+
+#define RSS_RX_DLY_INT (RING0_RX_DLY_INT | RING1_RX_DLY_INT | \
+ RING2_RX_DLY_INT | RING3_RX_DLY_INT)
+
+#define RXD_ERROR BIT(24)
+#define ALT_RPLC_INT3 BIT(23)
+#define ALT_RPLC_INT2 BIT(22)
+#define ALT_RPLC_INT1 BIT(21)
+
+#define RX_DONE_INT3 BIT(19)
+#define RX_DONE_INT2 BIT(18)
+#define RX_DONE_INT1 BIT(17)
+#define RX_DONE_INT0 BIT(16)
+
+#define TX_DONE_INT3 BIT(3)
+#define TX_DONE_INT2 BIT(2)
+#define TX_DONE_INT1 BIT(1)
+#define TX_DONE_INT0 BIT(0)
+
+#define RLS_COHERENT BIT(29)
+#define RLS_DLY_INT BIT(28)
+#define RLS_DONE_INT BIT(0)
+
+#define FE_INT_ALL (TX_DONE_INT3 | TX_DONE_INT2 | \
+ TX_DONE_INT1 | TX_DONE_INT0 | \
+ RX_DONE_INT0 | RX_DONE_INT1 | \
+ RX_DONE_INT2 | RX_DONE_INT3)
+
+#define QFE_INT_ALL (RLS_DONE_INT | RX_DONE_INT0 | \
+ RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3)
+#define QFE_INT_DLY_INIT (RLS_DLY_INT | RX_DLY_INT)
+#define RX_INT_ALL (RX_DONE_INT0 | RX_DONE_INT1 | \
+ RX_DONE_INT2 | RX_DONE_INT3 | \
+ RING0_RX_DLY_INT | RING1_RX_DLY_INT | \
+ RING2_RX_DLY_INT | RING3_RX_DLY_INT | RX_DLY_INT)
+#define TX_INT_ALL (TX_DONE_INT0 | TX_DLY_INT)
+
+#define NUM_QDMA_PAGE 512
+#define QDMA_PAGE_SIZE 2048
+
+/* SW_INT_STATUS */
+#define ESW_PHY_POLLING (RALINK_ETH_MAC_BASE + 0x0000)
+#define MAC1_WOL (RALINK_ETH_SW_BASE + 0x0110)
+#define WOL_INT_CLR BIT(17)
+#define WOL_INT_EN BIT(1)
+#define WOL_EN BIT(0)
+
+#define P5_LINK_CH BIT(5)
+#define P4_LINK_CH BIT(4)
+#define P3_LINK_CH BIT(3)
+#define P2_LINK_CH BIT(2)
+#define P1_LINK_CH BIT(1)
+#define P0_LINK_CH BIT(0)
+
+#define RX_BUF_ALLOC_SIZE 2000
+#define FASTPATH_HEADROOM 64
+
+#define ETHER_BUFFER_ALIGN 32 /* /// Align on a cache line */
+
+#define ETHER_ALIGNED_RX_SKB_ADDR(addr) \
+ ((((unsigned long)(addr) + ETHER_BUFFER_ALIGN - 1) & \
+ ~(ETHER_BUFFER_ALIGN - 1)) - (unsigned long)(addr))
+
+struct PSEUDO_ADAPTER {
+ struct net_device *raeth_dev;
+ struct net_device *pseudo_dev;
+ struct net_device_stats stat;
+ struct mii_if_info mii_info;
+};
+
+#define MAX_PSEUDO_ENTRY 1
+
+/* Register Categories Definition */
+#define RAFRAMEENGINE_OFFSET 0x0000
+#define RAGDMA_OFFSET 0x0020
+#define RAPSE_OFFSET 0x0040
+#define RAGDMA2_OFFSET 0x0060
+#define RACDMA_OFFSET 0x0080
+#define RAPDMA_OFFSET 0x0800
+#define SDM_OFFSET 0x0C00
+#define RAPPE_OFFSET 0x0200
+#define RACMTABLE_OFFSET 0x0400
+#define RAPOLICYTABLE_OFFSET 0x1000
+
+/* Register Map Detail */
+/* RT3883 */
+#define SYSCFG1 (RALINK_SYSCTL_BASE + 0x14)
+
+#define FE_PSE_FREE (RALINK_FRAME_ENGINE_BASE + 0x240)
+#define FE_DROP_FQ (RALINK_FRAME_ENGINE_BASE + 0x244)
+#define FE_DROP_FC (RALINK_FRAME_ENGINE_BASE + 0x248)
+#define FE_DROP_PPE (RALINK_FRAME_ENGINE_BASE + 0x24c)
+#define FE_INT_GRP (RALINK_FRAME_ENGINE_BASE + 0x20)
+/* Old FE with New PDMA */
+#define PDMA_RELATED 0x0800
+/* 1. PDMA */
+#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x000)
+#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x004)
+#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x008)
+#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x00C)
+
+#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x010)
+#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x014)
+#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x018)
+#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x01C)
+
+#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x020)
+#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x024)
+#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x028)
+#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x02C)
+
+#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x030)
+#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x034)
+#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x038)
+#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x03C)
+
+#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x100)
+#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x104)
+#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x108)
+#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x10C)
+
+#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x110)
+#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x114)
+#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x118)
+#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x11C)
+
+#define RX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x120)
+#define RX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x124)
+#define RX_CALC_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x128)
+#define RX_DRX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x12C)
+
+#define RX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x130)
+#define RX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x134)
+#define RX_CALC_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x138)
+#define RX_DRX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x13C)
+
+#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x200)
+#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x204)
+#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x208)
+#define PDMA_RST_CFG (PDMA_RST_IDX)
+#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x20C)
+#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x210)
+#define INT_STATUS (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x220)
+#define FE_INT_STATUS (INT_STATUS)
+#define INT_MASK (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED + 0x228)
+#define FE_INT_ENABLE (INT_MASK)
+#define SCH_Q01_CFG (RALINK_FRAME_ENGINE_BASE + RAPDMA_OFFSET + 0x280)
+#define SCH_Q23_CFG (RALINK_FRAME_ENGINE_BASE + RAPDMA_OFFSET + 0x284)
+
+#define PDMA_INT_GRP1 (RALINK_FRAME_ENGINE_BASE + RAPDMA_OFFSET + 0x250)
+#define PDMA_INT_GRP2 (RALINK_FRAME_ENGINE_BASE + RAPDMA_OFFSET + 0x254)
+#define PDMA_INT_GRP3 (RALINK_FRAME_ENGINE_BASE + RAPDMA_OFFSET + 0x22c)
+
+#define FE_GLO_CFG (RALINK_FRAME_ENGINE_BASE + 0x00)
+#define FE_RST_GL (RALINK_FRAME_ENGINE_BASE + 0x04)
+#define FE_INT_STATUS2 (RALINK_FRAME_ENGINE_BASE + 0x08)
+#define FE_INT_ENABLE2 (RALINK_FRAME_ENGINE_BASE + 0x0c)
+#define MAC1_LINK BIT(24)
+#define MAC2_LINK BIT(25)
+/* #define FC_DROP_STA RALINK_FRAME_ENGINE_BASE + 0x18 */
+#define FOE_TS_T (RALINK_FRAME_ENGINE_BASE + 0x10)
+
+#define FE_GLO_MISC (RALINK_FRAME_ENGINE_BASE + 0x124)
+
+#define GDMA1_RELATED 0x0500
+#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
+#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
+#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
+#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
+
+#define GDMA2_RELATED 0x1500
+#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
+#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
+#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
+#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
+
+#define GDMA1_SCH_CFG GDMA1_SHPR_CFG
+#define GDMA2_SCH_CFG GDMA2_SHPR_CFG
+
+#define PSE_RELATED 0x0040
+#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
+#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
+#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
+#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x0C)
+#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x10)
+#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x14)
+#define GDMA2_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x18)
+#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x1C)
+
+#define CDMA_RELATED 0x0400
+#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
+#define CDMP_IG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
+#define CDMP_EG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
+
+#define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE + 0x100)
+
+/*kurtis: add QDMA define*/
+#define CLK_CFG_0 (RALINK_SYSCTL_BASE + 0x2C)
+#define PAD_RGMII2_MDIO_CFG (RALINK_SYSCTL_BASE + 0x58)
+
+#define QDMA_RELATED 0x1800
+#define QTX_CFG_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x000)
+#define QTX_SCH_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x004)
+#define QTX_HEAD_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x008)
+#define QTX_TAIL_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x00C)
+#define QTX_CFG_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x010)
+#define QTX_SCH_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x014)
+#define QTX_HEAD_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x018)
+#define QTX_TAIL_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x01C)
+#define QTX_CFG_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x020)
+#define QTX_SCH_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x024)
+#define QTX_HEAD_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x028)
+#define QTX_TAIL_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x02C)
+#define QTX_CFG_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x030)
+#define QTX_SCH_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x034)
+#define QTX_HEAD_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x038)
+#define QTX_TAIL_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x03C)
+#define QTX_CFG_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x040)
+#define QTX_SCH_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x044)
+#define QTX_HEAD_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x048)
+#define QTX_TAIL_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x04C)
+#define QTX_CFG_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x050)
+#define QTX_SCH_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x054)
+#define QTX_HEAD_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x058)
+#define QTX_TAIL_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x05C)
+#define QTX_CFG_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x060)
+#define QTX_SCH_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x064)
+#define QTX_HEAD_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x068)
+#define QTX_TAIL_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x06C)
+#define QTX_CFG_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x070)
+#define QTX_SCH_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x074)
+#define QTX_HEAD_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x078)
+#define QTX_TAIL_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x07C)
+#define QTX_CFG_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x080)
+#define QTX_SCH_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x084)
+#define QTX_HEAD_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x088)
+#define QTX_TAIL_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x08C)
+#define QTX_CFG_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x090)
+#define QTX_SCH_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x094)
+#define QTX_HEAD_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x098)
+#define QTX_TAIL_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x09C)
+#define QTX_CFG_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A0)
+#define QTX_SCH_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A4)
+#define QTX_HEAD_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A8)
+#define QTX_TAIL_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0AC)
+#define QTX_CFG_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B0)
+#define QTX_SCH_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B4)
+#define QTX_HEAD_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B8)
+#define QTX_TAIL_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0BC)
+#define QTX_CFG_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C0)
+#define QTX_SCH_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C4)
+#define QTX_HEAD_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C8)
+#define QTX_TAIL_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0CC)
+#define QTX_CFG_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D0)
+#define QTX_SCH_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D4)
+#define QTX_HEAD_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D8)
+#define QTX_TAIL_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0DC)
+#define QTX_CFG_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E0)
+#define QTX_SCH_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E4)
+#define QTX_HEAD_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E8)
+#define QTX_TAIL_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0EC)
+#define QTX_CFG_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F0)
+#define QTX_SCH_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F4)
+#define QTX_HEAD_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F8)
+#define QTX_TAIL_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0FC)
+#define QRX_BASE_PTR_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x100)
+#define QRX_MAX_CNT_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x104)
+#define QRX_CRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x108)
+#define QRX_DRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x10C)
+#define QRX_BASE_PTR_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x110)
+#define QRX_MAX_CNT_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x114)
+#define QRX_CRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x118)
+#define QRX_DRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x11C)
+
+#define VQTX_TB_BASE_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x180)
+#define VQTX_TB_BASE_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x184)
+#define VQTX_TB_BASE_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x188)
+#define VQTX_TB_BASE_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x18C)
+
+#define QDMA_INFO (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x200)
+#define QDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x204)
+#define QDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x208)
+#define QDMA_RST_CFG (QDMA_RST_IDX)
+#define QDMA_DELAY_INT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x20C)
+#define QDMA_FC_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x210)
+#define QDMA_TX_SCH (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x214)
+#define QDMA_INT_STS (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x218)
+#define QFE_INT_STATUS (QDMA_INT_STS)
+#define QDMA_INT_MASK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x21C)
+#define QFE_INT_ENABLE (QDMA_INT_MASK)
+#define QDMA_TRTCM (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x220)
+#define QDMA_DATA0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x224)
+#define QDMA_DATA1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x228)
+#define QDMA_RED_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x22C)
+#define QDMA_TEST (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x230)
+#define QDMA_DMA (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x234)
+#define QDMA_BMU (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x238)
+#define QDMA_HRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x240)
+#define QDMA_HRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x244)
+#define QDMA_SRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x248)
+#define QDMA_SRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x24C)
+#define QTX_MIB_IF (RALINK_FRAME_ENGINE_BASE + 0x1abc)
+#define QTX_CTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x300)
+#define QTX_DTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x304)
+#define QTX_FWD_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x308)
+#define QTX_CRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x310)
+#define QTX_DRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x314)
+#define QTX_RLS_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x318)
+#define QDMA_FQ_HEAD (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x320)
+#define QDMA_FQ_TAIL (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x324)
+#define QDMA_FQ_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x328)
+#define QDMA_FQ_BLEN (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x32C)
+#define QTX_Q0MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x350)
+#define QTX_Q1MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x354)
+#define QTX_Q2MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x358)
+#define QTX_Q3MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x35C)
+#define QTX_Q0MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x360)
+#define QTX_Q1MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x364)
+#define QTX_Q2MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x368)
+#define QTX_Q3MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x36C)
+#define QDMA_INT_GRP1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x220)
+#define QDMA_INT_GRP2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x224)
+
+#define DELAY_INT_INIT 0x8f0f8f0f
+#define FE_INT_DLY_INIT (TX_DLY_INT | RX_DLY_INT)
+#define RSS_INT_DLY_INT_2RING (RING0_RX_DLY_INT | RING1_RX_DLY_INT)
+#define RSS_INT_DLY_INT (RING0_RX_DLY_INT | RING1_RX_DLY_INT | \
+ RING2_RX_DLY_INT | RING3_RX_DLY_INT | TX_DLY_INT)
+/* 6. Counter and Meter Table */
+/* PPE Accounting Group 0 Byte Cnt */
+#define PPE_AC_BCNT0 (RALINK_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x000)
+/* PPE Accounting Group 0 Packet Cnt */
+#define PPE_AC_PCNT0 (RALINK_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x004)
+/* 0 ~ 63 */
+#define PPE_MTR_CNT0 (RALINK_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x200)
+/* skip... */
+#define PPE_MTR_CNT63 (RALINK_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x2FC)
+
+/* Transmit good byte cnt for GEport */
+#define GDMA_TX_GBCNT0 (RALINK_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x300)
+/* Transmit good pkt cnt for GEport */
+#define GDMA_TX_GPCNT0 (RALINK_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x304)
+/* Transmit skip cnt for GEport */
+#define GDMA_TX_SKIPCNT0 (RALINK_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x308)
+/* Transmit collision cnt for GEport */
+#define GDMA_TX_COLCNT0 (RALINK_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x30C)
+
+/* update these address mapping to fit data sheet v0.26,
+ * by bobtseng, 2007.6.14
+ */
+#define GDMA_RX_GBCNT0 (RALINK_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x320)
+#define GDMA_RX_GPCNT0 (RALINK_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x324)
+#define GDMA_RX_OERCNT0 (RALINK_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x328)
+#define GDMA_RX_FERCNT0 (RALINK_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x32C)
+#define GDMA_RX_SERCNT0 (RALINK_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x330)
+#define GDMA_RX_LERCNT0 (RALINK_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x334)
+#define GDMA_RX_CERCNT0 (RALINK_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x338)
+#define GDMA_RX_FCCNT1 (RALINK_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x33C)
+
+/* LRO global control */
+/* Bits [15:0]:LRO_ALT_RFSH_TIMER, Bits [20:16]:LRO_ALT_TICK_TIMER */
+#define LRO_ALT_REFRESH_TIMER (RALINK_FRAME_ENGINE_BASE + 0x001C)
+
+/* LRO auto-learn table info */
+#define PDMA_FE_ALT_CF8 (RALINK_FRAME_ENGINE_BASE + 0x0300)
+#define PDMA_FE_ALT_SGL_CFC (RALINK_FRAME_ENGINE_BASE + 0x0304)
+#define PDMA_FE_ALT_SEQ_CFC (RALINK_FRAME_ENGINE_BASE + 0x0308)
+
+/* LRO controls */
+#define ADMA_LRO_CTRL_OFFSET 0x0980
+/*Bit [0]:LRO_EN, Bit [1]:LRO_IPv6_EN, Bit [2]:MULTIPLE_NON_LRO_RX_RING_EN,
+ * Bit [3]:MULTIPLE_RXD_PREFETCH_EN, Bit [4]:RXD_PREFETCH_EN,
+ * Bit [5]:LRO_DLY_INT_EN, Bit [6]:LRO_CRSN_BNW, Bit [7]:L3_CKS_UPD_EN,
+ * Bit [20]:first_ineligible_pkt_redirect_en, Bit [21]:cr_lro_alt_score_mode,
+ * Bit [22]:cr_lro_alt_rplc_mode, Bit [23]:cr_lro_l4_ctrl_psh_en,
+ * Bits [28:26]:LRO_RING_RELINGUISH_REQ, Bits [31:29]:LRO_RING_RELINGUISH_DONE
+ */
+#define ADMA_LRO_CTRL_DW0 (RALINK_FRAME_ENGINE_BASE + \
+ ADMA_LRO_CTRL_OFFSET + 0x00)
+/* Bits [31:0]:LRO_CPU_REASON */
+#define ADMA_LRO_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE + \
+ ADMA_LRO_CTRL_OFFSET + 0x04)
+/* Bits [31:0]:AUTO_LEARN_LRO_ELIGIBLE_THRESHOLD */
+#define ADMA_LRO_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE + \
+ ADMA_LRO_CTRL_OFFSET + 0x08)
+/*Bits [7:0]:LRO_MAX_AGGREGATED_CNT,
+ * Bits [11:8]:LRO_VLAN_EN, Bits [13:12]:LRO_VLAN_VID_CMP_DEPTH,
+ * Bit [14]:ADMA_FW_RSTN_REQ, Bit [15]:ADMA_MODE, Bits [31:16]:LRO_MIN_RXD_SDL0
+ */
+#define ADMA_LRO_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE + \
+ ADMA_LRO_CTRL_OFFSET + 0x0C)
+
+/* LRO RX delay interrupt configurations */
+#define LRO_RX1_DLY_INT (RALINK_FRAME_ENGINE_BASE + 0x0a70)
+#define LRO_RX2_DLY_INT (RALINK_FRAME_ENGINE_BASE + 0x0a74)
+#define LRO_RX3_DLY_INT (RALINK_FRAME_ENGINE_BASE + 0x0a78)
+
+/* LRO auto-learn configurations */
+#define PDMA_LRO_ATL_OVERFLOW_ADJ_OFFSET 0x0990
+#define PDMA_LRO_ATL_OVERFLOW_ADJ (RALINK_FRAME_ENGINE_BASE + \
+ PDMA_LRO_ATL_OVERFLOW_ADJ_OFFSET)
+#define LRO_ALT_SCORE_DELTA (RALINK_FRAME_ENGINE_BASE + 0x0a4c)
+
+/* LRO agg timer configurations */
+#define LRO_MAX_AGG_TIME (RALINK_FRAME_ENGINE_BASE + 0x0a5c)
+
+/* LRO configurations of RX ring #0 */
+#define LRO_RXRING0_OFFSET 0x0b00
+#define LRO_RX_RING0_DIP_DW0 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING0_OFFSET + 0x04)
+#define LRO_RX_RING0_DIP_DW1 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING0_OFFSET + 0x08)
+#define LRO_RX_RING0_DIP_DW2 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING0_OFFSET + 0x0C)
+#define LRO_RX_RING0_DIP_DW3 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING0_OFFSET + 0x10)
+#define LRO_RX_RING0_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING0_OFFSET + 0x28)
+/* Bit [8]:RING0_VLD, Bit [9]:RING0_MYIP_VLD */
+#define LRO_RX_RING0_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING0_OFFSET + 0x2C)
+#define LRO_RX_RING0_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING0_OFFSET + 0x30)
+/* LRO configurations of RX ring #1 */
+#define LRO_RXRING1_OFFSET 0x0b40
+#define LRO_RX_RING1_STP_DTP_DW (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING1_OFFSET + 0x00)
+#define LRO_RX_RING1_DIP_DW0 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING1_OFFSET + 0x04)
+#define LRO_RX_RING1_DIP_DW1 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING1_OFFSET + 0x08)
+#define LRO_RX_RING1_DIP_DW2 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING1_OFFSET + 0x0C)
+#define LRO_RX_RING1_DIP_DW3 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING1_OFFSET + 0x10)
+#define LRO_RX_RING1_SIP_DW0 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING1_OFFSET + 0x14)
+#define LRO_RX_RING1_SIP_DW1 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING1_OFFSET + 0x18)
+#define LRO_RX_RING1_SIP_DW2 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING1_OFFSET + 0x1C)
+#define LRO_RX_RING1_SIP_DW3 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING1_OFFSET + 0x20)
+#define LRO_RX_RING1_CTRL_DW0 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING1_OFFSET + 0x24)
+#define LRO_RX_RING1_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING1_OFFSET + 0x28)
+#define LRO_RX_RING1_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING1_OFFSET + 0x2C)
+#define LRO_RX_RING1_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING1_OFFSET + 0x30)
+#define LRO_RXRING2_OFFSET 0x0b80
+#define LRO_RX_RING2_STP_DTP_DW (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING2_OFFSET + 0x00)
+#define LRO_RX_RING2_DIP_DW0 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING2_OFFSET + 0x04)
+#define LRO_RX_RING2_DIP_DW1 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING2_OFFSET + 0x08)
+#define LRO_RX_RING2_DIP_DW2 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING2_OFFSET + 0x0C)
+#define LRO_RX_RING2_DIP_DW3 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING2_OFFSET + 0x10)
+#define LRO_RX_RING2_SIP_DW0 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING2_OFFSET + 0x14)
+#define LRO_RX_RING2_SIP_DW1 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING2_OFFSET + 0x18)
+#define LRO_RX_RING2_SIP_DW2 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING2_OFFSET + 0x1C)
+#define LRO_RX_RING2_SIP_DW3 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING2_OFFSET + 0x20)
+#define LRO_RX_RING2_CTRL_DW0 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING2_OFFSET + 0x24)
+#define LRO_RX_RING2_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING2_OFFSET + 0x28)
+#define LRO_RX_RING2_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING2_OFFSET + 0x2C)
+#define LRO_RX_RING2_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING2_OFFSET + 0x30)
+#define LRO_RXRING3_OFFSET 0x0bc0
+#define LRO_RX_RING3_STP_DTP_DW (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING3_OFFSET + 0x00)
+#define LRO_RX_RING3_DIP_DW0 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING3_OFFSET + 0x04)
+#define LRO_RX_RING3_DIP_DW1 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING3_OFFSET + 0x08)
+#define LRO_RX_RING3_DIP_DW2 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING3_OFFSET + 0x0C)
+#define LRO_RX_RING3_DIP_DW3 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING3_OFFSET + 0x10)
+#define LRO_RX_RING3_SIP_DW0 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING3_OFFSET + 0x14)
+#define LRO_RX_RING3_SIP_DW1 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING3_OFFSET + 0x18)
+#define LRO_RX_RING3_SIP_DW2 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING3_OFFSET + 0x1C)
+#define LRO_RX_RING3_SIP_DW3 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING3_OFFSET + 0x20)
+#define LRO_RX_RING3_CTRL_DW0 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING3_OFFSET + 0x24)
+#define LRO_RX_RING3_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING3_OFFSET + 0x28)
+#define LRO_RX_RING3_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING3_OFFSET + 0x2C)
+#define LRO_RX_RING3_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE + \
+ LRO_RXRING3_OFFSET + 0x30)
+
+#define ADMA_DBG_OFFSET 0x0a30
+#define ADMA_TX_DBG0 (RALINK_FRAME_ENGINE_BASE + ADMA_DBG_OFFSET + 0x00)
+#define ADMA_TX_DBG1 (RALINK_FRAME_ENGINE_BASE + ADMA_DBG_OFFSET + 0x04)
+#define ADMA_RX_DBG0 (RALINK_FRAME_ENGINE_BASE + ADMA_DBG_OFFSET + 0x08)
+#define ADMA_RX_DBG1 (RALINK_FRAME_ENGINE_BASE + ADMA_DBG_OFFSET + 0x0C)
+
+/********RSS CR ************/
+#define ADMA_RSS_OFFSET 0x3000
+#define ADMA_RSS_GLO_CFG (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x00)
+#define ADMA_RSS_INDR_TABLE_DW0 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x50)
+#define ADMA_RSS_INDR_TABLE_DW1 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x54)
+#define ADMA_RSS_INDR_TABLE_DW2 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x58)
+#define ADMA_RSS_INDR_TABLE_DW3 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x5C)
+#define ADMA_RSS_INDR_TABLE_DW4 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x60)
+#define ADMA_RSS_INDR_TABLE_DW5 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x64)
+#define ADMA_RSS_INDR_TABLE_DW6 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x68)
+#define ADMA_RSS_INDR_TABLE_DW7 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x6C)
+
+#define ADMA_RSS_HASH_KEY_DW0 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x20)
+#define ADMA_RSS_HASH_KEY_DW1 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x24)
+#define ADMA_RSS_HASH_KEY_DW2 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x28)
+#define ADMA_RSS_HASH_KEY_DW3 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x2C)
+#define ADMA_RSS_HASH_KEY_DW4 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x30)
+#define ADMA_RSS_HASH_KEY_DW5 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x34)
+#define ADMA_RSS_HASH_KEY_DW6 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x38)
+#define ADMA_RSS_HASH_KEY_DW7 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x3C)
+#define ADMA_RSS_HASH_KEY_DW8 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x40)
+#define ADMA_RSS_HASH_KEY_DW9 (RALINK_FRAME_ENGINE_BASE + ADMA_RSS_OFFSET + 0x44)
+/* LRO RX ring mode */
+#define PDMA_RX_NORMAL_MODE (0x0)
+#define PDMA_RX_PSE_MODE (0x1)
+#define PDMA_RX_FORCE_PORT (0x2)
+#define PDMA_RX_AUTO_LEARN (0x3)
+
+#define ADMA_RX_RING0 (0)
+#define ADMA_RX_RING1 (1)
+#define ADMA_RX_RING2 (2)
+#define ADMA_RX_RING3 (3)
+
+#define ADMA_RX_LEN0_MASK (0x3fff)
+#define ADMA_RX_LEN1_MASK (0x3)
+
+#define SET_ADMA_RX_LEN0(x) ((x) & ADMA_RX_LEN0_MASK)
+#define SET_ADMA_RX_LEN1(x) ((x) & ADMA_RX_LEN1_MASK)
+
+#define QDMA_PAGE (ETHDMASYS_FRAME_ENGINE_BASE + 0x19f0)
+
+/*SFQ use*/
+#define VQTX_TB_BASE0 (ETHDMASYS_FRAME_ENGINE_BASE + 0x1980)
+#define VQTX_TB_BASE1 (ETHDMASYS_FRAME_ENGINE_BASE + 0x1984)
+#define VQTX_TB_BASE2 (ETHDMASYS_FRAME_ENGINE_BASE + 0x1988)
+#define VQTX_TB_BASE3 (ETHDMASYS_FRAME_ENGINE_BASE + 0x198C)
+#define SFQ_OFFSET 0x1A80
+#define VQTX_GLO (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET)
+#define VQTX_INVLD_PTR (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x0C)
+#define VQTX_NUM (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x10)
+#define VQTX_SCH (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x18)
+#define VQTX_HASH_CFG (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x20)
+#define VQTX_HASH_SD (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x24)
+#define VQTX_VLD_CFG (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x30)
+#define VQTX_MIB_IF (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x3C)
+#define VQTX_MIB_PCNT (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x40)
+#define VQTX_MIB_BCNT0 (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x44)
+#define VQTX_MIB_BCNT1 (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x48)
+#define VQTX_0_BIND_QID (PQ0 << 0)
+#define VQTX_1_BIND_QID (PQ1 << 8)
+#define VQTX_2_BIND_QID (PQ2 << 16)
+#define VQTX_3_BIND_QID (PQ3 << 24)
+#define VQTX_4_BIND_QID (PQ4 << 0)
+#define VQTX_5_BIND_QID (PQ5 << 8)
+#define VQTX_6_BIND_QID (PQ6 << 16)
+#define VQTX_7_BIND_QID (PQ7 << 24)
+#define VQTX_TB_BASE4 (ETHDMASYS_FRAME_ENGINE_BASE + 0x1990)
+#define VQTX_TB_BASE5 (ETHDMASYS_FRAME_ENGINE_BASE + 0x1994)
+#define VQTX_TB_BASE6 (ETHDMASYS_FRAME_ENGINE_BASE + 0x1998)
+#define VQTX_TB_BASE7 (ETHDMASYS_FRAME_ENGINE_BASE + 0x199C)
+#define VQTX_0_3_BIND_QID (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x140)
+#define VQTX_4_7_BIND_QID (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x144)
+#define PQ0 0
+#define PQ1 1
+#define PQ2 15
+#define PQ3 16
+#define PQ4 30
+#define PQ5 31
+#define PQ6 43
+#define PQ7 63
+
+#if defined(CONFIG_MACH_MT7623)
+#define VQ_NUM0 256
+#define VQ_NUM1 256
+#define VQ_NUM2 256
+#define VQ_NUM3 256
+#define VQ_NUM4 0
+#define VQ_NUM5 0
+#define VQ_NUM6 0
+#define VQ_NUM7 0
+#define VQTX_NUM_0 (4 << 0)
+#define VQTX_NUM_1 (4 << 4)
+#define VQTX_NUM_2 (4 << 8)
+#define VQTX_NUM_3 (4 << 12)
+#define VQTX_NUM_4 0
+#define VQTX_NUM_5 0
+#define VQTX_NUM_6 0
+#define VQTX_NUM_7 0
+#else
+#define VQ_NUM0 128
+#define VQ_NUM1 128
+#define VQ_NUM2 128
+#define VQ_NUM3 128
+#define VQ_NUM4 128
+#define VQ_NUM5 128
+#define VQ_NUM6 128
+#define VQ_NUM7 128
+#define VQTX_NUM_0 (3 << 0)
+#define VQTX_NUM_1 (3 << 4)
+#define VQTX_NUM_2 (3 << 8)
+#define VQTX_NUM_3 (3 << 12)
+#define VQTX_NUM_4 (3 << 16)
+#define VQTX_NUM_5 (3 << 20)
+#define VQTX_NUM_6 (3 << 24)
+#define VQTX_NUM_7 (3 << 28)
+#endif
+
+#define VQTX_MIB_EN BIT(17)
+
+/*HW IO-COHERNET BASE address*/
+#if defined(CONFIG_MACH_LEOPARD)
+#define HW_IOC_BASE 0x1B000080
+#define IOC_OFFSET 4
+#else
+#define HW_IOC_BASE 0x1B000400
+#define IOC_OFFSET 8
+#endif
+
+/*=========================================
+ * SFQ Table Format define
+ *=========================================
+ */
+struct SFQ_INFO1_T {
+ unsigned int VQHPTR;
+};
+
+struct SFQ_INFO2_T {
+ unsigned int VQTPTR;
+};
+
+struct SFQ_INFO3_T {
+ unsigned int QUE_DEPTH:16;
+ unsigned int DEFICIT_CNT:16;
+};
+
+struct SFQ_INFO4_T {
+ unsigned int RESV;
+};
+
+struct SFQ_INFO5_T {
+ unsigned int PKT_CNT;
+};
+
+struct SFQ_INFO6_T {
+ unsigned int BYTE_CNT;
+};
+
+struct SFQ_INFO7_T {
+ unsigned int BYTE_CNT;
+};
+
+struct SFQ_INFO8_T {
+ unsigned int RESV;
+};
+
+struct SFQ_table {
+ struct SFQ_INFO1_T sfq_info1;
+ struct SFQ_INFO2_T sfq_info2;
+ struct SFQ_INFO3_T sfq_info3;
+ struct SFQ_INFO4_T sfq_info4;
+ struct SFQ_INFO5_T sfq_info5;
+ struct SFQ_INFO6_T sfq_info6;
+ struct SFQ_INFO7_T sfq_info7;
+ struct SFQ_INFO8_T sfq_info8;
+};
+
+#if defined(CONFIG_RAETH_HW_LRO) || defined(CONFIG_RAETH_MULTIPLE_RX_RING)
+#define FE_GDM_RXID1_OFFSET (0x0130)
+#define FE_GDM_RXID1 (RALINK_FRAME_ENGINE_BASE + FE_GDM_RXID1_OFFSET)
+#define GDM_VLAN_PRI7_RXID_SEL BITS(30, 31)
+#define GDM_VLAN_PRI6_RXID_SEL BITS(28, 29)
+#define GDM_VLAN_PRI5_RXID_SEL BITS(26, 27)
+#define GDM_VLAN_PRI4_RXID_SEL BITS(24, 25)
+#define GDM_VLAN_PRI3_RXID_SEL BITS(22, 23)
+#define GDM_VLAN_PRI2_RXID_SEL BITS(20, 21)
+#define GDM_VLAN_PRI1_RXID_SEL BITS(18, 19)
+#define GDM_VLAN_PRI0_RXID_SEL BITS(16, 17)
+#define GDM_TCP_ACK_RXID_SEL BITS(4, 5)
+#define GDM_TCP_ACK_WZPC BIT(3)
+#define GDM_RXID_PRI_SEL BITS(0, 2)
+
+#define FE_GDM_RXID2_OFFSET (0x0134)
+#define FE_GDM_RXID2 (RALINK_FRAME_ENGINE_BASE + FE_GDM_RXID2_OFFSET)
+#define GDM_STAG7_RXID_SEL BITS(30, 31)
+#define GDM_STAG6_RXID_SEL BITS(28, 29)
+#define GDM_STAG5_RXID_SEL BITS(26, 27)
+#define GDM_STAG4_RXID_SEL BITS(24, 25)
+#define GDM_STAG3_RXID_SEL BITS(22, 23)
+#define GDM_STAG2_RXID_SEL BITS(20, 21)
+#define GDM_STAG1_RXID_SEL BITS(18, 19)
+#define GDM_STAG0_RXID_SEL BITS(16, 17)
+#define GDM_PID2_RXID_SEL BITS(2, 3)
+#define GDM_PID1_RXID_SEL BITS(0, 1)
+
+#define GDM_PRI_PID (0)
+#define GDM_PRI_VLAN_PID (1)
+#define GDM_PRI_ACK_PID (2)
+#define GDM_PRI_VLAN_ACK_PID (3)
+#define GDM_PRI_ACK_VLAN_PID (4)
+
+#define SET_GDM_VLAN_PRI_RXID_SEL(x, y) \
+{ \
+unsigned int reg_val = sys_reg_read(FE_GDM_RXID1); \
+reg_val &= ~(0x03 << (((x) << 1) + 16)); \
+reg_val |= ((y) & 0x3) << (((x) << 1) + 16); \
+sys_reg_write(FE_GDM_RXID1, reg_val); \
+}
+
+#define SET_GDM_TCP_ACK_RXID_SEL(x) \
+{ \
+unsigned int reg_val = sys_reg_read(FE_GDM_RXID1); \
+reg_val &= ~(GDM_TCP_ACK_RXID_SEL); \
+reg_val |= ((x) & 0x3) << 4; \
+sys_reg_write(FE_GDM_RXID1, reg_val); \
+}
+
+#define SET_GDM_TCP_ACK_WZPC(x) \
+{ \
+unsigned int reg_val = sys_reg_read(FE_GDM_RXID1); \
+reg_val &= ~(GDM_TCP_ACK_WZPC); \
+reg_val |= ((x) & 0x1) << 3; \
+sys_reg_write(FE_GDM_RXID1, reg_val); \
+}
+
+#define SET_GDM_RXID_PRI_SEL(x) \
+{ \
+unsigned int reg_val = sys_reg_read(FE_GDM_RXID1); \
+reg_val &= ~(GDM_RXID_PRI_SEL); \
+reg_val |= (x) & 0x7; \
+sys_reg_write(FE_GDM_RXID1, reg_val); \
+}
+
+#define GDM_STAG_RXID_SEL(x, y) \
+{ \
+unsigned int reg_val = sys_reg_read(FE_GDM_RXID2); \
+reg_val &= ~(0x03 << (((x) << 1) + 16)); \
+reg_val |= ((y) & 0x3) << (((x) << 1) + 16); \
+sys_reg_write(FE_GDM_RXID2, reg_val); \
+}
+
+#define SET_GDM_PID2_RXID_SEL(x) \
+{ \
+unsigned int reg_val = sys_reg_read(FE_GDM_RXID2); \
+reg_val &= ~(GDM_PID2_RXID_SEL); \
+reg_val |= ((x) & 0x3) << 2; \
+sys_reg_write(FE_GDM_RXID2, reg_val); \
+}
+
+#define SET_GDM_PID1_RXID_SEL(x) \
+{ \
+unsigned int reg_val = sys_reg_read(FE_GDM_RXID2); \
+reg_val &= ~(GDM_PID1_RXID_SEL); \
+reg_val |= ((x) & 0x3); \
+sys_reg_write(FE_GDM_RXID2, reg_val); \
+}
+
+#endif /* CONFIG_RAETH_MULTIPLE_RX_RING */
+/* Per Port Packet Counts in RT3052, added by bobtseng 2009.4.17. */
+#define PORT0_PKCOUNT (0xb01100e8)
+#define PORT1_PKCOUNT (0xb01100ec)
+#define PORT2_PKCOUNT (0xb01100f0)
+#define PORT3_PKCOUNT (0xb01100f4)
+#define PORT4_PKCOUNT (0xb01100f8)
+#define PORT5_PKCOUNT (0xb01100fc)
+
+#define sys_reg_read(phys) (__raw_readl((void __iomem *)phys))
+#define sys_reg_write(phys, val) (__raw_writel(val, (void __iomem *)phys))
+
+/* ====================================== */
+#define GDM1_DISPAD BIT(18)
+#define GDM1_DISCRC BIT(17)
+
+/* GDMA1 uni-cast frames destination port */
+#define GDM1_ICS_EN (0x1 << 22)
+#define GDM1_TCS_EN (0x1 << 21)
+#define GDM1_UCS_EN (0x1 << 20)
+#define GDM1_JMB_EN (0x1 << 19)
+#define GDM1_STRPCRC (0x1 << 16)
+#define GDM1_UFRC_P_CPU (0 << 12)
+
+/* GDMA1 broad-cast MAC address frames */
+#define GDM1_BFRC_P_CPU (0 << 8)
+
+/* GDMA1 multi-cast MAC address frames */
+#define GDM1_MFRC_P_CPU (0 << 4)
+
+/* GDMA1 other MAC address frames destination port */
+#define GDM1_OFRC_P_CPU (0 << 0)
+
+/* checksum generator registers are removed */
+#define ICS_GEN_EN (0 << 2)
+#define UCS_GEN_EN (0 << 1)
+#define TCS_GEN_EN (0 << 0)
+
+/* MDIO_CFG bit */
+#define MDIO_CFG_GP1_FC_TX BIT(11)
+#define MDIO_CFG_GP1_FC_RX BIT(10)
+
+/* ====================================== */
+/* ====================================== */
+#define GP1_LNK_DWN BIT(9)
+#define GP1_AN_FAIL BIT(8)
+/* ====================================== */
+/* ====================================== */
+#define PSE_RESET BIT(0)
+/* ====================================== */
+#define PST_DRX_IDX3 BIT(19)
+#define PST_DRX_IDX2 BIT(18)
+#define PST_DRX_IDX1 BIT(17)
+#define PST_DRX_IDX0 BIT(16)
+#define PST_DTX_IDX3 BIT(3)
+#define PST_DTX_IDX2 BIT(2)
+#define PST_DTX_IDX1 BIT(1)
+#define PST_DTX_IDX0 BIT(0)
+
+#define RX_2B_OFFSET BIT(31)
+#define CSR_CLKGATE_BYP BIT(30)
+#define MULTI_EN BIT(10)
+#define DESC_32B_EN BIT(8)
+#define TX_WB_DDONE BIT(6)
+#define RX_DMA_BUSY BIT(3)
+#define TX_DMA_BUSY BIT(1)
+#define RX_DMA_EN BIT(2)
+#define TX_DMA_EN BIT(0)
+
+#define PDMA_BT_SIZE_4DWORDS (0 << 4)
+#define PDMA_BT_SIZE_8DWORDS BIT(4)
+#define PDMA_BT_SIZE_16DWORDS (2 << 4)
+#define PDMA_BT_SIZE_32DWORDS (3 << 4)
+
+#define ADMA_RX_BT_SIZE_4DWORDS (0 << 11)
+#define ADMA_RX_BT_SIZE_8DWORDS BIT(11)
+#define ADMA_RX_BT_SIZE_16DWORDS (2 << 11)
+#define ADMA_RX_BT_SIZE_32DWORDS (3 << 11)
+
+/* Register bits.
+ */
+
+#define MACCFG_RXEN BIT(2)
+#define MACCFG_TXEN BIT(3)
+#define MACCFG_PROMISC BIT(18)
+#define MACCFG_RXMCAST BIT(19)
+#define MACCFG_FDUPLEX BIT(20)
+#define MACCFG_PORTSEL BIT(27)
+#define MACCFG_HBEATDIS BIT(28)
+
+#define DMACTL_SR BIT(1) /* Start/Stop Receive */
+#define DMACTL_ST BIT(13) /* Start/Stop Transmission Command */
+
+#define DMACFG_SWR BIT(0) /* Software Reset */
+#define DMACFG_BURST32 (32 << 8)
+
+#define DMASTAT_TS 0x00700000 /* Transmit Process State */
+#define DMASTAT_RS 0x000e0000 /* Receive Process State */
+
+#define MACCFG_INIT 0 /* (MACCFG_FDUPLEX) // | MACCFG_PORTSEL) */
+
+/* Descriptor bits.
+ */
+#define R_OWN 0x80000000 /* Own Bit */
+#define RD_RER 0x02000000 /* Receive End Of Ring */
+#define RD_LS 0x00000100 /* Last Descriptor */
+#define RD_ES 0x00008000 /* Error Summary */
+#define RD_CHAIN 0x01000000 /* Chained */
+
+/* Word 0 */
+#define T_OWN 0x80000000 /* Own Bit */
+#define TD_ES 0x00008000 /* Error Summary */
+
+/* Word 1 */
+#define TD_LS 0x40000000 /* Last Segment */
+#define TD_FS 0x20000000 /* First Segment */
+#define TD_TER 0x08000000 /* Transmit End Of Ring */
+#define TD_CHAIN 0x01000000 /* Chained */
+
+#define TD_SET 0x08000000 /* Setup Packet */
+
+#define POLL_DEMAND 1
+
+#define RSTCTL (0x34)
+#define RSTCTL_RSTENET1 BIT(19)
+#define RSTCTL_RSTENET2 BIT(20)
+
+#define INIT_VALUE_OF_RT2883_PSE_FQ_CFG 0xff908000
+#define INIT_VALUE_OF_PSE_FQFC_CFG 0x80504000
+#define INIT_VALUE_OF_FORCE_100_FD 0x1001BC01
+#define INIT_VALUE_OF_FORCE_1000_FD 0x1F01DC01
+
+/* Define Whole FE Reset Register */
+#define RSTCTRL (RALINK_SYSCTL_BASE + 0x34)
+#define RT2880_AGPIOCFG_REG (RALINK_SYSCTL_BASE + 0x3C)
+
+/*=========================================
+ * PDMA RX Descriptor Format define
+ *=========================================
+ */
+
+struct PDMA_RXD_INFO1_T {
+ unsigned int PDP0;
+};
+
+struct PDMA_RXD_INFO2_T {
+ unsigned int PLEN1:2;
+ unsigned int LRO_AGG_CNT:8;
+ unsigned int REV:5;
+ unsigned int TAG:1;
+ unsigned int PLEN0:14;
+ unsigned int LS0:1;
+ unsigned int DDONE_bit:1;
+};
+
+struct PDMA_RXD_INFO3_T {
+ unsigned int VID:16;
+ unsigned int TPID:16;
+};
+
+struct PDMA_RXD_INFO4_T {
+ unsigned int FOE_ENTRY:14;
+ unsigned int CRSN:5;
+ unsigned int SP:3;
+ unsigned int FOE_ENTRY_32:1;
+ unsigned int L4F:1;
+ unsigned int L4VLD:1;
+ unsigned int TACK:1;
+ unsigned int IP4F:1;
+ unsigned int IP4:1;
+ unsigned int IP6:1;
+ unsigned int UN_USE1:3;
+};
+
+struct PDMA_rxdesc {
+ struct PDMA_RXD_INFO1_T rxd_info1;
+ struct PDMA_RXD_INFO2_T rxd_info2;
+ struct PDMA_RXD_INFO3_T rxd_info3;
+ struct PDMA_RXD_INFO4_T rxd_info4;
+#ifdef CONFIG_32B_DESC
+ unsigned int rxd_info5;
+ unsigned int rxd_info6;
+ unsigned int rxd_info7;
+ unsigned int rxd_info8;
+#endif
+};
+
+/*=========================================
+ * PDMA TX Descriptor Format define
+ *=========================================
+ */
+struct PDMA_TXD_INFO1_T {
+ unsigned int SDP0;
+};
+
+struct PDMA_TXD_INFO2_T {
+ unsigned int SDL1:14;
+ unsigned int LS1_bit:1;
+ unsigned int BURST_bit:1;
+ unsigned int SDL0:14;
+ unsigned int LS0_bit:1;
+ unsigned int DDONE_bit:1;
+};
+
+struct PDMA_TXD_INFO3_T {
+ unsigned int SDP1;
+};
+
+struct PDMA_TXD_INFO4_T {
+ unsigned int VLAN_TAG:17; /* INSV(1)+VPRI(3)+CFI(1)+VID(12) */
+ unsigned int RESV:2;
+ unsigned int UDF:6;
+ unsigned int FPORT:3;
+ unsigned int TSO:1;
+ unsigned int TUI_CO:3;
+};
+
+struct PDMA_txdesc {
+ struct PDMA_TXD_INFO1_T txd_info1;
+ struct PDMA_TXD_INFO2_T txd_info2;
+ struct PDMA_TXD_INFO3_T txd_info3;
+ struct PDMA_TXD_INFO4_T txd_info4;
+#ifdef CONFIG_32B_DESC
+ unsigned int txd_info5;
+ unsigned int txd_info6;
+ unsigned int txd_info7;
+ unsigned int txd_info8;
+#endif
+};
+
+/*=========================================
+ * QDMA TX Descriptor Format define
+ *=========================================
+ */
+struct QDMA_TXD_INFO1_T {
+ unsigned int SDP;
+};
+
+struct QDMA_TXD_INFO2_T {
+ unsigned int NDP;
+};
+
+struct QDMA_TXD_INFO3_T {
+ unsigned int QID:4; /* Q0~Q15 */
+ /* unsigned int VQID : 10; */
+ unsigned int PROT:3;
+ unsigned int IPOFST:7;
+ unsigned int SWC_bit:1;
+ unsigned int BURST_bit:1;
+ unsigned int SDL:14;
+ unsigned int LS_bit:1;
+ unsigned int OWN_bit:1;
+};
+
+struct QDMA_TXD_INFO4_T {
+ unsigned int VLAN_TAG:17; /* INSV(1)+VPRI(3)+CFI(1)+VID(12) */
+ unsigned int VQID0:1;
+ unsigned int SDL:2;
+ unsigned int QID:2; /* Q16~Q63 */
+ unsigned int RESV:3;
+ unsigned int FPORT:3;
+ unsigned int TSO:1;
+ unsigned int TUI_CO:3;
+};
+
+struct QDMA_txdesc {
+ struct QDMA_TXD_INFO1_T txd_info1;
+ struct QDMA_TXD_INFO2_T txd_info2;
+ struct QDMA_TXD_INFO3_T txd_info3;
+ struct QDMA_TXD_INFO4_T txd_info4;
+#ifdef CONFIG_32B_DESC
+ unsigned int txd_info5;
+ unsigned int txd_info6;
+ unsigned int txd_info7;
+ unsigned int txd_info8;
+#endif
+};
+
+#define QTXD_LEN (sizeof(struct QDMA_txdesc))
+#define PHY_ENABLE_AUTO_NEGO 0x1000
+#define PHY_RESTART_AUTO_NEGO 0x0200
+
+/* PHY_STAT_REG = 1; */
+#define PHY_AUTO_NEGO_COMP 0x0020
+#define PHY_LINK_STATUS 0x0004
+
+/* PHY_AUTO_NEGO_REG = 4; */
+#define PHY_CAP_10_HALF 0x0020
+#define PHY_CAP_10_FULL 0x0040
+#define PHY_CAP_100_HALF 0x0080
+#define PHY_CAP_100_FULL 0x0100
+
+/* proc definition */
+
+#define PROCREG_CONTROL_FILE "/var/run/procreg_control"
+#if defined(CONFIG_MACH_MT7623)
+#define PROCREG_DIR "mt7623"
+#elif defined(CONFIG_MACH_LEOPARD)
+#define PROCREG_DIR "leopard"
+#elif defined(CONFIG_PINCTRL_MT7622)
+#define PROCREG_DIR "mt7622"
+#elif defined(CONFIG_SOC_MT7621)
+#define PROCREG_DIR "mt7621"
+#endif
+
+#define PROCREG_SKBFREE "skb_free"
+#define PROCREG_TXRING "tx_ring"
+#define PROCREG_RXRING "rx_ring"
+#define PROCREG_RXRING1 "rx_ring1"
+#define PROCREG_RXRING2 "rx_ring2"
+#define PROCREG_RXRING3 "rx_ring3"
+#define PROCREG_NUM_OF_TXD "num_of_txd"
+#define PROCREG_TSO_LEN "tso_len"
+#define PROCREG_LRO_STATS "lro_stats"
+#define PROCREG_HW_LRO_STATS "hw_lro_stats"
+#define PROCREG_HW_LRO_AUTO_TLB "hw_lro_auto_tlb"
+#define PROCREG_HW_IO_COHERENT "hw_iocoherent"
+#define PROCREG_GMAC "gmac"
+#define PROCREG_GMAC2 "gmac2"
+#define PROCREG_CP0 "cp0"
+#define PROCREG_RAQOS "qos"
+#define PROCREG_READ_VAL "regread_value"
+#define PROCREG_WRITE_VAL "regwrite_value"
+#define PROCREG_ADDR "reg_addr"
+#define PROCREG_CTL "procreg_control"
+#define PROCREG_RXDONE_INTR "rxdone_intr_count"
+#define PROCREG_ESW_INTR "esw_intr_count"
+#define PROCREG_ESW_CNT "esw_cnt"
+#define PROCREG_ETH_CNT "eth_cnt"
+#define PROCREG_SNMP "snmp"
+#define PROCREG_SET_LAN_IP "set_lan_ip"
+#if defined(TASKLET_WORKQUEUE_SW)
+#define PROCREG_SCHE "schedule"
+#endif
+#define PROCREG_QDMA "qdma"
+#define PROCREG_INT_DBG "int_dbg"
+struct rt2880_reg_op_data {
+ char name[64];
+ unsigned int reg_addr;
+ unsigned int op;
+ unsigned int reg_value;
+};
+
+struct lro_counters {
+ u32 lro_aggregated;
+ u32 lro_flushed;
+ u32 lro_no_desc;
+};
+
+struct lro_para_struct {
+ unsigned int lan_ip1;
+};
+
+struct parse_result {
+ /* layer2 header */
+ u8 dmac[6];
+ u8 smac[6];
+
+ /* vlan header */
+ u16 vlan_tag;
+ u16 vlan1_gap;
+ u16 vlan1;
+ u16 vlan2_gap;
+ u16 vlan2;
+ u16 vlan_layer;
+
+ /* pppoe header */
+ u32 pppoe_gap;
+ u16 ppp_tag;
+ u16 pppoe_sid;
+
+ /* layer3 header */
+ u16 eth_type;
+ struct iphdr iph;
+ struct ipv6hdr ip6h;
+
+ /* layer4 header */
+ struct tcphdr th;
+ struct udphdr uh;
+
+ u32 pkt_type;
+ u8 is_mcast;
+};
+
+#define DMA_GLO_CFG PDMA_GLO_CFG
+
+#if defined(CONFIG_RAETH_QDMATX_QDMARX)
+#define GDMA1_FWD_PORT 0x5555
+#define GDMA2_FWD_PORT 0x5555
+#elif defined(CONFIG_RAETH_PDMATX_QDMARX)
+#define GDMA1_FWD_PORT 0x5555
+#define GDMA2_FWD_PORT 0x5555
+#else
+#define GDMA1_FWD_PORT 0x0000
+#define GDMA2_FWD_PORT 0x0000
+#endif
+
+#if defined(CONFIG_RAETH_QDMATX_QDMARX)
+#define RAETH_RX_CALC_IDX0 QRX_CRX_IDX_0
+#define RAETH_RX_CALC_IDX1 QRX_CRX_IDX_1
+#elif defined(CONFIG_RAETH_PDMATX_QDMARX)
+#define RAETH_RX_CALC_IDX0 QRX_CRX_IDX_0
+#define RAETH_RX_CALC_IDX1 QRX_CRX_IDX_1
+#else
+#define RAETH_RX_CALC_IDX0 RX_CALC_IDX0
+#define RAETH_RX_CALC_IDX1 RX_CALC_IDX1
+#endif
+#define RAETH_RX_CALC_IDX2 RX_CALC_IDX2
+#define RAETH_RX_CALC_IDX3 RX_CALC_IDX3
+#define RAETH_FE_INT_STATUS FE_INT_STATUS
+#define RAETH_FE_INT_ALL FE_INT_ALL
+#define RAETH_FE_INT_ENABLE FE_INT_ENABLE
+#define RAETH_FE_INT_DLY_INIT FE_INT_DLY_INIT
+#define RAETH_FE_INT_SETTING (RX_DONE_INT0 | RX_DONE_INT1 | \
+ TX_DONE_INT0 | TX_DONE_INT1 | \
+ TX_DONE_INT2 | TX_DONE_INT3)
+#define QFE_INT_SETTING (RX_DONE_INT0 | RX_DONE_INT1 | \
+ TX_DONE_INT0 | TX_DONE_INT1 | \
+ TX_DONE_INT2 | TX_DONE_INT3)
+#define RAETH_TX_DLY_INT TX_DLY_INT
+#define RAETH_TX_DONE_INT0 TX_DONE_INT0
+#define RAETH_DLY_INT_CFG DLY_INT_CFG
+
+/* io-coherent for ethdmasys */
+#define IOC_ETH_PDMA BIT(0)
+#define IOC_ETH_QDMA BIT(1)
+
+#endif /* RAETH_REG_H */
diff --git a/src/kernel/modules/netsys_driver/nat/include/raether.h b/src/kernel/modules/netsys_driver/nat/include/raether.h
new file mode 100755
index 0000000..81e27b7
--- /dev/null
+++ b/src/kernel/modules/netsys_driver/nat/include/raether.h
@@ -0,0 +1,482 @@
+/* Copyright 2016 MediaTek Inc.
+ * Author: Nelson Chang <nelson.chang@mediatek.com>
+ * Author: Carlos Huang <carlos.huang@mediatek.com>
+ * Author: Harry Huang <harry.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef RA2882ETHEND_H
+#define RA2882ETHEND_H
+
+#include "raeth_config.h"
+#include "raeth_reg.h"
+#include "ra_dbg_proc.h"
+#include "ra_ioctl.h"
+
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/skbuff.h>
+#include <linux/if_vlan.h>
+#include <linux/if_ether.h>
+#include <linux/fs.h>
+#include <linux/mii.h>
+#include <linux/uaccess.h>
+#if defined(CONFIG_RAETH_TSO)
+#include <linux/tcp.h>
+#include <net/ipv6.h>
+#include <linux/ip.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <linux/in.h>
+#include <linux/ppp_defs.h>
+#include <linux/if_pppox.h>
+#endif
+#include <linux/netdevice.h>
+#include <linux/if_vlan.h>
+#include <linux/ppp_defs.h>
+
+/* LRO support */
+#include <linux/inet_lro.h>
+
+#include <linux/delay.h>
+#include <linux/sched.h>
+
+#include <asm-generic/pci-dma-compat.h>
+
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/of_net.h>
+#include <linux/of_irq.h>
+#include <linux/of_gpio.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+
+#include <linux/dma-mapping.h>
+
+#if defined(CONFIG_MACH_MT7623)
+#include <linux/delay.h>
+#endif
+#include <linux/kthread.h>
+#include <linux/prefetch.h>
+
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
+#include <net/ra_nat.h>
+#endif
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#define ETH_GPIO_BASE 0x10005000
+
+#if defined(CONFIG_QDMA_MQ)
+#define GMAC1_TXQ_NUM 3
+#define GMAC1_TXQ_TXD_NUM 512
+#define GMAC1_TXD_NUM (GMAC1_TXQ_NUM * GMAC1_TXQ_TXD_NUM)
+#define GMAC2_TXQ_NUM 1
+#define GMAC2_TXQ_TXD_NUM 128
+#define GMAC2_TXD_NUM (GMAC2_TXQ_NUM * GMAC2_TXQ_TXD_NUM)
+#define NUM_TX_DESC (GMAC1_TXD_NUM + GMAC2_TXD_NUM)
+#define TOTAL_TXQ_NUM (GMAC1_TXQ_NUM + GMAC2_TXQ_NUM)
+#else
+#define TOTAL_TXQ_NUM 2
+#endif
+
+#if defined(CONFIG_MACH_MT7623)
+#define NUM_RX_DESC 2048
+#define NUM_QRX_DESC 16
+#define NUM_PQ_RESV 4
+#define FFA 2048
+#define QUEUE_OFFSET 0x10
+#else
+#define NUM_QRX_DESC 16
+#define NUM_PQ_RESV 4
+#define FFA 512
+#define QUEUE_OFFSET 0x10
+#endif
+
+#if defined(CONFIG_PINCTRL_MT7622)
+#define NUM_PQ 64
+#else
+#define NUM_PQ 16
+#endif
+/* #define NUM_TX_MAX_PROCESS NUM_TX_DESC */
+#define NUM_RX_MAX_PROCESS 16
+
+#define MAX_RX_RING_NUM 4
+#define NUM_LRO_RX_DESC 16
+
+#define MAX_RX_LENGTH 1536
+
+#if defined(CONFIG_SUPPORT_OPENWRT)
+#define DEV_NAME "eth0"
+#define DEV2_NAME "eth1"
+#else
+#define DEV_NAME "eth2"
+#define DEV2_NAME "eth3"
+#endif
+
+#if defined(CONFIG_MACH_MT7623)
+#define GMAC0_OFFSET 0xE000
+#define GMAC2_OFFSET 0xE006
+#else
+#define GMAC0_OFFSET 0x28
+#define GMAC2_OFFSET 0x22
+#endif
+
+#if defined(CONFIG_MACH_MT7623)
+#define IRQ_ENET0 232
+#define IRQ_ENET1 231
+#define IRQ_ENET2 230
+#else
+/* NOTE(Nelson): prom version started from 20150806 */
+#define IRQ_ENET0 255
+#define IRQ_ENET1 256
+#define IRQ_ENET2 257
+#endif
+#define MTK_NAPI_WEIGHT 64
+
+#define RAETH_VERSION "STD_v0.1"
+
+/* MT7623 PSE reset workaround */
+#define FE_RESET_POLLING_MS (5000)
+
+/*LEOPARD POLLING*/
+#define PHY_POLLING_MS (1000)
+#define FE_DEFAULT_LAN_IP "192.168.1.1"
+#define IP4_ADDR_LEN 16
+
+#if defined(CONFIG_SOC_MT7621)
+#define MT_TRIGGER_LOW 0
+#else
+#define MT_TRIGGER_LOW IRQF_TRIGGER_LOW
+#endif
+
+/* This enum allows us to identify how the clock is defined on the array of the
+ * clock in the order
+ */
+enum mtk_clks_map {
+ MTK_CLK_ETHIF,
+ MTK_CLK_ESW,
+ MTK_CLK_GP0,
+ MTK_CLK_GP1,
+ MTK_CLK_GP2,
+ MTK_CLK_SGMII_TX250M,
+ MTK_CLK_SGMII_RX250M,
+ MTK_CLK_SGMII_CDR_REF,
+ MTK_CLK_SGMII_CDR_FB,
+ MTK_CLK_SGMII1_TX250M,
+ MTK_CLK_SGMII1_RX250M,
+ MTK_CLK_SGMII1_CDR_REF,
+ MTK_CLK_SGMII1_CDR_FB,
+ MTK_CLK_TRGPLL,
+ MTK_CLK_SGMIPLL,
+ MTK_CLK_ETH1PLL,
+ MTK_CLK_ETH2PLL,
+ MTK_CLK_FE,
+ MTK_CLK_SGMII_TOP,
+ MTK_CLK_MAX
+};
+
+struct END_DEVICE {
+ struct device *dev;
+ unsigned int tx_cpu_owner_idx0;
+#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
+ unsigned int rx_calc_idx[MAX_RX_RING_NUM];
+#endif
+ unsigned int tx_ring_full;
+ unsigned int tx_full; /* NOTE(Nelso): unused, can remove */
+
+ /* PDMA TX PTR */
+ dma_addr_t phy_tx_ring0;
+
+ /* QDMA TX PTR */
+ struct platform_device *qdma_pdev;
+ /* struct sk_buff *free_skb[NUM_TX_DESC]; */
+ struct sk_buff **free_skb;
+ unsigned int tx_dma_ptr;
+ unsigned int tx_cpu_ptr;
+ unsigned int tx_cpu_idx;
+ unsigned int rls_cpu_idx;
+ /* atomic_t free_txd_num[TOTAL_TXQ_NUM]; */
+ atomic_t *free_txd_num;
+ /* unsigned int free_txd_head[TOTAL_TXQ_NUM]; */
+ /* unsigned int free_txd_tail[TOTAL_TXQ_NUM]; */
+ unsigned int *free_txd_head;
+ unsigned int *free_txd_tail;
+ struct QDMA_txdesc *txd_pool;
+ dma_addr_t phy_txd_pool;
+ /* unsigned int txd_pool_info[NUM_TX_DESC]; */
+ unsigned int *txd_pool_info;
+ struct QDMA_txdesc *free_head;
+ unsigned int phy_free_head;
+ unsigned int *free_page_head;
+ dma_addr_t phy_free_page_head;
+ struct PDMA_rxdesc *qrx_ring;
+ dma_addr_t phy_qrx_ring;
+
+ /* TSO */
+ unsigned int skb_txd_num;
+
+ /* MT7623 workaround */
+ struct work_struct reset_task;
+
+ /* workqueue_bh */
+ struct work_struct rx_wq;
+
+ /* tasklet_bh */
+ struct tasklet_struct rx_tasklet;
+
+ /* struct sk_buff *skb_free[NUM_TX_DESC]; */
+ struct sk_buff **skb_free;
+ unsigned int free_idx;
+
+ struct net_device_stats stat; /* The new statistics table. */
+ spinlock_t page_lock; /* spin_lock for cr access critial section */
+ spinlock_t irq_lock; /* spin_lock for isr critial section */
+ spinlock_t mdio_lock; /* spin_lock for mdio reg access */
+ struct PDMA_txdesc *tx_ring0;
+ struct PDMA_rxdesc *rx_ring[MAX_RX_RING_NUM];
+ dma_addr_t phy_rx_ring[MAX_RX_RING_NUM];
+
+ /* void *netrx_skb_data[MAX_RX_RING_NUM][NUM_RX_DESC]; */
+ void **netrx_skb_data[MAX_RX_RING_NUM];
+
+ /* struct sk_buff *netrx0_skbuf[NUM_RX_DESC]; */
+ /*struct sk_buff **netrx0_skbuf;*/
+ void **netrx0_skb_data;
+ /* napi */
+ struct napi_struct napi;
+ struct napi_struct napi_rx;
+ struct napi_struct napi_rx_rss0;
+ struct napi_struct napi_rx_rss1;
+ struct napi_struct napi_rx_rss2;
+ struct napi_struct napi_rx_rss3;
+ struct napi_struct napi_tx;
+ struct net_device dummy_dev;
+
+ /* clock control */
+ struct clk *clks[MTK_CLK_MAX];
+
+ /* gsw device node */
+ struct device_node *switch_np;
+
+ /* GE1 support */
+ struct net_device *netdev;
+ /* GE2 support */
+ struct net_device *pseudo_dev;
+ unsigned int is_pseudo;
+
+ struct mii_if_info mii_info;
+ struct lro_counters lro_counters;
+ struct net_lro_mgr lro_mgr;
+ struct net_lro_desc lro_arr[8];
+ struct vlan_group *vlgrp;
+
+ /* virtual base addr from device tree */
+ void __iomem *ethdma_sysctl_base;
+
+ unsigned int irq0;
+ unsigned int irq1;
+ unsigned int irq2;
+ unsigned int irq3;
+ unsigned int esw_irq;
+ void __iomem *fe_tx_int_status;
+ void __iomem *fe_tx_int_enable;
+ void __iomem *fe_rx_int_status;
+ void __iomem *fe_rx_int_enable;
+
+ unsigned int features;
+ unsigned int chip_name;
+ unsigned int architecture;
+
+ /* IP address */
+ char lan_ip4_addr[IP4_ADDR_LEN];
+
+ /* Function pointers */
+ int (*ei_start_xmit)(struct sk_buff *skb, struct net_device *netdev,
+ int gmac_no);
+ int (*ei_xmit_housekeeping)(struct net_device *netdev, int budget);
+ int (*ei_eth_recv)(struct net_device *dev,
+ struct napi_struct *napi,
+ int budget);
+ int (*ei_eth_recv_rss0)(struct net_device *dev,
+ struct napi_struct *napi,
+ int budget);
+ int (*ei_eth_recv_rss1)(struct net_device *dev,
+ struct napi_struct *napi,
+ int budget);
+ int (*ei_eth_recv_rss2)(struct net_device *dev,
+ struct napi_struct *napi,
+ int budget);
+ int (*ei_eth_recv_rss3)(struct net_device *dev,
+ struct napi_struct *napi,
+ int budget);
+ int (*ei_fill_tx_desc)(struct net_device *dev,
+ unsigned long *tx_cpu_owner_idx,
+ struct sk_buff *skb, int gmac_no);
+
+ /* MT7623 PSE reset workaround */
+ struct task_struct *kreset_task;
+ struct task_struct *kphy_poll_task;
+ unsigned int fe_reset_times;
+ unsigned int tx_mask;
+ unsigned int rx_mask;
+ unsigned int *rls_cnt;
+};
+
+#ifdef CONFIG_INET_LRO
+static inline void ei_lro_flush_all(struct net_lro_mgr *lro_mgr)
+{
+ lro_flush_all(lro_mgr);
+}
+#else
+static inline void ei_lro_flush_all(struct net_lro_mgr *lro_mgr)
+{
+}
+#endif
+
+struct net_device_stats *ra_get_stats(struct net_device *dev);
+
+int ei_open(struct net_device *dev);
+int ei_close(struct net_device *dev);
+
+int ra2882eth_init(void);
+void ra2882eth_cleanup_module(void);
+
+u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data);
+u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data);
+u32 mii_mgr_cl45_set_address(u32 port_num, u32 dev_addr, u32 reg_addr);
+u32 mii_mgr_read_cl45(u32 port_num, u32 dev_addr, u32 reg_addr,
+ u32 *read_data);
+u32 mii_mgr_write_cl45(u32 port_num, u32 dev_addr, u32 reg_addr,
+ u32 write_data);
+
+/* HNAT functions */
+#if defined(CONFIG_RA_NAT_NONE)
+static int (*ra_sw_nat_hook_rx)(struct sk_buff *skb);
+static int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no);
+#else
+extern int (*ra_sw_nat_hook_rx)(struct sk_buff *skb);
+extern int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no);
+#endif
+
+/* PDMA functions */
+int fe_pdma_wait_dma_idle(void);
+int fe_pdma_rx_dma_init(struct net_device *dev);
+int fe_pdma_tx_dma_init(struct net_device *dev);
+void fe_pdma_rx_dma_deinit(struct net_device *dev);
+void fe_pdma_tx_dma_deinit(struct net_device *dev);
+void set_fe_pdma_glo_cfg(void);
+int ei_pdma_start_xmit(struct sk_buff *skb, struct net_device *dev,
+ int gmac_no);
+int ei_pdma_xmit_housekeeping(struct net_device *netdev,
+ int budget);
+int fe_fill_tx_desc(struct net_device *dev,
+ unsigned long *tx_cpu_owner_idx,
+ struct sk_buff *skb,
+ int gmac_no);
+int fe_fill_tx_desc_tso(struct net_device *dev,
+ unsigned long *tx_cpu_owner_idx,
+ struct sk_buff *skb,
+ int gmac_no);
+void fe_set_sw_lro_my_ip(char *lan_ip_addr);
+
+/* QDMA functions */
+int fe_qdma_wait_dma_idle(void);
+int fe_qdma_rx_dma_init(struct net_device *dev);
+int fe_qdma_tx_dma_init(struct net_device *dev);
+void fe_qdma_rx_dma_deinit(struct net_device *dev);
+void fe_qdma_tx_dma_deinit(struct net_device *dev);
+void set_fe_qdma_glo_cfg(void);
+int ei_qdma_start_xmit(struct sk_buff *skb, struct net_device *dev,
+ int gmac_no);
+int ei_qdma_xmit_housekeeping(struct net_device *netdev, int budget);
+int ei_qdma_ioctl(struct net_device *dev, struct ifreq *ifr,
+ struct qdma_ioctl_data *ioctl_data);
+int ephy_ioctl(struct net_device *dev, struct ifreq *ifr,
+ struct ephy_ioctl_data *ioctl_data);
+/* HW LRO functions */
+int fe_hw_lro_init(struct net_device *dev);
+void fe_hw_lro_deinit(struct net_device *dev);
+int fe_hw_lro_recv(struct net_device *dev,
+ struct napi_struct *napi,
+ int budget);
+void fe_set_hw_lro_my_ip(char *lan_ip_addr);
+
+int fe_rss_4ring_init(struct net_device *dev);
+void fe_rss_4ring_deinit(struct net_device *dev);
+int fe_rss_2ring_init(struct net_device *dev);
+void fe_rss_2ring_deinit(struct net_device *dev);
+int fe_rss0_recv(struct net_device *dev,
+ struct napi_struct *napi,
+ int budget);
+int fe_rss1_recv(struct net_device *dev,
+ struct napi_struct *napi,
+ int budget);
+int fe_rss2_recv(struct net_device *dev,
+ struct napi_struct *napi,
+ int budget);
+int fe_rss3_recv(struct net_device *dev,
+ struct napi_struct *napi,
+ int budget);
+static inline void *raeth_alloc_skb_data(size_t size, gfp_t flags)
+{
+#ifdef CONFIG_ETH_SLAB_ALLOC_SKB
+ return kmalloc(size, flags);
+#else
+ return netdev_alloc_frag(size);
+#endif
+}
+
+static inline void raeth_free_skb_data(void *addr)
+{
+#ifdef CONFIG_ETH_SLAB_ALLOC_SKB
+ kfree(addr);
+#else
+ skb_free_frag(addr);
+#endif
+}
+
+static inline struct sk_buff *raeth_build_skb(void *data,
+ unsigned int frag_size)
+{
+#ifdef CONFIG_ETH_SLAB_ALLOC_SKB
+ return build_skb(data, 0);
+#else
+ return build_skb(data, frag_size);
+#endif
+}
+
+extern u32 gmac1_txq_num;
+extern u32 gmac1_txq_txd_num;
+extern u32 gmac1_txd_num;
+extern u32 gmac2_txq_num;
+extern u32 gmac2_txq_txd_num;
+extern u32 gmac2_txd_num;
+extern u32 num_rx_desc;
+extern u32 num_tx_max_process;
+extern u32 num_tx_desc;
+extern u32 total_txq_num;
+extern u32 mac_to_gigaphy_mode_addr;
+extern u32 mac_to_gigaphy_mode_addr2;
+#endif
diff --git a/src/kernel/modules/netsys_driver/nat/include/raether_hwlro.h b/src/kernel/modules/netsys_driver/nat/include/raether_hwlro.h
new file mode 100755
index 0000000..c319aca
--- /dev/null
+++ b/src/kernel/modules/netsys_driver/nat/include/raether_hwlro.h
@@ -0,0 +1,403 @@
+/* Copyright 2016 MediaTek Inc.
+ * Author: Nelson Chang <nelson.chang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef RA_HWLRO_H
+#define RA_HWLRO_H
+
+#include "raeth_reg.h"
+
+#define HW_LRO_TIMER_UNIT 1
+#define HW_LRO_REFRESH_TIME 50000
+#define HW_LRO_MAX_AGG_CNT 64
+#define HW_LRO_AGG_DELTA 1
+#define MAX_LRO_RX_LENGTH (PAGE_SIZE * 3)
+#define HW_LRO_AGG_TIME 10 /* 200us */
+#define HW_LRO_AGE_TIME 50 /* 1ms */
+#define HW_LRO_BW_THRE 3000
+#define HW_LRO_REPLACE_DELTA 1000
+#define HW_LRO_SDL_REMAIN_ROOM 1522
+
+struct PDMA_LRO_AUTO_TLB_INFO0_T {
+ unsigned int DTP:16;
+ unsigned int STP:16;
+};
+
+struct PDMA_LRO_AUTO_TLB_INFO1_T {
+ unsigned int SIP0:32;
+};
+
+struct PDMA_LRO_AUTO_TLB_INFO2_T {
+ unsigned int SIP1:32;
+};
+
+struct PDMA_LRO_AUTO_TLB_INFO3_T {
+ unsigned int SIP2:32;
+};
+
+struct PDMA_LRO_AUTO_TLB_INFO4_T {
+ unsigned int SIP3:32;
+};
+
+struct PDMA_LRO_AUTO_TLB_INFO5_T {
+ unsigned int VLAN_VID0:32;
+};
+
+struct PDMA_LRO_AUTO_TLB_INFO6_T {
+ unsigned int VLAN_VID1:16;
+ unsigned int VLAN_VID_VLD:4;
+ unsigned int CNT:12;
+};
+
+struct PDMA_LRO_AUTO_TLB_INFO7_T {
+ unsigned int DW_LEN:32;
+};
+
+struct PDMA_LRO_AUTO_TLB_INFO8_T {
+ unsigned int DIP_ID:2;
+ unsigned int IPV6:1;
+ unsigned int IPV4:1;
+ unsigned int RESV:27;
+ unsigned int VALID:1;
+};
+
+struct PDMA_LRO_AUTO_TLB_INFO {
+ struct PDMA_LRO_AUTO_TLB_INFO0_T auto_tlb_info0;
+ struct PDMA_LRO_AUTO_TLB_INFO1_T auto_tlb_info1;
+ struct PDMA_LRO_AUTO_TLB_INFO2_T auto_tlb_info2;
+ struct PDMA_LRO_AUTO_TLB_INFO3_T auto_tlb_info3;
+ struct PDMA_LRO_AUTO_TLB_INFO4_T auto_tlb_info4;
+ struct PDMA_LRO_AUTO_TLB_INFO5_T auto_tlb_info5;
+ struct PDMA_LRO_AUTO_TLB_INFO6_T auto_tlb_info6;
+ struct PDMA_LRO_AUTO_TLB_INFO7_T auto_tlb_info7;
+ struct PDMA_LRO_AUTO_TLB_INFO8_T auto_tlb_info8;
+};
+
+#define PDMA_LRO_EN BIT(0)
+#define PDMA_LRO_IPV6_EN BIT(1)
+#define PDMA_LRO_CRSN_BNW BIT(6)
+#define PDMA_LRO_IPV4_CSUM_UPDATE_EN BIT(7)
+#define PDMA_LRO_IPV4_CTRL_PUSH_EN BIT(23)
+#define PDMA_LRO_RXD_PREFETCH_EN BITS(3, 4)
+#define PDMA_NON_LRO_MULTI_EN BIT(2)
+#define PDMA_LRO_DLY_INT_EN BIT(5)
+#define PDMA_LRO_FUSH_REQ BITS(26, 28)
+#define PDMA_LRO_RELINGUISH BITS(29, 31)
+#define PDMA_LRO_FREQ_PRI_ADJ BITS(16, 19)
+#define PDMA_LRO_TPUT_PRE_ADJ BITS(8, 11)
+#define PDMA_LRO_TPUT_PRI_ADJ BITS(12, 15)
+#define PDMA_LRO_ALT_SCORE_MODE BIT(21)
+#define PDMA_LRO_RING_AGE1 BITS(22, 31)
+#define PDMA_LRO_RING_AGE2 BITS(0, 5)
+#define PDMA_LRO_RING_AGG BITS(10, 25)
+#define PDMA_LRO_RING_AGG_CNT1 BITS(26, 31)
+#define PDMA_LRO_RING_AGG_CNT2 BITS(0, 1)
+#define PDMA_LRO_ALT_TICK_TIMER BITS(16, 20)
+#define PDMA_LRO_LRO_MIN_RXD_SDL0 BITS(16, 31)
+
+#define PDMA_LRO_DLY_INT_EN_OFFSET (5)
+#define PDMA_LRO_TPUT_PRE_ADJ_OFFSET (8)
+#define PDMA_LRO_FREQ_PRI_ADJ_OFFSET (16)
+#define PDMA_LRO_LRO_MIN_RXD_SDL0_OFFSET (16)
+#define PDMA_LRO_TPUT_PRI_ADJ_OFFSET (12)
+#define PDMA_LRO_ALT_SCORE_MODE_OFFSET (21)
+#define PDMA_LRO_FUSH_REQ_OFFSET (26)
+#define PDMA_NON_LRO_MULTI_EN_OFFSET (2)
+#define PDMA_LRO_IPV6_EN_OFFSET (1)
+#define PDMA_LRO_RXD_PREFETCH_EN_OFFSET (3)
+#define PDMA_LRO_IPV4_CSUM_UPDATE_EN_OFFSET (7)
+#define PDMA_LRO_IPV4_CTRL_PUSH_EN_OFFSET (23)
+#define PDMA_LRO_ALT_TICK_TIMER_OFFSET (16)
+
+#define PDMA_LRO_TPUT_OVERFLOW_ADJ BITS(12, 31)
+#define PDMA_LRO_CNT_OVERFLOW_ADJ BITS(0, 11)
+
+#define PDMA_LRO_TPUT_OVERFLOW_ADJ_OFFSET (12)
+#define PDMA_LRO_CNT_OVERFLOW_ADJ_OFFSET (0)
+
+#define PDMA_LRO_ALT_BYTE_CNT_MODE (0)
+#define PDMA_LRO_ALT_PKT_CNT_MODE (1)
+
+/* LRO_RX_RING1_CTRL_DW1 offsets */
+#define PDMA_LRO_AGE_H_OFFSET (10)
+#define PDMA_LRO_RING_AGE1_OFFSET (22)
+#define PDMA_LRO_RING_AGG_CNT1_OFFSET (26)
+/* LRO_RX_RING1_CTRL_DW2 offsets */
+#define PDMA_RX_MODE_OFFSET (6)
+#define PDMA_RX_PORT_VALID_OFFSET (8)
+#define PDMA_RX_MYIP_VALID_OFFSET (9)
+#define PDMA_LRO_RING_AGE2_OFFSET (0)
+#define PDMA_LRO_RING_AGG_OFFSET (10)
+#define PDMA_LRO_RING_AGG_CNT2_OFFSET (0)
+/* LRO_RX_RING1_CTRL_DW3 offsets */
+#define PDMA_LRO_AGG_CNT_H_OFFSET (6)
+/* LRO_RX_RING1_STP_DTP_DW offsets */
+#define PDMA_RX_TCP_SRC_PORT_OFFSET (16)
+#define PDMA_RX_TCP_DEST_PORT_OFFSET (0)
+/* LRO_RX_RING1_CTRL_DW0 offsets */
+#define PDMA_RX_IPV4_FORCE_OFFSET (1)
+#define PDMA_RX_IPV6_FORCE_OFFSET (0)
+
+#define ADMA_MULTI_RXD_PREFETCH_EN BIT(3)
+#define ADMA_RXD_PREFETCH_EN BIT(4)
+
+#define SET_PDMA_LRO_MAX_AGG_CNT(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW3); \
+reg_val &= ~0xff; \
+reg_val |= ((x) & 0xff); \
+sys_reg_write(ADMA_LRO_CTRL_DW3, reg_val); \
+}
+
+#define SET_PDMA_LRO_FLUSH_REQ(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
+reg_val &= ~PDMA_LRO_FUSH_REQ; \
+reg_val |= ((x) & 0x7) << PDMA_LRO_FUSH_REQ_OFFSET; \
+sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
+}
+
+#define SET_PDMA_LRO_IPV6_EN(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
+reg_val &= ~PDMA_LRO_IPV6_EN; \
+reg_val |= ((x) & 0x1) << PDMA_LRO_IPV6_EN_OFFSET; \
+sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
+}
+
+#define SET_PDMA_LRO_RXD_PREFETCH_EN(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
+reg_val &= ~PDMA_LRO_RXD_PREFETCH_EN; \
+reg_val |= (x); \
+sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
+}
+
+#define SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
+reg_val &= ~PDMA_LRO_IPV4_CSUM_UPDATE_EN; \
+reg_val |= ((x) & 0x1) << PDMA_LRO_IPV4_CSUM_UPDATE_EN_OFFSET; \
+sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
+}
+
+#define SET_PDMA_LRO_IPV4_CTRL_PUSH_EN(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
+reg_val &= ~PDMA_LRO_IPV4_CTRL_PUSH_EN; \
+reg_val |= ((x) & 0x1) << PDMA_LRO_IPV4_CTRL_PUSH_EN_OFFSET; \
+sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
+}
+
+#define SET_PDMA_NON_LRO_MULTI_EN(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
+reg_val &= ~(PDMA_NON_LRO_MULTI_EN); \
+reg_val |= ((x) & 0x1) << PDMA_NON_LRO_MULTI_EN_OFFSET; \
+sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
+}
+
+#define SET_PDMA_LRO_FREQ_PRI_ADJ(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
+reg_val &= ~PDMA_LRO_FREQ_PRI_ADJ; \
+reg_val |= ((x) & 0xf) << PDMA_LRO_FREQ_PRI_ADJ_OFFSET; \
+sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
+}
+
+#define SET_PDMA_LRO_TPUT_PRE_ADJ(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
+reg_val &= ~PDMA_LRO_TPUT_PRE_ADJ; \
+reg_val |= ((x) & 0xf) << PDMA_LRO_TPUT_PRE_ADJ_OFFSET; \
+sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
+}
+
+#define SET_PDMA_LRO_TPUT_PRI_ADJ(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
+reg_val &= ~PDMA_LRO_TPUT_PRI_ADJ; \
+reg_val |= ((x) & 0xf) << PDMA_LRO_TPUT_PRI_ADJ_OFFSET; \
+sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
+}
+
+#define SET_PDMA_LRO_ALT_SCORE_MODE(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
+reg_val &= ~PDMA_LRO_ALT_SCORE_MODE; \
+reg_val |= ((x) & 0x1) << PDMA_LRO_ALT_SCORE_MODE_OFFSET; \
+sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
+}
+
+#define SET_PDMA_LRO_DLY_INT_EN(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
+reg_val &= ~PDMA_LRO_DLY_INT_EN; \
+reg_val |= ((x) & 0x1) << PDMA_LRO_DLY_INT_EN_OFFSET; \
+sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
+}
+
+#define SET_PDMA_LRO_BW_THRESHOLD(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW2); \
+reg_val = (x); \
+sys_reg_write(ADMA_LRO_CTRL_DW2, reg_val); \
+}
+
+#define SET_PDMA_LRO_MIN_RXD_SDL(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW3); \
+reg_val &= ~PDMA_LRO_LRO_MIN_RXD_SDL0; \
+reg_val |= ((x) & 0xffff) << PDMA_LRO_LRO_MIN_RXD_SDL0_OFFSET; \
+sys_reg_write(ADMA_LRO_CTRL_DW3, reg_val); \
+}
+
+#define SET_PDMA_LRO_TPUT_OVERFLOW_ADJ(x) \
+{ \
+unsigned int reg_val = sys_reg_read(PDMA_LRO_ATL_OVERFLOW_ADJ); \
+reg_val &= ~PDMA_LRO_TPUT_OVERFLOW_ADJ; \
+reg_val |= ((x) & 0xfffff) << PDMA_LRO_TPUT_OVERFLOW_ADJ_OFFSET; \
+sys_reg_write(PDMA_LRO_ATL_OVERFLOW_ADJ, reg_val); \
+}
+
+#define SET_PDMA_LRO_CNT_OVERFLOW_ADJ(x) \
+{ \
+unsigned int reg_val = sys_reg_read(PDMA_LRO_ATL_OVERFLOW_ADJ); \
+reg_val &= ~PDMA_LRO_CNT_OVERFLOW_ADJ; \
+reg_val |= ((x) & 0xfff) << PDMA_LRO_CNT_OVERFLOW_ADJ_OFFSET; \
+sys_reg_write(PDMA_LRO_ATL_OVERFLOW_ADJ, reg_val); \
+}
+
+#define SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(x) \
+{ \
+unsigned int reg_val = sys_reg_read(LRO_ALT_REFRESH_TIMER); \
+reg_val &= ~PDMA_LRO_ALT_TICK_TIMER; \
+reg_val |= ((x) & 0x1f) << PDMA_LRO_ALT_TICK_TIMER_OFFSET; \
+sys_reg_write(LRO_ALT_REFRESH_TIMER, reg_val); \
+}
+
+#define SET_PDMA_LRO_ALT_REFRESH_TIMER(x) \
+{ \
+unsigned int reg_val = sys_reg_read(LRO_ALT_REFRESH_TIMER); \
+reg_val &= ~0xffff; \
+reg_val |= ((x) & 0xffff); \
+sys_reg_write(LRO_ALT_REFRESH_TIMER, reg_val); \
+}
+
+#define SET_PDMA_LRO_MAX_AGG_TIME(x) \
+{ \
+unsigned int reg_val = sys_reg_read(LRO_MAX_AGG_TIME); \
+reg_val &= ~0xffff; \
+reg_val |= ((x) & 0xffff); \
+sys_reg_write(LRO_MAX_AGG_TIME, reg_val); \
+}
+
+#define SET_PDMA_RXRING_MODE(x, y) \
+{ \
+unsigned int reg_val = sys_reg_read(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \
+reg_val &= ~(0x3 << PDMA_RX_MODE_OFFSET); \
+reg_val |= (y) << PDMA_RX_MODE_OFFSET; \
+sys_reg_write(LRO_RX_RING0_CTRL_DW2 + ((x) << 6), reg_val); \
+}
+
+#define SET_PDMA_RXRING_MYIP_VALID(x, y) \
+{ \
+unsigned int reg_val = sys_reg_read(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \
+reg_val &= ~(0x1 << PDMA_RX_MYIP_VALID_OFFSET); \
+reg_val |= ((y) & 0x1) << PDMA_RX_MYIP_VALID_OFFSET; \
+sys_reg_write(LRO_RX_RING0_CTRL_DW2 + ((x) << 6), reg_val); \
+}
+
+#define SET_PDMA_RXRING_VALID(x, y) \
+{ \
+unsigned int reg_val = sys_reg_read(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \
+reg_val &= ~(0x1 << PDMA_RX_PORT_VALID_OFFSET); \
+reg_val |= ((y) & 0x1) << PDMA_RX_PORT_VALID_OFFSET; \
+sys_reg_write(LRO_RX_RING0_CTRL_DW2 + ((x) << 6), reg_val); \
+}
+
+#define SET_PDMA_RXRING_TCP_SRC_PORT(x, y) \
+{ \
+unsigned int reg_val = sys_reg_read(LRO_RX_RING1_STP_DTP_DW + \
+ (((x) - 1) << 6)); \
+reg_val &= ~(0xffff << PDMA_RX_TCP_SRC_PORT_OFFSET); \
+reg_val |= (y) << PDMA_RX_TCP_SRC_PORT_OFFSET; \
+sys_reg_write(LRO_RX_RING1_STP_DTP_DW + (((x) - 1) << 6), reg_val); \
+}
+
+#define SET_PDMA_RXRING_TCP_DEST_PORT(x, y) \
+{ \
+unsigned int reg_val = sys_reg_read(LRO_RX_RING1_STP_DTP_DW + \
+ (((x) - 1) << 6)); \
+reg_val &= ~(0xffff << PDMA_RX_TCP_DEST_PORT_OFFSET); \
+reg_val |= (y) << PDMA_RX_TCP_DEST_PORT_OFFSET; \
+sys_reg_write(LRO_RX_RING1_STP_DTP_DW + (((x) - 1) << 6), reg_val); \
+}
+
+#define SET_PDMA_RXRING_IPV4_FORCE_MODE(x, y) \
+{ \
+unsigned int reg_val = sys_reg_read(LRO_RX_RING1_CTRL_DW0 + (((x) - 1) << 6)); \
+reg_val &= ~(0x1 << PDMA_RX_IPV4_FORCE_OFFSET); \
+reg_val |= (y) << PDMA_RX_IPV4_FORCE_OFFSET; \
+sys_reg_write(LRO_RX_RING1_CTRL_DW0 + (((x) - 1) << 6), reg_val); \
+}
+
+#define SET_PDMA_RXRING_IPV6_FORCE_MODE(x, y) \
+{ \
+unsigned int reg_val = sys_reg_read(LRO_RX_RING1_CTRL_DW0 + (((x) - 1) << 6)); \
+reg_val &= ~(0x1 << PDMA_RX_IPV6_FORCE_OFFSET); \
+reg_val |= (y) << PDMA_RX_IPV6_FORCE_OFFSET; \
+sys_reg_write(LRO_RX_RING1_CTRL_DW0 + (((x) - 1) << 6), reg_val); \
+}
+
+#define SET_PDMA_RXRING_AGE_TIME(x, y) \
+{ \
+unsigned int reg_val1 = sys_reg_read(LRO_RX_RING0_CTRL_DW1 + ((x) << 6)); \
+unsigned int reg_val2 = sys_reg_read(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \
+reg_val1 &= ~PDMA_LRO_RING_AGE1; \
+reg_val2 &= ~PDMA_LRO_RING_AGE2; \
+reg_val1 |= ((y) & 0x3ff) << PDMA_LRO_RING_AGE1_OFFSET; \
+reg_val2 |= (((y) >> PDMA_LRO_AGE_H_OFFSET) & 0x03f) << \
+ PDMA_LRO_RING_AGE2_OFFSET;\
+sys_reg_write(LRO_RX_RING0_CTRL_DW1 + ((x) << 6), reg_val1); \
+sys_reg_write(LRO_RX_RING0_CTRL_DW2 + ((x) << 6), reg_val2); \
+}
+
+#define SET_PDMA_RXRING_AGG_TIME(x, y) \
+{ \
+unsigned int reg_val = sys_reg_read(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \
+reg_val &= ~PDMA_LRO_RING_AGG; \
+reg_val |= ((y) & 0xffff) << PDMA_LRO_RING_AGG_OFFSET; \
+sys_reg_write(LRO_RX_RING0_CTRL_DW2 + ((x) << 6), reg_val); \
+}
+
+#define SET_PDMA_RXRING_MAX_AGG_CNT(x, y) \
+{ \
+unsigned int reg_val1 = sys_reg_read(LRO_RX_RING1_CTRL_DW2 + \
+ (((x) - 1) << 6)); \
+unsigned int reg_val2 = sys_reg_read(LRO_RX_RING1_CTRL_DW3 + \
+ (((x) - 1) << 6)); \
+reg_val1 &= ~PDMA_LRO_RING_AGG_CNT1; \
+reg_val2 &= ~PDMA_LRO_RING_AGG_CNT2; \
+reg_val1 |= ((y) & 0x3f) << PDMA_LRO_RING_AGG_CNT1_OFFSET; \
+reg_val2 |= (((y) >> PDMA_LRO_AGG_CNT_H_OFFSET) & 0x03) << \
+ PDMA_LRO_RING_AGG_CNT2_OFFSET; \
+sys_reg_write(LRO_RX_RING1_CTRL_DW2 + (((x) - 1) << 6), reg_val1); \
+sys_reg_write(LRO_RX_RING1_CTRL_DW3 + (((x) - 1) << 6), reg_val2); \
+}
+
+/* HW LRO debug functions */
+void hw_lro_stats_update(unsigned int ring_num,
+ struct PDMA_rxdesc *rx_ring);
+void hw_lro_flush_stats_update(unsigned int ring_num,
+ struct PDMA_rxdesc *rx_ring);
+
+#endif
diff --git a/src/kernel/modules/netsys_driver/nat/include/raether_qdma.h b/src/kernel/modules/netsys_driver/nat/include/raether_qdma.h
new file mode 100755
index 0000000..ce1af4d
--- /dev/null
+++ b/src/kernel/modules/netsys_driver/nat/include/raether_qdma.h
@@ -0,0 +1,20 @@
+/* Copyright 2016 MediaTek Inc.
+ * Author: Carlos Huang <carlos.huang@mediatek.com>
+ * Author: Harry Huang <harry.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef RAETHER_QDMA_H
+#define RAETHER_QDMA_H
+
+extern struct net_device *dev_raether;
+void set_fe_dma_glo_cfg(void);
+
+#endif
diff --git a/src/kernel/modules/netsys_driver/nat/include/raether_rss.h b/src/kernel/modules/netsys_driver/nat/include/raether_rss.h
new file mode 100755
index 0000000..07c073f
--- /dev/null
+++ b/src/kernel/modules/netsys_driver/nat/include/raether_rss.h
@@ -0,0 +1,104 @@
+/* Copyright 2016 MediaTek Inc.
+ * Author: Nelson Chang <nelson.chang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef RA_RSS_H
+#define RA_RSS_H
+
+#include "raeth_reg.h"
+
+#define NUM_RSS_RX_DESC 1024
+#define MAX_RX_RING_NUM_2RING 2
+
+/******RSS define*******/
+#define PDMA_RSS_EN BIT(0)
+#define PDMA_RSS_BUSY BIT(1)
+#define PDMA_RSS_CFG_REQ BIT(2)
+#define PDMA_RSS_CFG_RDY BIT(3)
+#define PDMA_RSS_INDR_TBL_SIZE BITS(4, 6)
+#define PDMA_RSS_IPV6_TYPE BITS(8, 10)
+#define PDMA_RSS_IPV4_TYPE BITS(12, 14)
+#define PDMA_RSS_IPV6_TUPLE_EN BITS(16, 20)
+#define PDMA_RSS_IPV4_TUPLE_EN BITS(24, 28)
+
+#define PDMA_RSS_EN_OFFSET (0)
+#define PDMA_RSS_BUSY_OFFSET (1)
+#define PDMA_RSS_CFG_REQ_OFFSET (2)
+#define PDMA_RSS_CFG_RDY_OFFSET (3)
+#define PDMA_RSS_INDR_TBL_SIZE_OFFSET (4)
+#define PDMA_RSS_IPV6_TYPE_OFFSET (8)
+#define PDMA_RSS_IPV4_TYPE_OFFSET (12)
+#define PDMA_RSS_IPV6_TUPLE_EN_OFFSET (16)
+#define PDMA_RSS_IPV4_TUPLE_EN_OFFSET (24)
+
+#define SET_PDMA_RSS_EN(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_RSS_GLO_CFG); \
+reg_val &= ~(PDMA_RSS_EN); \
+reg_val |= ((x) & 0x1) << PDMA_RSS_EN_OFFSET; \
+sys_reg_write(ADMA_RSS_GLO_CFG, reg_val); \
+}
+
+#define SET_PDMA_RSS_CFG_REQ(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_RSS_GLO_CFG); \
+reg_val &= ~(PDMA_RSS_CFG_REQ); \
+reg_val |= ((x) & 0x1) << PDMA_RSS_CFG_REQ_OFFSET; \
+sys_reg_write(ADMA_RSS_GLO_CFG, reg_val); \
+}
+
+#define SET_PDMA_RSS_IPV4_TYPE(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_RSS_GLO_CFG); \
+reg_val &= ~(PDMA_RSS_IPV4_TYPE); \
+reg_val |= ((x) & 0x7) << PDMA_RSS_IPV4_TYPE_OFFSET; \
+sys_reg_write(ADMA_RSS_GLO_CFG, reg_val); \
+}
+
+#define SET_PDMA_RSS_IPV6_TYPE(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_RSS_GLO_CFG); \
+reg_val &= ~(PDMA_RSS_IPV6_TYPE); \
+reg_val |= ((x) & 0x7) << PDMA_RSS_IPV6_TYPE_OFFSET; \
+sys_reg_write(ADMA_RSS_GLO_CFG, reg_val); \
+}
+
+#define SET_PDMA_RSS_IPV4_TUPLE_TYPE(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_RSS_GLO_CFG); \
+reg_val &= ~(PDMA_RSS_IPV4_TYPE); \
+reg_val |= ((x) & 0x7) << PDMA_RSS_IPV4_TUPLE_EN_OFFSET; \
+sys_reg_write(ADMA_RSS_GLO_CFG, reg_val); \
+}
+
+#define SET_PDMA_RSS_IPV6_TUPLE_TYPE(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_RSS_GLO_CFG); \
+reg_val &= ~(PDMA_RSS_IPV6_TYPE); \
+reg_val |= ((x) & 0x7) << PDMA_RSS_IPV6_TUPLE_EN_OFFSET; \
+sys_reg_write(ADMA_RSS_GLO_CFG, reg_val); \
+}
+
+#define SET_PDMA_RSS_INDR_TBL_SIZE(x) \
+{ \
+unsigned int reg_val = sys_reg_read(ADMA_RSS_GLO_CFG); \
+reg_val &= ~(PDMA_RSS_INDR_TBL_SIZE); \
+reg_val |= ((x) & 0x7) << PDMA_RSS_INDR_TBL_SIZE_OFFSET; \
+sys_reg_write(ADMA_RSS_GLO_CFG, reg_val); \
+}
+
+#define SET_PDMA_RSS_CR_VALUE(x, y) \
+{ \
+unsigned int reg_val = y; \
+sys_reg_write(x, reg_val); \
+}
+
+#endif