[Feature] add GA346 baseline version
Change-Id: Ic62933698569507dcf98240cdf5d9931ae34348f
diff --git a/src/tinysys/medmcu/.create-project b/src/tinysys/medmcu/.create-project
new file mode 100755
index 0000000..c7a3250
--- /dev/null
+++ b/src/tinysys/medmcu/.create-project
@@ -0,0 +1,35 @@
+#!/bin/bash
+
+if [ ${#} -ne 1 ]; then
+ echo "Usage: $(basename ${0}) ENVCFG_FILE" >&2
+ exit 1
+fi
+
+. ${1} || exit 1
+
+I='medmcu'
+
+if [ ${CREATE_PLATFORM} -eq 1 ]; then
+ echo "kernel: platform creation is not supported yet" >&2
+ exit 1
+else # project creation
+ PROJECT_ROOT='project/RV33_A'
+ BASE_PATH="${PROJECT_ROOT}/${BASE_PLATFORM}/${BASE_PROJECT_NAME}"
+ [ ${BASE_IS_INTERNAL} -eq 1 ] && \
+ BASE_PATH="${PROJECT_ROOT}/${BASE_PLATFORM}/internal/${BASE_PROJECT_NAME}"
+
+ if [ ! -d "${BASE_PATH}" ]; then
+ echo "${I}: base project ${BASE_PATH} does not exist. No-op."
+ exit 0
+ fi
+
+ TARGET_PATH="${PROJECT_ROOT}/${TARGET_PLATFORM}/${TARGET_PROJECT_NAME}"
+ [ ${TARGET_IS_INTERNAL} -eq 1 ] && \
+ TARGET_PATH="${PROJECT_ROOT}/${TARGET_PLATFORM}/internal/${TARGET_PROJECT_NAME}"
+
+ CP_CMD="rsync -rlpgoDvc --delete --exclude .git ${BASE_PATH}/ ${TARGET_PATH}"
+ echo "${I}: clone project: ${CP_CMD}"
+ eval ${CP_CMD} || exit 1
+fi
+
+exit 0
diff --git a/src/tinysys/medmcu/.gitignore b/src/tinysys/medmcu/.gitignore
new file mode 100644
index 0000000..11d4615
--- /dev/null
+++ b/src/tinysys/medmcu/.gitignore
@@ -0,0 +1,2 @@
+/drivers/RV33_A/mt68*
+/project/RV33_A/mt68*
diff --git a/src/tinysys/medmcu/Android.mk b/src/tinysys/medmcu/Android.mk
new file mode 100644
index 0000000..87aaf5f
--- /dev/null
+++ b/src/tinysys/medmcu/Android.mk
@@ -0,0 +1,87 @@
+# use new tinysys structure when TINYSYS_STRUCTURE_VERSION is 2
+ifeq (2,$(strip $(TINYSYS_STRUCTURE_VERSION)))
+
+LOCAL_PATH := $(call my-dir)
+include $(CLEAR_VARS)
+
+TINYSYS_MEDMCU := tinysys-medmcu
+TINYSYS_MEDMCU_IMAGE_NAME := medmcu.img
+TINYSYS_MEDMCU_CLEAN_MODULE := clean-$(TINYSYS_MEDMCU)
+TINYSYS_MEDMCU_INSTALLED_TARGET := $(PRODUCT_OUT)/$(TINYSYS_MEDMCU_IMAGE_NAME)
+TINYSYS_MEDMCU_SIGN_IMAGE_TARGET := $(addsuffix -verified$(suffix $(TINYSYS_MEDMCU_INSTALLED_TARGET)),$(basename $(TINYSYS_MEDMCU_INSTALLED_TARGET)))
+
+LOCAL_MODULE := $(TINYSYS_MEDMCU)
+LOCAL_MODULE_STEM := $(TINYSYS_MEDMCU_IMAGE_NAME)
+LOCAL_MODULE_CLASS := TINYSYS_OBJ
+LOCAL_MULTILIB := 32
+LOCAL_MODULE_OWNER := mtk
+LOCAL_MODULE_PATH := $(PRODUCT_OUT)
+include $(BUILD_SYSTEM)/base_rules.mk
+
+TINYSYS_MEDMCU_BUILT_INTERMEDIATES := \
+ $(call intermediates-dir-for,$(LOCAL_MODULE_CLASS),$(LOCAL_MODULE))
+TINYSYS_MEDMCU_DEPENDENT_FOLDERS := \
+ $(wildcard $(LOCAL_PATH) $(LOCAL_PATH)/../common $(LOCAL_PATH)/../kernel/*/FreeRTOS/Source $(LOCAL_PATH)/../private)
+TINYSYS_MEDMCU_MAKE_DEPENDENCIES := \
+ $(shell find $(TINYSYS_MEDMCU_DEPENDENT_FOLDERS) -name .git -prune -o -type f | sort)
+TINYSYS_MEDMCU_MAKE_DEPENDENCIES := \
+ $(filter-out %/.git %/.gitignore %/.gitattributes,$(TINYSYS_MEDMCU_MAKE_DEPENDENCIES))
+TINYSYS_MEDMCU_BUILD_CMD := \
+ PROJECT=$(MTK_TARGET_PROJECT) \
+ O=$(abspath $(TINYSYS_MEDMCU_BUILT_INTERMEDIATES)) \
+ BUILD_TYPE=$(if $(filter-out user,$(TARGET_BUILD_VARIANT)),debug,release) \
+ -C $(LOCAL_PATH)
+
+# Config header targets
+TINYSYS_MEDMCU_CONFIG_HEADER := $(TINYSYS_MEDMCU)-configheader
+
+.PHONY: $(TINYSYS_MEDMCU_CONFIG_HEADER)
+$(TINYSYS_MEDMCU_CONFIG_HEADER):
+ $(PREBUILT_MAKE_PREFIX)$(MAKE) $(TINYSYS_MEDMCU_BUILD_CMD) configheader
+
+# Main targets
+.PHONY: $(TINYSYS_MEDMCU)
+$(TINYSYS_MEDMCU): $(TINYSYS_MEDMCU_SIGN_IMAGE_TARGET)
+$(TINYSYS_MEDMCU_SIGN_IMAGE_TARGET):
+.KATI_RESTAT: $(LOCAL_INSTALLED_MODULE)
+
+$(LOCAL_BUILT_MODULE): $(TINYSYS_MEDMCU_MAKE_DEPENDENCIES) | check-$(TINYSYS_MEDMCU)-config
+ $(PREBUILT_MAKE_PREFIX)$(MAKE) $(TINYSYS_MEDMCU_BUILD_CMD)
+
+#ifneq (yes,$(MTK_REMAKE_SUBMAKE_FLAG))
+#$(LOCAL_BUILT_MODULE) $(TINYSYS_MEDMCU_CONFIG_HEADER): $(TINYSYS_MEDMCU_CLEAN_MODULE)
+#endif
+
+###########################################################
+# TinySys Check config
+###########################################################
+.PHONY: check-$(TINYSYS_MEDMCU)-config
+check-$(TINYSYS_MEDMCU)-config: $(TINYSYS_MEDMCU_CONFIG_HEADER)
+ifneq (yes,$(strip $(DISABLE_MTK_CONFIG_CHECK)))
+ python device/mediatek/build/build/tools/check_kernel_config.py --prjconfig $(MTK_TARGET_PROJECT_FOLDER)/ProjectConfig.mk --project $(MTK_TARGET_PROJECT) --header `find $(TINYSYS_MEDMCU_BUILT_INTERMEDIATES) -type f -name tinysys_config.h | tr "\n" "," | sed -e "s/,$$//"`
+else
+ -python device/mediatek/build/build/tools/check_kernel_config.py --prjconfig $(MTK_TARGET_PROJECT_FOLDER)/ProjectConfig.mk --project $(MTK_TARGET_PROJECT) --header `find $(TINYSYS_MEDMCU_BUILT_INTERMEDIATES) -type f -name tinysys_config.h | tr "\n" "," | sed -e "s/,$$//"`
+endif
+
+ifneq (,$(filter yes,$(MTK_TINYSYS_MEDMCU_SUPPORT)))
+.PHONY: check-mtk-config
+check-mtk-config: check-$(TINYSYS_MEDMCU)-config
+endif
+
+###########################################################
+# Collect NOTICE files
+###########################################################
+TINYSYS_MEDMCU_NOTICE_FILES := \
+ $(shell find $(LOCAL_PATH) -type f -name '*NOTICE*.txt' -printf '%P\n')
+TINYSYS_MEDMCU_NOTICE_FILES_INSTALLED := \
+ $(TINYSYS_MEDMCU_NOTICE_FILES:%=$(TARGET_OUT_NOTICE_FILES)/src/tinysys/%)
+
+$(TARGET_OUT_INTERMEDIATES)/NOTICE.html: $(TINYSYS_MEDMCU_NOTICE_FILES_INSTALLED)
+
+$(TINYSYS_MEDMCU_NOTICE_FILES_INSTALLED): \
+ $(TARGET_OUT_NOTICE_FILES)/src/tinysys/%: $(LOCAL_PATH)/% | $(ACP)
+ @echo Copying: $@
+ $(hide) mkdir -p $(dir $@)
+ $(hide) $(ACP) $< $
+
+endif
diff --git a/src/tinysys/medmcu/CleanSpec.mk b/src/tinysys/medmcu/CleanSpec.mk
new file mode 100644
index 0000000..94e06e1
--- /dev/null
+++ b/src/tinysys/medmcu/CleanSpec.mk
@@ -0,0 +1,4 @@
+# Copyright (c) 2016 MediaTek Inc.
+#
+# A dummy CleanSpec.mk prevents Android findleaves.py from unnecessary diving
+# into the underlying directories to look up this file.
diff --git a/src/tinysys/medmcu/Makefile b/src/tinysys/medmcu/Makefile
new file mode 100644
index 0000000..001a513
--- /dev/null
+++ b/src/tinysys/medmcu/Makefile
@@ -0,0 +1,160 @@
+# Copyright Statement:
+#
+# This software/firmware and related documentation ("MediaTek Software") are
+# protected under relevant copyright laws. The information contained herein
+# is confidential and proprietary to MediaTek Inc. and/or its licensors.
+# Without the prior written permission of MediaTek inc. and/or its licensors,
+# any reproduction, modification, use or disclosure of MediaTek Software,
+# and information contained herein, in whole or in part, shall be strictly
+# prohibited.
+#
+# MediaTek Inc. (C) 2018. All rights reserved.
+#
+# BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+# THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+# RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+# AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+# NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+# SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+# SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+# THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
+# ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
+# THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
+# SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
+# RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
+# FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+# CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
+# WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
+# AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
+# RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+#
+# The following software/firmware and/or related documentation
+# ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
+# subject to any receiver\'s applicable license agreements with MediaTek Inc.
+#
+###########################################################
+## Generic definitions
+###########################################################
+# Remove $@ if error occurs
+.DELETE_ON_ERROR:
+
+# Turn off suffix build rules built into make
+.SUFFIXES:
+
+SHELL := /bin/bash
+TINYSYS_MEDMCU := tinysys-medmcu
+
+.DEFAULT_GOAL := scp
+
+###########################################################
+## Parameter control
+###########################################################
+PROJECT := $(strip $(PROJECT))
+ifeq ($(PROJECT),)
+ $(error $(TINYSYS_MEDMCU): project name is required)
+endif
+
+ifeq ($(strip $(O)),)
+O := tinysys_out
+endif
+
+# Verbosity control
+V ?= 1
+ifeq ($(V),1)
+hide :=
+else
+hide := @
+endif
+
+###########################################################
+## Common directory locations and generic variables
+###########################################################
+SCP_DIR := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST))))
+SCP_IMAGE_NAME := medmcu.img
+SCP_BUILT_DIR := $(O)
+SCP_INSTALLED_TARGET := $(O)/$(SCP_IMAGE_NAME)
+
+SCP_PROJECT_DIR := $(SCP_DIR)/project
+SCP_DRIVERS_DIR := $(SCP_DIR)/drivers
+SCP_KERNEL_DIR := $(SCP_DIR)/kernel
+SCP_BUILD_DIR := $(SCP_DIR)/build
+SCP_TOOLS_DIR := $(SCP_DIR)/tools
+SCP_MIDDLEWARE_DIR := $(SCP_DIR)/middleware
+
+KERNEL_DIR := $(SCP_DIR)/../kernel
+COMMON_DIR := $(SCP_DIR)/../common
+PRIVATE_DIR := $(SCP_DIR)/../private
+COMMON_DRIVERS_DIR := $(COMMON_DIR)/drivers
+COMMON_MIDDLEWARE_DIR := $(COMMON_DIR)/middleware
+COMMON_BUILD_DIR := $(COMMON_DIR)/build
+COMMON_TOOLS_DIR := $(COMMON_DIR)/tools
+COMMON_INCLUDE_DIR := $(COMMON_DIR)/include
+PRIVATE_DRIVERS_DIR := $(PRIVATE_DIR)/drivers
+PRIVATE_MIDDLEWARE_DIR := $(PRIVATE_DIR)/middleware
+PRIVATE_BUILD_DIR := $(PRIVATE_DIR)/build
+PRIVATE_TOOLS_DIR := $(PRIVATE_DIR)/tools
+
+MKIMAGE := $(COMMON_TOOLS_DIR)/mkimage
+OBJSIZE := $(COMMON_TOOLS_DIR)/objsize
+MCHECK := $(COMMON_TOOLS_DIR)/memoryReport.py
+GEN_LINK_LD := $(SCP_TOOLS_DIR)/link_ld.py
+
+###########################################################
+## Generic build flow
+###########################################################
+include $(COMMON_BUILD_DIR)/definitions.mk
+-include $(SCP_BUILD_DIR)/definitions.mk
+
+# Initialize the environment for each processor
+include $(SCP_BUILD_DIR)/main.mk
+
+ifeq (1,$(V))
+ $(info $(TINYSYS_MEDMCU): PROCESSORS=$(PROCESSORS))
+ $(info $(TINYSYS_MEDMCU): PROJECT=$(PROJECT))
+ $(info $(TINYSYS_MEDMCU): PLATFORM=$(PLATFORM))
+ $(info $(TINYSYS_MEDMCU): O=$(O))
+ $(info $(TINYSYS_MEDMCU): SCP_DIR=$(SCP_DIR))
+ $(info $(TINYSYS_MEDMCU): ALL_SCP_BINS=$(ALL_SCP_BINS))
+ $(info $(TINYSYS_MEDMCU): ALL_SCP_ESL_BINS=$(ALL_SCP_ESL_BINS))
+endif
+
+SCP_SETTING_INI := $(SCP_PROJECT_DIR)/$(word 1,$(PROCESSORS))/$(PLATFORM)/platform/Setting.ini
+
+###########################################################
+## Build targets
+###########################################################
+.PHONY: scp
+
+ifneq (,$(ALL_SCP_BINS))
+scp: $(SCP_INSTALLED_TARGET)
+
+SORTED_SCP_BINS := $(call sort_scp_binaries,$(ALL_SCP_BINS),RV33)
+
+$(SCP_INSTALLED_TARGET): $(SORTED_SCP_BINS)
+ @mkdir -p $(dir $@)
+ @echo '$(TINYSYS_MEDMCU): BIN $@'
+ @if [ -s '$($(PROCESSOR)_DRAM.BIN_BUILT)' ]; then \
+ if [ -s '$($(PROCESSOR)_MEDHW.BIN_BUILT)' ]; then \
+ echo 'cat $^ $($(PROCESSOR)_DRAM.BIN_BUILT) $($(PROCESSOR)_MEDHW.BIN_BUILT) > $@'; \
+ cat $^ $($(PROCESSOR)_DRAM.BIN_BUILT) $($(PROCESSOR)_MEDHW.BIN_BUILT) > $@; \
+ else \
+ echo 'cat $^ $($(PROCESSOR)_DRAM.BIN_BUILT) > $@'; \
+ cat $^ $($(PROCESSOR)_DRAM.BIN_BUILT) > $@; \
+ fi; \
+ elif [ -s '$($(PROCESSOR)_MEDHW.BIN_BUILT)' ]; then \
+ echo 'cat $^ $($(PROCESSOR)_MEDHW.BIN_BUILT) > $@'; \
+ cat $^ $($(PROCESSOR)_MEDHW.BIN_BUILT) > $@; \
+ else \
+ echo 'cat $^ > $@'; \
+ cat $^ > $@; \
+ fi;
+endif
+
+ifneq (,$(ALL_SCP_ESL_BINS))
+scp: $(ALL_SCP_ESL_BINS)
+endif
+
+clean:
+ rm -rf $(SCP_INSTALLED_TARGET) $(O)
diff --git a/src/tinysys/medmcu/NOTICE b/src/tinysys/medmcu/NOTICE
new file mode 100644
index 0000000..c61f927
--- /dev/null
+++ b/src/tinysys/medmcu/NOTICE
@@ -0,0 +1,17 @@
+
+The MIT License
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the Software without restriction, including without limitation the
+rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit
+persons to whom the Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all copies or substantial portions of the
+Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+
diff --git a/src/tinysys/medmcu/build/clear_vars.mk b/src/tinysys/medmcu/build/clear_vars.mk
new file mode 100644
index 0000000..d5e5670
--- /dev/null
+++ b/src/tinysys/medmcu/build/clear_vars.mk
@@ -0,0 +1,12 @@
+ESL_AP_C_FILES :=
+ESL_AP_S_FILES :=
+ESL_MCU_C_FILES :=
+ESL_MCU_S_FILES :=
+ESL_AP_C_OBJS :=
+ESL_AP_S_OBJS :=
+ESL_MCU_C_OBJS :=
+ESL_MCU_S_OBJS :=
+ESL_AP_OBJS :=
+ESL_MCU_OBJS :=
+ESL_C_OBJS :=
+ESL_S_OBJS :=
diff --git a/src/tinysys/medmcu/build/config.mk b/src/tinysys/medmcu/build/config.mk
new file mode 100644
index 0000000..4dc0a92
--- /dev/null
+++ b/src/tinysys/medmcu/build/config.mk
@@ -0,0 +1,558 @@
+include $(COMMON_BUILD_DIR)/clear_vars.mk
+-include $(SCP_BUILD_DIR)/clear_vars.mk
+
+###########################################################
+## Common SCP build environment
+###########################################################
+RV33_VAR := MRV33E25
+REL_ROOT_DIR := ../../../..
+CROSS_COMPILE = $(REL_ROOT_DIR)/prebuilt/clang/md32rv/linux-x86
+#CROSS_COMPILE = /mtkeda/Utility/CodeLine/md32rv/1.4.1/ToolChain/LLVM/
+#CROSS_COMPILE = /mtkeda/Utility/Doble/md32rv/rv1.4.1_printf/ToolChain/LLVM/
+CC := $(CROSS_COMPILE)/bin/clang
+CPP := $(CROSS_COMPILE)/bin/clang-cpp
+LLD := $(CROSS_COMPILE)/bin/ld.lld
+#LLD := /mtkeda/Utility/Doble/md32rv/alpha70/ToolChain/LLVM/bin/ld.lld
+AR := $(CROSS_COMPILE)/bin/llvm-ar
+RANLIB := $(CROSS_COMPILE)/bin/llvm-ranlib
+OBJCOPY := $(CROSS_COMPILE)/bin/llvm-objcopy
+OBJDUMP := $(CROSS_COMPILE)/bin/llvm-objdump
+SIZE := $(CROSS_COMPILE)/bin/llvm-size
+STRIP := $(CROSS_COMPILE)/bin/strip
+READELF := $(CROSS_COMPILE)/bin/llvm-readelf
+LLVM_RTLIB := $(CROSS_COMPILE)/lib/clang/7.0.0/lib/riscv32/$(RV33_VAR)
+LLVM_DKWLIB := $(CROSS_COMPILE)/dkwlib/$(RV33_VAR)/lib
+LLVM_NEWLIB := $(CROSS_COMPILE)/riscv32-elf/$(RV33_VAR)/lib
+LLVM_INCLUDE := $(CROSS_COMPILE)/riscv32-elf/$(RV33_VAR)/include
+
+LLVM_DKWINC := $(COMMON_INCLUDE_DIR)/dkwlib_inc/
+#TMP_MODULE_ROOT := /proj/mtk11261/misc/alps/vendor/mediatek/proprietary/tinysys/private/ESL_simulator/ESL_RV33/toolchain/riscv32
+#GOBJDUMP := $(TMP_MODULE_ROOT)/bin/riscv32-unknown-elf-objdump
+#READELF := $(TMP_MODULE_ROOT)/bin/riscv32-unknown-elf-readelf
+#OBJCOPY := $(TMP_MODULE_ROOT)/bin/riscv32-unknown-elf-objcopy
+# Apply default environment if CROSS_COMPILE is not defined
+ifeq (,$(CROSS_COMPILE))
+ REL_ROOT_DIR := ../../../../..
+ MRV_MODULE_ROOT := $(REL_ROOT_DIR)/prebuilt/clang/md32rv/linux-x86
+
+ CC := $(MRV_MODULE_ROOT)/bin/clang
+ CPP := $(MRV_MODULE_ROOT)/bin/clang-cpp
+ LLD := $(MRV_MODULE_ROOT)/bin/ld.lld
+ AR := $(MRV_MODULE_ROOT)/bin/llvm-ar
+ RANLIB := $(MRV_MODULE_ROOT)/bin/llvm-ranlib
+ OBJCOPY := $(MRV_MODULE_ROOT)/bin/llvm-objcopy
+ OBJDUMP := $(MRV_MODULE_ROOT)/bin/llvm-objdump
+ SIZE := $(MRV_MODULE_ROOT)/bin/llvm-size
+ #STRIP := $(MRV_MODULE_ROOT)/bin/strip
+ READELF := $(MRV_MODULE_ROOT)/bin/llvm-readelf
+ LLVM_RTLIB := $(MRV_MODULE_ROOT)/lib/clang/5.0.1/lib/riscv32/$(RV33_VAR)
+ LLVM_NEWLIB := $(MRV_MODULE_ROOT)/riscv32-elf/$(RV33_VAR)/lib
+endif # CROSS_COMPILE is not defined
+
+ifeq (1,$(V))
+ $(info $(TINYSYS_MEDMCU): CC=$(CC))
+ $(info $(TINYSYS_MEDMCU): CPP=$(CPP))
+ $(info $(TINYSYS_MEDMCU): LLD=$(LLD))
+ $(info $(TINYSYS_MEDMCU): AR=$(AR))
+ $(info $(TINYSYS_MEDMCU): RANLIB=$(RANLIB))
+ $(info $(TINYSYS_MEDMCU): OBJCOPY=$(OBJCOPY))
+ $(info $(TINYSYS_MEDMCU): OBJDUMP=$(OBJDUMP))
+ $(info $(TINYSYS_MEDMCU): SIZE=$(SIZE))
+ $(info $(TINYSYS_MEDMCU): STRIP=$(STRIP))
+ $(info $(TINYSYS_MEDMCU): READELF=$(READELF))
+ $(info $(TINYSYS_MEDMCU): LLVM_RTLIB=$(LLVM_RTLIB))
+ $(info $(TINYSYS_MEDMCU): LLVM_DKWLIB=$(LLVM_DKWLIB))
+endif
+
+CFLAGS += -Werror -Wall -Wextra -Wshadow -Wpointer-arith -Wbad-function-cast \
+ -Wcast-align -Wsign-compare -Waggregate-return -Wstrict-prototypes \
+ -Wmissing-prototypes -Wmissing-declarations -Wunused \
+ -Wno-unused-parameter -Wno-format \
+ -g -fomit-frame-pointer -fno-strict-aliasing \
+ -fno-builtin -mllvm -enable-printf-opt=false -Os -D__gracefulExit -DLLVM \
+ --target=riscv32-unknown-elf -mcpu=$(RV33_VAR)
+
+# Define build type. Default to release
+BUILD_TYPE ?= release
+
+ifeq (1,$(V))
+ $(info $(TINYSYS_MEDMCU): BUILD_TYPE=$(BUILD_TYPE))
+endif
+
+ifeq (debug,$(strip $(BUILD_TYPE)))
+ CFLAGS += -DTINYSYS_DEBUG_BUILD
+endif
+
+###########################################################
+## Processor-based environment and targets
+###########################################################
+PROCESSOR_DIR := $(SCP_PROJECT_DIR)/$(PROCESSOR)
+PLATFORM_BASE_DIR := $(PROCESSOR_DIR)/$(PLATFORM)
+PLATFORM_DIR := $(PLATFORM_BASE_DIR)/platform
+PROJECT_DIR := $(PLATFORM_BASE_DIR)/$(PROJECT)
+ifeq (,$(wildcard $(PROJECT_DIR)))
+PROJECT_DIR := $(PLATFORM_BASE_DIR)/internal/$(PROJECT)
+endif
+PLATFORM_FEATURES_DIR := $(PLATFORM_DIR)/features
+SCP_BUILT_DIR := $(SCP_BUILT_DIR)/$(PROCESSOR)/medmcu
+DRIVERS_PLATFORM_DIR := $(SCP_DRIVERS_DIR)/$(PROCESSOR)/$(PLATFORM)
+GENERATED_DIR := $(SCP_BUILT_DIR)/generated
+GENERATED_INCLUDE_DIR := $(GENERATED_DIR)/include
+$(PROCESSOR).TINYSYS_CONFIG_H := $(GENERATED_INCLUDE_DIR)/tinysys_config.h
+$(PROCESSOR).BIN_BUILT := \
+ $(SCP_BUILT_DIR)/$(TINYSYS_MEDMCU)-$(PROCESSOR).bin
+
+$(PROCESSOR)_MEDHW_GC0_PM.BIN_BUILT := $(SCP_BUILT_DIR)/medhw-gc0-pm.bin
+$(PROCESSOR)_MEDHW_GC1_PM.BIN_BUILT := $(SCP_BUILT_DIR)/medhw-gc1-pm.bin
+$(PROCESSOR)_MEDHW_GC2_PM.BIN_BUILT := $(SCP_BUILT_DIR)/medhw-gc2-pm.bin
+$(PROCESSOR)_MEDHW_GC0_DM.BIN_BUILT := $(SCP_BUILT_DIR)/medhw-gc0-dm.bin
+$(PROCESSOR)_MEDHW_GC1_DM.BIN_BUILT := $(SCP_BUILT_DIR)/medhw-gc1-dm.bin
+$(PROCESSOR)_MEDHW_GC2_DM.BIN_BUILT := $(SCP_BUILT_DIR)/medhw-gc2-dm.bin
+$(PROCESSOR)_MEDHW.BIN_BUILT := $(SCP_BUILT_DIR)/medhw.bin
+
+# Set to no on DVT and SLT load
+CFG_HEAP_ON_L1TCM = yes
+
+ifeq (yes,$(CFG_HEAP_ON_L1TCM))
+$(PROCESSOR)_L1TCM.BIN_BUILT := \
+ $(SCP_BUILT_DIR)/$(TINYSYS_MEDMCU)-$(PROCESSOR)_L1TCM.bin
+else
+$(PROCESSOR)_DRAM.BIN_BUILT := \
+ $(SCP_BUILT_DIR)/$(TINYSYS_MEDMCU)-$(PROCESSOR)_DRAM.bin
+endif
+$(PROCESSOR).LINK_LD := $(SCP_BUILT_DIR)/link.ld
+
+
+SCP_BIN_STEM := $(basename $($(PROCESSOR).BIN_BUILT))
+$(PROCESSOR).BIN_NH := $(SCP_BIN_STEM)-no-mtk-header.bin
+$(PROCESSOR).BIN_MEDHW_NH := $(DRIVERS_PLATFORM_DIR)/med/medhw/bin
+MEDHW_GC0_PM := assembly_code_medhw_gc0.bin
+MEDHW_GC1_PM := assembly_code_medhw_gc1.bin
+MEDHW_GC2_PM := assembly_code_medhw_gc2.bin
+MEDHW_GC0_DM := dm_data_medhw_gc0.bin
+MEDHW_GC1_DM := dm_data_medhw_gc1.bin
+MEDHW_GC2_DM := dm_data_medhw_gc2.bin
+ifeq (yes,$(CFG_HEAP_ON_L1TCM))
+$(PROCESSOR).BIN_L1TCM_NH := $(SCP_BIN_STEM)_L1TCM-no-mtk-header.bin
+else
+$(PROCESSOR).BIN_DRAM_NH := $(SCP_BIN_STEM)_DRAM-no-mtk-header.bin
+endif
+$(PROCESSOR).ELF_FILE := $(SCP_BIN_STEM).elf
+$(PROCESSOR).MAP_FILE := $(SCP_BIN_STEM).map
+$(PROCESSOR).ASM_FILE := $(SCP_BIN_STEM).asm
+$(PROCESSOR).ASM2_FILE := $(SCP_BIN_STEM).asm2
+$(PROCESSOR).RELF_FILE := $(SCP_BIN_STEM).relf
+$(PROCESSOR).IMG_HDR_CFG := $(SCP_BUILT_DIR)/img_hdr_$(notdir $(SCP_BIN_STEM)).cfg
+$(PROCESSOR)_MEDHW_GC0_PM.IMG_HDR_CFG := $(SCP_BUILT_DIR)/img_hdr_medhw-gc0-pm.cfg
+$(PROCESSOR)_MEDHW_GC1_PM.IMG_HDR_CFG := $(SCP_BUILT_DIR)/img_hdr_medhw-gc1-pm.cfg
+$(PROCESSOR)_MEDHW_GC2_PM.IMG_HDR_CFG := $(SCP_BUILT_DIR)/img_hdr_medhw-gc2-pm.cfg
+$(PROCESSOR)_MEDHW_GC0_DM.IMG_HDR_CFG := $(SCP_BUILT_DIR)/img_hdr_medhw-gc0-dm.cfg
+$(PROCESSOR)_MEDHW_GC1_DM.IMG_HDR_CFG := $(SCP_BUILT_DIR)/img_hdr_medhw-gc1-dm.cfg
+$(PROCESSOR)_MEDHW_GC2_DM.IMG_HDR_CFG := $(SCP_BUILT_DIR)/img_hdr_medhw-gc2-dm.cfg
+ifeq (yes,$(CFG_HEAP_ON_L1TCM))
+$(PROCESSOR)_L1TCM.IMG_HDR_CFG := $(SCP_BUILT_DIR)/img_hdr_$(notdir $(SCP_BIN_STEM))_l1tcm.cfg
+else
+$(PROCESSOR)_DRAM.IMG_HDR_CFG := $(SCP_BUILT_DIR)/img_hdr_$(notdir $(SCP_BIN_STEM))_dram.cfg
+endif
+
+# ESL-specific outputs
+$(PROCESSOR).ESL_AP_LINK_LD := $(SCP_BUILT_DIR)/link.ap.ld
+$(PROCESSOR).ESL_MCU0_LINK_LD := $(SCP_BUILT_DIR)/link.mcu0.ld
+$(PROCESSOR).ESL_MCU1_LINK_LD := $(SCP_BUILT_DIR)/link.mcu1.ld
+$(PROCESSOR).ESL_AP_ELF := $(SCP_BIN_STEM).ap.elf
+$(PROCESSOR).ESL_MCU0_ELF := $(SCP_BIN_STEM).mcu0.elf
+$(PROCESSOR).ESL_MCU1_ELF := $(SCP_BIN_STEM).mcu1.elf
+$(PROCESSOR).ESL_AP_MAP := $(SCP_BIN_STEM).ap.map
+$(PROCESSOR).ESL_MCU0_MAP := $(SCP_BIN_STEM).mcu0.map
+$(PROCESSOR).ESL_MCU1_MAP := $(SCP_BIN_STEM).mcu1.map
+$(PROCESSOR).ESL_AP_ASM := $(SCP_BIN_STEM).ap.asm
+$(PROCESSOR).ESL_MCU0_ASM := $(SCP_BIN_STEM).mcu0.asm
+$(PROCESSOR).ESL_MCU1_ASM := $(SCP_BIN_STEM).mcu1.asm
+$(PROCESSOR).ESL_AP_BIN := $(SCP_BIN_STEM).ap.bin
+$(PROCESSOR).ESL_MCU0_BIN := $(SCP_BIN_STEM).mcu0.bin
+$(PROCESSOR).ESL_MCU1_BIN := $(SCP_BIN_STEM).mcu1.bin
+
+PLATFORM_MK := $(PLATFORM_DIR)/platform.mk
+ifeq ($(wildcard $(PLATFORM_MK)),)
+ $(error $(TINYSYS_MEDMCU): $(PLATFORM_MK) is missing)
+endif
+
+# Reset any previously defined SCP options before including my own definitions
+$(foreach v,$(SCP_PREVIOUS_CFG_OPTS), \
+ $(eval $(v) := ) \
+)
+scp_old_cfgs := $(.VARIABLES)
+
+include $(PLATFORM_MK)
+
+scp_new_cfgs := $(.VARIABLES)
+SCP_PREVIOUS_CFG_OPTS := \
+ $(filter CFG_%,$(filter-out $(scp_old_cfgs),$(scp_new_cfgs)))
+
+ifneq (yesyes,$(CFG_ESL_BUILD)$(CFG_ESL_DUAL_CORE))
+ ALL_SCP_BINS := $(ALL_SCP_BINS) $($(PROCESSOR).BIN_BUILT)
+else
+ ALL_SCP_ESL_BINS := $(ALL_SCP_ESL_BINS) \
+ $($(PROCESSOR).ESL_AP_BIN) \
+ $($(PROCESSOR).ESL_MCU0_BIN) \
+ $($(PROCESSOR).ESL_MCU1_BIN)
+endif
+
+INCLUDES += $(GENERATED_INCLUDE_DIR)
+INCLUDES += $(LLVM_DKWINC)
+CFLAGS += -include $($(PROCESSOR).TINYSYS_CONFIG_H)
+
+# Include project-specific files only when available
+ifneq ($(wildcard $(PROJECT_DIR)/inc),)
+ INCLUDES += $(PROJECT_DIR)/inc
+endif
+
+ifneq ($(wildcard $(PROJECT_DIR)/src/project.c),)
+ C_FILES += $(wildcard $(PROJECT_DIR)/src/project.c)
+endif
+
+C_FILES := $(patsubst ./%,%,$(C_FILES))
+S_FILES := $(patsubst ./%,%,$(S_FILES))
+C_OBJS := $(sort $(C_FILES:%.c=$(SCP_BUILT_DIR)/%.o))
+S_OBJS := $(sort $(S_FILES:%.S=$(SCP_BUILT_DIR)/%.o))
+
+OBJS += $(sort $(C_OBJS) $(S_OBJS))
+$(OBJS): $($(PROCESSOR).TINYSYS_CONFIG_H)
+
+# Set dependency
+DEPS += $(sort $(filter-out %.d,$(MAKEFILE_LIST)))
+
+# Stash the list of configuration names and values to generate config header
+CONFIG_MK_FILES := \
+ $(PLATFORM_MK) \
+ $(wildcard $(PROJECT_DIR)/project.mk)
+$(call stash_config_options,$(CONFIG_MK_FILES))
+
+INCLUDES := $(call normalize-includes,$(INCLUDES))
+
+###########################################################
+## Generic build targets
+###########################################################
+$(C_OBJS): PRIVATE_BUILD_TAG := $(TINYSYS_MEDMCU)
+$(C_OBJS): PRIVATE_CC := $(CC)
+$(C_OBJS): PRIVATE_CFLAGS := $(CFLAGS)
+$(C_OBJS): PRIVATE_INCLUDES := $(INCLUDES)
+$(C_OBJS): $(SCP_BUILT_DIR)/%.o: %.c
+ $(compile-c-or-s-to-o)
+
+$(S_OBJS): PRIVATE_BUILD_TAG := $(TINYSYS_MEDMCU)
+$(S_OBJS): PRIVATE_CC := $(CC)
+$(S_OBJS): PRIVATE_CFLAGS := $(CFLAGS)
+$(S_OBJS): PRIVATE_INCLUDES := $(INCLUDES)
+$(S_OBJS): $(SCP_BUILT_DIR)/%.o: %.S
+ $(compile-c-or-s-to-o)
+
+# Generate header file that contains all config options and its values
+.PHONY: configheader
+configheader: $($(PROCESSOR).TINYSYS_CONFIG_H)
+
+.PHONY: $($(PROCESSOR).TINYSYS_CONFIG_H)
+$($(PROCESSOR).TINYSYS_CONFIG_H): PRIVATE_PROCESSOR := $(PROCESSOR)
+$($(PROCESSOR).TINYSYS_CONFIG_H):
+ $(call gen-tinysys-header,__TINYSYS_CONFIG_H, \
+ $($(PRIVATE_PROCESSOR).CONFIG_OPTIONS), $(TINYSYS_MEDMCU),)
+
+$(OBJS): $(DEPS)
+-include $(OBJS:.o=.d)
+
+###########################################################
+## Processor-based SCP build targets
+###########################################################
+$($(PROCESSOR).BIN_BUILT): PRIVATE_PROCESSOR:= $(PROCESSOR)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_BIN_NH := $($(PROCESSOR).BIN_NH)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_BUILT_DIR := $(SCP_BUILT_DIR)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_IMG_HDR_CFG := $($(PROCESSOR).IMG_HDR_CFG)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_BIN_MEDHW_GC0_PM_BUILT := $($(PROCESSOR)_MEDHW_GC0_PM.BIN_BUILT)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_BIN_MEDHW_GC1_PM_BUILT := $($(PROCESSOR)_MEDHW_GC1_PM.BIN_BUILT)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_BIN_MEDHW_GC2_PM_BUILT := $($(PROCESSOR)_MEDHW_GC2_PM.BIN_BUILT)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_BIN_MEDHW_GC0_DM_BUILT := $($(PROCESSOR)_MEDHW_GC0_DM.BIN_BUILT)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_BIN_MEDHW_GC1_DM_BUILT := $($(PROCESSOR)_MEDHW_GC1_DM.BIN_BUILT)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_BIN_MEDHW_GC2_DM_BUILT := $($(PROCESSOR)_MEDHW_GC2_DM.BIN_BUILT)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_BIN_MEDHW_NH := $($(PROCESSOR).BIN_MEDHW_NH)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_MEDHW_GC0_PM_IMG_HDR_CFG := $($(PROCESSOR)_MEDHW_GC0_PM.IMG_HDR_CFG)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_MEDHW_GC1_PM_IMG_HDR_CFG := $($(PROCESSOR)_MEDHW_GC1_PM.IMG_HDR_CFG)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_MEDHW_GC2_PM_IMG_HDR_CFG := $($(PROCESSOR)_MEDHW_GC2_PM.IMG_HDR_CFG)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_MEDHW_GC0_DM_IMG_HDR_CFG := $($(PROCESSOR)_MEDHW_GC0_DM.IMG_HDR_CFG)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_MEDHW_GC1_DM_IMG_HDR_CFG := $($(PROCESSOR)_MEDHW_GC1_DM.IMG_HDR_CFG)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_MEDHW_GC2_DM_IMG_HDR_CFG := $($(PROCESSOR)_MEDHW_GC2_DM.IMG_HDR_CFG)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_ELF_FILE := $($(PROCESSOR).ELF_FILE)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_PLATFORM_DIR := $(PLATFORM_DIR)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_PROJECT_DIR := $(PROJECT_DIR)
+ifeq (yes,$(CFG_HEAP_ON_L1TCM))
+$($(PROCESSOR).BIN_BUILT): PRIVATE_BIN_L1TCM_BUILT := $($(PROCESSOR)_L1TCM.BIN_BUILT)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_BIN_L1TCM_NH := $($(PROCESSOR).BIN_L1TCM_NH)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_L1TCM_IMG_HDR_CFG := $($(PROCESSOR)_L1TCM.IMG_HDR_CFG)
+else
+$($(PROCESSOR).BIN_BUILT): PRIVATE_BIN_DRAM_BUILT := $($(PROCESSOR)_DRAM.BIN_BUILT)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_BIN_DRAM_NH := $($(PROCESSOR).BIN_DRAM_NH)
+$($(PROCESSOR).BIN_BUILT): PRIVATE_DRAM_IMG_HDR_CFG := $($(PROCESSOR)_DRAM.IMG_HDR_CFG)
+endif
+$($(PROCESSOR).BIN_BUILT): PRIVATE_OBJCOPY := $(OBJCOPY)
+
+ifeq (yes,$(CFG_HEAP_ON_L1TCM))
+$($(PROCESSOR).BIN_BUILT): $($(PROCESSOR).ELF_FILE) \
+ $($(PROCESSOR).IMG_HDR_CFG) $($(PROCESSOR)_DRAM.IMG_HDR_CFG) $(DEPS) \
+ $($(PROCESSOR)_MEDHW_GC0_PM.IMG_HDR_CFG) $($(PROCESSOR)_MEDHW_GC1_PM.IMG_HDR_CFG) $($(PROCESSOR)_MEDHW_GC2_PM.IMG_HDR_CFG) \
+ $($(PROCESSOR)_MEDHW_GC0_DM.IMG_HDR_CFG) $($(PROCESSOR)_MEDHW_GC1_DM.IMG_HDR_CFG) $($(PROCESSOR)_MEDHW_GC2_DM.IMG_HDR_CFG) $(DEPS) \
+ | $(OBJSIZE) $(MKIMAGE)
+else
+$($(PROCESSOR).BIN_BUILT): $($(PROCESSOR).ELF_FILE) \
+ $($(PROCESSOR).IMG_HDR_CFG) $($(PROCESSOR)_L1TCM.IMG_HDR_CFG) $(DEPS) \
+ $($(PROCESSOR)_MEDHW_GC0_PM.IMG_HDR_CFG) $($(PROCESSOR)_MEDHW_GC1_PM.IMG_HDR_CFG) $($(PROCESSOR)_MEDHW_GC2_PM.IMG_HDR_CFG) \
+ $($(PROCESSOR)_MEDHW_GC0_DM.IMG_HDR_CFG) $($(PROCESSOR)_MEDHW_GC1_DM.IMG_HDR_CFG) $($(PROCESSOR)_MEDHW_GC2_DM.IMG_HDR_CFG) $(DEPS) \
+ | $(OBJSIZE) $(MKIMAGE)
+endif
+ @echo '$(TINYSYS_MEDMCU): BIN $@'
+ifeq (yes,$(CFG_HEAP_ON_L1TCM))
+ $(hide)$(PRIVATE_OBJCOPY) -O binary --remove-section .l1tcm_region $(PRIVATE_ELF_FILE) $(PRIVATE_BIN_NH)
+ #$(hide)$(PRIVATE_OBJCOPY) -O binary $(PRIVATE_ELF_FILE) $(PRIVATE_BIN_NH)
+ -rm -f $(PRIVATE_BIN_L1TCM_NH)
+ -rm -f $(PRIVATE_BIN_L1TCM_BUILT)
+ -$(hide)$(PRIVATE_OBJCOPY) -O binary --only-keep=.l1tcm_region $(PRIVATE_ELF_FILE) $(PRIVATE_BIN_L1TCM_NH)
+
+ @if [ -s '$(PRIVATE_BIN_L1TCM_NH)' ]; then \
+ echo "$(TINYSYS_MEDMCU): enable cache support for $(PRIVATE_PROCESSOR)"; \
+ $(MKIMAGE) $(PRIVATE_BIN_L1TCM_NH) $(PRIVATE_L1TCM_IMG_HDR_CFG) > $(PRIVATE_BIN_L1TCM_BUILT); \
+ fi;
+else
+ $(hide)$(PRIVATE_OBJCOPY) -O binary --remove-section .dram_region $(PRIVATE_ELF_FILE) $(PRIVATE_BIN_NH)
+ #$(hide)$(PRIVATE_OBJCOPY) -O binary $(PRIVATE_ELF_FILE) $(PRIVATE_BIN_NH)
+ -rm -f $(PRIVATE_BIN_DRAM_NH)
+ -rm -f $(PRIVATE_BIN_DRAM_BUILT)
+ -$(hide)$(PRIVATE_OBJCOPY) -O binary --only-keep=.dram_region $(PRIVATE_ELF_FILE) $(PRIVATE_BIN_DRAM_NH)
+
+ @if [ -s '$(PRIVATE_BIN_DRAM_NH)' ]; then \
+ echo "$(TINYSYS_MEDMCU): enable cache support for $(PRIVATE_PROCESSOR)"; \
+ $(MKIMAGE) $(PRIVATE_BIN_DRAM_NH) $(PRIVATE_DRAM_IMG_HDR_CFG) > $(PRIVATE_BIN_DRAM_BUILT); \
+ fi;
+endif
+ @if [ -s '$(PRIVATE_BIN_MEDHW_NH)/$(MEDHW_GC0_PM)' ]; then \
+ echo "$(TINYSYS_MEDMCU): $(MEDHW_GC0_PM) binary found"; \
+ $(MKIMAGE) $(PRIVATE_BIN_MEDHW_NH)/$(MEDHW_GC0_PM) $(PRIVATE_MEDHW_GC0_PM_IMG_HDR_CFG) > $(PRIVATE_BIN_MEDHW_GC0_PM_BUILT); \
+ $(MKIMAGE) $(PRIVATE_BIN_MEDHW_NH)/$(MEDHW_GC0_DM) $(PRIVATE_MEDHW_GC0_DM_IMG_HDR_CFG) > $(PRIVATE_BIN_MEDHW_GC0_DM_BUILT); \
+ cat $(PRIVATE_BIN_MEDHW_GC0_PM_BUILT) $(PRIVATE_BIN_MEDHW_GC0_DM_BUILT) > $($(PROCESSOR)_MEDHW.BIN_BUILT); \
+ fi;
+ @if [ -s '$(PRIVATE_BIN_MEDHW_NH)/$(MEDHW_GC1_PM)' ]; then \
+ echo "$(TINYSYS_MEDMCU): $(MEDHW_GC1_PM) binary found"; \
+ $(MKIMAGE) $(PRIVATE_BIN_MEDHW_NH)/$(MEDHW_GC1_PM) $(PRIVATE_MEDHW_GC1_PM_IMG_HDR_CFG) > $(PRIVATE_BIN_MEDHW_GC1_PM_BUILT); \
+ $(MKIMAGE) $(PRIVATE_BIN_MEDHW_NH)/$(MEDHW_GC1_DM) $(PRIVATE_MEDHW_GC1_DM_IMG_HDR_CFG) > $(PRIVATE_BIN_MEDHW_GC1_DM_BUILT); \
+ cat $(PRIVATE_BIN_MEDHW_GC1_PM_BUILT) $(PRIVATE_BIN_MEDHW_GC1_DM_BUILT) >> $($(PROCESSOR)_MEDHW.BIN_BUILT); \
+ fi;
+ @if [ -s '$(PRIVATE_BIN_MEDHW_NH)/$(MEDHW_GC2_PM)' ]; then \
+ echo "$(TINYSYS_MEDMCU): $(MEDHW_GC2_PM) binary found"; \
+ $(MKIMAGE) $(PRIVATE_BIN_MEDHW_NH)/$(MEDHW_GC2_PM) $(PRIVATE_MEDHW_GC2_PM_IMG_HDR_CFG) > $(PRIVATE_BIN_MEDHW_GC2_PM_BUILT); \
+ $(MKIMAGE) $(PRIVATE_BIN_MEDHW_NH)/$(MEDHW_GC2_DM) $(PRIVATE_MEDHW_GC2_DM_IMG_HDR_CFG) > $(PRIVATE_BIN_MEDHW_GC2_DM_BUILT); \
+ cat $(PRIVATE_BIN_MEDHW_GC2_PM_BUILT) $(PRIVATE_BIN_MEDHW_GC2_DM_BUILT) >> $($(PROCESSOR)_MEDHW.BIN_BUILT); \
+ fi;
+ $(hide)$(MKIMAGE) $(PRIVATE_BIN_NH) $(PRIVATE_IMG_HDR_CFG) > $@
+
+
+ifeq (yes,$(CFG_HEAP_ON_L1TCM))
+.PHONY: $($(PROCESSOR)_L1TCM.BIN_BUILT)
+else
+.PHONY: $($(PROCESSOR)_DRAM.BIN_BUILT)
+endif
+
+ifeq (1,$(V))
+ $(hide)$(SIZE) $(PRIVATE_ELF_FILE)
+ $(hide)$(OBJSIZE) $(PRIVATE_BUILT_DIR)/$(SCP_RTOS_SRC_DIR)
+ $(hide)$(OBJSIZE) $(PRIVATE_BUILT_DIR)/$(PRIVATE_PLATFORM_DIR)
+ $(hide)$(OBJSIZE) $(PRIVATE_BUILT_DIR)/$(PRIVATE_PROJECT_DIR)
+endif
+
+MY_LIBFLAGS_SEARCH_PATH := $(patsubst -L%,%,$(filter -L%,$(LIBFLAGS)))
+MY_LIBFLAGS_SEARCH_NAME := $(patsubst -l%,lib%.a,$(filter -l%,$(LIBFLAGS)))
+MY_LIBFLAGS_SEARCH_FILE := $(wildcard $(foreach p,$(MY_LIBFLAGS_SEARCH_PATH),$(foreach n,$(MY_LIBFLAGS_SEARCH_NAME),$(p)/$(n))))
+$($(PROCESSOR).ELF_FILE): PRIVATE_CC := $(CC)
+$($(PROCESSOR).ELF_FILE): PRIVATE_LLD := $(LLD)
+$($(PROCESSOR).ELF_FILE): PRIVATE_PLATFORM := $(PLATFORM)
+$($(PROCESSOR).ELF_FILE): PRIVATE_MAP_FILE := $($(PROCESSOR).MAP_FILE)
+$($(PROCESSOR).ELF_FILE): PRIVATE_ASM_FILE := $($(PROCESSOR).ASM_FILE)
+$($(PROCESSOR).ELF_FILE): PRIVATE_LDFLAGS := $(LDFLAGS)
+$($(PROCESSOR).ELF_FILE): PRIVATE_LIBS := $(LIBFLAGS)
+$($(PROCESSOR).ELF_FILE): PRIVATE_OBJDUMP := $(OBJDUMP)
+$($(PROCESSOR).ELF_FILE): PRIVATE_RV33_VAR := $(RV33_VAR)
+$($(PROCESSOR).ELF_FILE): PRIVATE_OBJS := $(OBJS)
+$($(PROCESSOR).ELF_FILE): PRIVATE_LINK_LD := $($(PROCESSOR).LINK_LD)
+$($(PROCESSOR).ELF_FILE): $(OBJS)
+$($(PROCESSOR).ELF_FILE): $(MY_LIBFLAGS_SEARCH_FILE)
+$($(PROCESSOR).ELF_FILE): $($(PROCESSOR).LINK_LD) $(DEPS)
+ @echo '$(TINYSYS_MEDMCU): ELF $@'
+ @mkdir -p $(dir $@)
+ $(hide)$(PRIVATE_LLD) -Map=$(PRIVATE_MAP_FILE) -o $@ -T $(PRIVATE_LINK_LD) $(PRIVATE_LDFLAGS) $(PRIVATE_OBJS) $(PRIVATE_LIBS)
+ $(hide)$(PRIVATE_OBJDUMP) -mcpu=$(PRIVATE_RV33_VAR) -S $@ > $(PRIVATE_ASM_FILE)
+ #$(hide)$(GOBJDUMP) -S $@ > $($(PROCESSOR).ASM2_FILE)
+ #$(hide)$(READELF) -a $@ > $($(PROCESSOR).RELF_FILE)
+ @echo '$(TINYSYS_MEDMCU): Memory Check'
+ $(hide)PLATFORM=$(PRIVATE_PLATFORM) $(MCHECK) -d SCP $(SCP_SETTING_INI) $(PRIVATE_MAP_FILE)
+
+$($(PROCESSOR).LINK_LD): PRIVATE_CC := $(CC)
+$($(PROCESSOR).LINK_LD): PRIVATE_CFLAGS := $(CFLAGS)
+$($(PROCESSOR).LINK_LD): PRIVATE_INCLUDES := $(INCLUDES)
+$($(PROCESSOR).LINK_LD): $(PLATFORM_DIR)/link.ld.c configheader
+ @echo '$(TINYSYS_MEDMCU): CC $@'
+ @mkdir -p $(dir $@)
+ $(hide)$(PRIVATE_CC) -Xpreprocessor $(PRIVATE_CFLAGS) $(PRIVATE_INCLUDES) -E -P $< -o $@_tmp
+ $(hide)$(GEN_LINK_LD) -i $@_tmp -o $@
+
+$($(PROCESSOR).IMG_HDR_CFG): $(DEPS)
+ $(call gen-image-header,$(TINYSYS_MEDMCU))
+
+ifeq (yes,$(CFG_HEAP_ON_L1TCM))
+$($(PROCESSOR)_L1TCM.IMG_HDR_CFG): $(DEPS)
+ $(call gen-image-header,$(TINYSYS_MEDMCU))
+else
+$($(PROCESSOR)_DRAM.IMG_HDR_CFG): $(DEPS)
+ $(call gen-image-header,$(TINYSYS_MEDMCU))
+endif
+
+$($(PROCESSOR)_MEDHW_GC0_PM.IMG_HDR_CFG): $(DEPS)
+ $(call gen-image-header,$(TINYSYS_MEDMCU))
+
+$($(PROCESSOR)_MEDHW_GC1_PM.IMG_HDR_CFG): $(DEPS)
+ $(call gen-image-header,$(TINYSYS_MEDMCU))
+
+$($(PROCESSOR)_MEDHW_GC2_PM.IMG_HDR_CFG): $(DEPS)
+ $(call gen-image-header,$(TINYSYS_MEDMCU))
+
+$($(PROCESSOR)_MEDHW_GC0_DM.IMG_HDR_CFG): $(DEPS)
+ $(call gen-image-header,$(TINYSYS_MEDMCU))
+
+$($(PROCESSOR)_MEDHW_GC1_DM.IMG_HDR_CFG): $(DEPS)
+ $(call gen-image-header,$(TINYSYS_MEDMCU))
+
+$($(PROCESSOR)_MEDHW_GC2_DM.IMG_HDR_CFG): $(DEPS)
+ $(call gen-image-header,$(TINYSYS_MEDMCU))
+
+###########################################################
+## ESL object definition
+###########################################################
+ESL_AP_C_FILES := $(patsubst ./%,%,$(ESL_AP_C_FILES))
+ESL_AP_S_FILES := $(patsubst ./%,%,$(ESL_AP_S_FILES))
+ESL_MCU_C_FILES := $(patsubst ./%,%,$(ESL_MCU_C_FILES))
+ESL_MCU_S_FILES := $(patsubst ./%,%,$(ESL_MCU_S_FILES))
+ESL_AP_C_OBJS := $(sort $(ESL_AP_C_FILES:%.c=$(SCP_BUILT_DIR)/%.o))
+ESL_MCU_C_OBJS := $(sort $(ESL_MCU_C_FILES:%.c=$(SCP_BUILT_DIR)/%.o))
+ESL_AP_S_OBJS := $(sort $(ESL_AP_S_FILES:%.S=$(SCP_BUILT_DIR)/%.o))
+ESL_MCU_S_OBJS := $(sort $(ESL_MCU_S_FILES:%.S=$(SCP_BUILT_DIR)/%.o))
+
+ESL_AP_OBJS := $(sort $(ESL_AP_C_OBJS) $(ESL_AP_S_OBJS))
+ESL_MCU_OBJS := $(sort $(ESL_MCU_C_OBJS) $(ESL_MCU_S_OBJS))
+ESL_C_OBJS := $(sort $(ESL_AP_C_OBJS) $(ESL_MCU_C_OBJS))
+ESL_S_OBJS := $(sort $(ESL_AP_S_OBJS) $(ESL_MCU_S_OBJS))
+$(ESL_C_OBJS) $(ESL_S_OBJS): $($(PROCESSOR).TINYSYS_CONFIG_H)
+
+###########################################################
+## ESL build targets
+###########################################################
+$(ESL_C_OBJS) $(ESL_S_OBJS): $(DEPS)
+
+$(ESL_C_OBJS): PRIVATE_BUILD_TAG := $(TINYSYS_MEDMCU)
+$(ESL_C_OBJS): PRIVATE_CC := $(CC)
+$(ESL_C_OBJS): PRIVATE_CFLAGS := $(CFLAGS)
+$(ESL_C_OBJS): PRIVATE_INCLUDES := $(INCLUDES)
+$(ESL_C_OBJS): $(SCP_BUILT_DIR)/%.o: %.c
+ $(compile-c-or-s-to-o)
+
+$(ESL_S_OBJS): PRIVATE_BUILD_TAG := $(TINYSYS_MEDMCU)
+$(ESL_S_OBJS): PRIVATE_CC := $(CC)
+$(ESL_S_OBJS): PRIVATE_CFLAGS := $(CFLAGS)
+$(ESL_S_OBJS): PRIVATE_INCLUDES := $(INCLUDES)
+$(ESL_S_OBJS): $(SCP_BUILT_DIR)/%.o: %.S
+ $(compile-c-or-s-to-o)
+
+# ESL LDs
+$($(PROCESSOR).ESL_AP_LINK_LD): PRIVATE_CC := $(CC)
+$($(PROCESSOR).ESL_AP_LINK_LD): PRIVATE_CFLAGS := $(CFLAGS) -Xpreprocessor -DPLAT_DUAL -DPLAT_DUAL_AP -E -P
+$($(PROCESSOR).ESL_AP_LINK_LD): PRIVATE_INCLUDES := $(INCLUDES)
+$($(PROCESSOR).ESL_AP_LINK_LD): $(PLATFORM_DIR)/link.ld.c configheader
+ @echo '$(TINYSYS_MEDMCU): CC $@'
+ @mkdir -p $(dir $@)
+ $(hide)$(PRIVATE_CC) $(PRIVATE_CFLAGS) $(PRIVATE_INCLUDES) -E -P $< -o $@
+
+$($(PROCESSOR).ESL_MCU0_LINK_LD): PRIVATE_CC := $(CC)
+$($(PROCESSOR).ESL_MCU0_LINK_LD): PRIVATE_CFLAGS := $(CFLAGS) -Xpreprocessor -DPLAT_DUAL -DPLAT_DUAL_MCU0 -E -P
+$($(PROCESSOR).ESL_MCU0_LINK_LD): PRIVATE_INCLUDES := $(INCLUDES)
+$($(PROCESSOR).ESL_MCU0_LINK_LD): $(PLATFORM_DIR)/link.ld.c configheader
+ @echo '$(TINYSYS_MEDMCU): CC $@'
+ @mkdir -p $(dir $@)
+ $(hide)$(PRIVATE_CC) $(PRIVATE_CFLAGS) $(PRIVATE_INCLUDES) -E -P $< -o $@
+
+$($(PROCESSOR).ESL_MCU1_LINK_LD): PRIVATE_CC := $(CC)
+$($(PROCESSOR).ESL_MCU1_LINK_LD): PRIVATE_CFLAGS := $(CFLAGS) -Xpreprocessor -DPLAT_DUAL -DPLAT_DUAL_MCU1 -E -P
+$($(PROCESSOR).ESL_MCU1_LINK_LD): PRIVATE_INCLUDES := $(INCLUDES)
+$($(PROCESSOR).ESL_MCU1_LINK_LD): $(PLATFORM_DIR)/link.ld.c configheader
+ @echo '$(TINYSYS_MEDMCU): CC $@'
+ @mkdir -p $(dir $@)
+ $(hide)$(PRIVATE_CC) $(PRIVATE_CFLAGS) $(PRIVATE_INCLUDES) -E -P $< -o $@
+
+# ESL ELFs
+$($(PROCESSOR).ESL_AP_ELF): PRIVATE_LLD := $(LLD)
+$($(PROCESSOR).ESL_AP_ELF): PRIVATE_LINK_LD := $($(PROCESSOR).ESL_AP_LINK_LD)
+$($(PROCESSOR).ESL_AP_ELF): PRIVATE_MAP_FILE := $($(PROCESSOR).ESL_AP_MAP)
+$($(PROCESSOR).ESL_AP_ELF): PRIVATE_LDFLAGS := $(LDFLAGS)
+$($(PROCESSOR).ESL_AP_ELF): PRIVATE_LIBS := $(LIBFLAGS)
+$($(PROCESSOR).ESL_AP_ELF): PRIVATE_OBJS := $(OBJS)
+$($(PROCESSOR).ESL_AP_ELF): PRIVATE_AP_OBJS := $(ESL_AP_OBJS)
+$($(PROCESSOR).ESL_AP_ELF): $($(PROCESSOR).ESL_AP_LINK_LD) $(OBJS) $(ESL_AP_OBJS)
+ $(hide)$(PRIVATE_LLD) -Map=$(PRIVATE_MAP_FILE) -o $@ -T $(PRIVATE_LINK_LD) $(PRIVATE_LDFLAGS) $(PRIVATE_OBJS) $(PRIVATE_AP_OBJS) $(PRIVATE_LIBS)
+
+$($(PROCESSOR).ESL_MCU0_ELF): PRIVATE_LLD := $(LLD)
+$($(PROCESSOR).ESL_MCU0_ELF): PRIVATE_LINK_LD := $($(PROCESSOR).ESL_MCU0_LINK_LD)
+$($(PROCESSOR).ESL_MCU0_ELF): PRIVATE_MAP_FILE := $($(PROCESSOR).ESL_MCU0_MAP)
+$($(PROCESSOR).ESL_MCU0_ELF): PRIVATE_LDFLAGS := $(LDFLAGS)
+$($(PROCESSOR).ESL_MCU0_ELF): PRIVATE_LIBS := $(LIBFLAGS)
+$($(PROCESSOR).ESL_MCU0_ELF): PRIVATE_OBJS := $(OBJS)
+$($(PROCESSOR).ESL_MCU0_ELF): PRIVATE_MCU_OBJS := $(ESL_MCU_OBJS)
+$($(PROCESSOR).ESL_MCU0_ELF): $($(PROCESSOR).ESL_MCU0_LINK_LD) $(OBJS) $(ESL_MCU_OBJS)
+ $(hide)$(PRIVATE_LLD) -Map=$(PRIVATE_MAP_FILE) -o $@ -T $(PRIVATE_LINK_LD) $(PRIVATE_LDFLAGS) $(PRIVATE_OBJS) $(PRIVATE_MCU_OBJS) $(PRIVATE_LIBS)
+
+$($(PROCESSOR).ESL_MCU1_ELF): PRIVATE_LLD := $(LLD)
+$($(PROCESSOR).ESL_MCU1_ELF): PRIVATE_LINK_LD := $($(PROCESSOR).ESL_MCU1_LINK_LD)
+$($(PROCESSOR).ESL_MCU1_ELF): PRIVATE_MAP_FILE := $($(PROCESSOR).ESL_MCU1_MAP)
+$($(PROCESSOR).ESL_MCU1_ELF): PRIVATE_LDFLAGS := $(LDFLAGS)
+$($(PROCESSOR).ESL_MCU1_ELF): PRIVATE_LIBS := $(LIBFLAGS)
+$($(PROCESSOR).ESL_MCU1_ELF): PRIVATE_OBJS := $(OBJS)
+$($(PROCESSOR).ESL_MCU1_ELF): PRIVATE_MCU_OBJS := $(ESL_MCU_OBJS)
+$($(PROCESSOR).ESL_MCU1_ELF): $($(PROCESSOR).ESL_MCU1_LINK_LD) $(OBJS) $(ESL_MCU_OBJS)
+ $(hide)$(PRIVATE_LLD) -Map=$(PRIVATE_MAP_FILE) -o $@ -T $(PRIVATE_LINK_LD) $(PRIVATE_LDFLAGS) $(PRIVATE_OBJS) $(PRIVATE_MCU_OBJS) $(PRIVATE_LIBS)
+
+# ESL BINs
+$($(PROCESSOR).ESL_AP_BIN): PRIVATE_OBJDUMP := $(OBJDUMP)
+$($(PROCESSOR).ESL_AP_BIN): PRIVATE_OBJCOPY := $(OBJCOPY)
+$($(PROCESSOR).ESL_AP_BIN): PRIVATE_ELF_FILE := $($(PROCESSOR).ESL_AP_ELF)
+$($(PROCESSOR).ESL_AP_BIN): PRIVATE_ASM_FILE := $($(PROCESSOR).ESL_AP_ASM)
+$($(PROCESSOR).ESL_AP_BIN): PRIVATE_RV33_VAR := $(RV33_VAR)
+$($(PROCESSOR).ESL_AP_BIN): $($(PROCESSOR).ESL_AP_ELF)
+ @echo '$(TINYSYS_MEDMCU): ASM $(PRIVATE_ASM_FILE)'
+ $(hide)$(PRIVATE_OBJDUMP) -mcpu=$(PRIVATE_RV33_VAR) -S $< > $(PRIVATE_ASM_FILE)
+ @echo '$(TINYSYS_MEDMCU): BIN $@'
+ $(hide)$(PRIVATE_OBJCOPY) -O binary $(PRIVATE_ELF_FILE) $@
+
+$($(PROCESSOR).ESL_MCU0_BIN): PRIVATE_OBJDUMP := $(OBJDUMP)
+$($(PROCESSOR).ESL_MCU0_BIN): PRIVATE_OBJCOPY := $(OBJCOPY)
+$($(PROCESSOR).ESL_MCU0_BIN): PRIVATE_ELF_FILE := $($(PROCESSOR).ESL_MCU0_ELF)
+$($(PROCESSOR).ESL_MCU0_BIN): PRIVATE_ASM_FILE := $($(PROCESSOR).ESL_MCU0_ASM)
+$($(PROCESSOR).ESL_MCU0_BIN): PRIVATE_RV33_VAR := $(RV33_VAR)
+$($(PROCESSOR).ESL_MCU0_BIN): $($(PROCESSOR).ESL_MCU0_ELF)
+ $(hide)$(PRIVATE_OBJDUMP) -mcpu=$(PRIVATE_RV33_VAR) -S $< > $(PRIVATE_ASM_FILE)
+ @echo '$(TINYSYS_MEDMCU): BIN $@'
+ $(hide)$(PRIVATE_OBJCOPY) -O binary $(PRIVATE_ELF_FILE) $@
+
+$($(PROCESSOR).ESL_MCU1_BIN): PRIVATE_OBJDUMP := $(OBJDUMP)
+$($(PROCESSOR).ESL_MCU1_BIN): PRIVATE_OBJCOPY := $(OBJCOPY)
+$($(PROCESSOR).ESL_MCU1_BIN): PRIVATE_ELF_FILE := $($(PROCESSOR).ESL_MCU1_ELF)
+$($(PROCESSOR).ESL_MCU1_BIN): PRIVATE_ASM_FILE := $($(PROCESSOR).ESL_MCU1_ASM)
+$($(PROCESSOR).ESL_MCU1_BIN): PRIVATE_RV33_VAR := $(RV33_VAR)
+$($(PROCESSOR).ESL_MCU1_BIN): $($(PROCESSOR).ESL_MCU1_ELF)
+ $(hide)$(PRIVATE_OBJDUMP) -mcpu=$(PRIVATE_RV33_VAR) -S $< > $(PRIVATE_ASM_FILE)
+ @echo '$(TINYSYS_MEDMCU): BIN $@'
+ $(hide)$(PRIVATE_OBJCOPY) -O binary $(PRIVATE_ELF_FILE) $@
+
+-include $(OBJS:.o=.d)
+-include $($(sort $(ESL_C_OBJS) $(ESL_S_OBJS)):.o=.d)
diff --git a/src/tinysys/medmcu/build/definitions.mk b/src/tinysys/medmcu/build/definitions.mk
new file mode 100644
index 0000000..d7a1be6
--- /dev/null
+++ b/src/tinysys/medmcu/build/definitions.mk
@@ -0,0 +1,24 @@
+###########################################################
+## Sort required Tiny System intermediate binaries and
+## print the result.
+## For each processor, loader must precede tinysys binary.
+###########################################################
+
+# $(1): the list of unordered binary file paths
+# $(2): prefix of processors to be filtered
+define sort_scp_binaries
+$(eval _arg := $(strip $(1))) \
+$(if $(_arg),, \
+ $(error $(TINYSYS_MEDMCU): sort_tinysys_binaries: argument missing)) \
+$(eval SORTED_TINYSYS_DEPS :=) \
+$(foreach p,$(filter $(2)_%,$(PROCESSORS)), \
+ $(eval m := $(filter %/$(TINYSYS_MEDMCU)-$(p).bin,$(_arg))) \
+ $(if $(m), \
+ $(eval SORTED_TINYSYS_DEPS := $(SORTED_TINYSYS_DEPS) $(m)), \
+ $(error $(TINYSYS_MEDMCU): Missing tinysys image for processor $(p)) \
+ ) \
+) \
+$(strip $(SORTED_TINYSYS_DEPS)) \
+$(eval m :=) \
+$(eval _arg :=)
+endef
diff --git a/src/tinysys/medmcu/build/main.mk b/src/tinysys/medmcu/build/main.mk
new file mode 100644
index 0000000..d48b5a4
--- /dev/null
+++ b/src/tinysys/medmcu/build/main.mk
@@ -0,0 +1,41 @@
+###########################################################
+## Obtain processor and platform name by project name
+###########################################################
+my_project_paths := $(strip $(shell find $(SCP_PROJECT_DIR) -maxdepth 4 \
+ -type d -name $(PROJECT) -printf '%P\n'))
+ifeq ($(my_project_paths),)
+ $(error $(TINYSYS_MEDMCU): cannot find project $(PROJECT) in $(SCP_PROJECT_DIR))
+endif
+
+my_processor_and_platform_names :=
+$(foreach p,$(my_project_paths), \
+ $(eval my_processor_and_platform_names += \
+ $(call get_processor_and_platform,$(p))) \
+)
+$(foreach i,$(my_processor_and_platform_names), \
+ $(eval PROCESSORS += $(strip $(word 1,$(subst :, ,$(i))))) \
+ $(eval PLATFORM += $(strip $(word 2,$(subst :, ,$(i))))) \
+)
+
+PROCESSORS := $(sort $(PROCESSORS))
+PLATFORM := $(sort $(PLATFORM))
+ifneq (1,$(words $(PLATFORM)))
+ $(error $(TINYSYS_MEDMCU): $(PROJECT) defined in multiple platforms: $(PLATFORM))
+endif
+
+ifeq (1,$(V))
+ $(info $(TINYSYS_MEDMCU): PROCESSORS=$(PROCESSORS))
+ $(info $(TINYSYS_MEDMCU): PLATFORM=$(PLATFORM))
+endif
+
+###########################################################
+## Initialize environment and targets for each processor
+###########################################################
+$(foreach p,$(PROCESSORS), \
+ $(eval PROCESSOR := $(p)) \
+ $(eval include $(SCP_BUILD_DIR)/config.mk) \
+)
+
+my_project_path :=
+my_project :=
+my_processor_and_platform_names :=
diff --git a/src/tinysys/medmcu/drivers/RV33_A/include/encoding.h b/src/tinysys/medmcu/drivers/RV33_A/include/encoding.h
new file mode 100644
index 0000000..9e56186
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/RV33_A/include/encoding.h
@@ -0,0 +1,1906 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
+ * ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
+ * THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
+ * SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
+ * RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
+ * FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
+ * WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
+ * AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
+ * RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation
+ * ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
+ * subject to any receiver\'s applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef _ENCODING_H_
+#define _ENCODING_H_
+
+#define __track_irq
+#define __two_levels_exception
+
+#define configExtension_F
+//#define configExtension_ACC /* unmark if required */
+#define configExtension_UAM
+
+#define configExtension_FastCTX
+#define __branch_prediction
+
+#ifdef configExtension_F
+#define RNE (0x0 << 5) /* round to nearest, tie to even */
+#define RTZ (0x1 << 5) /* round toward zero */
+#define RDN (0x2 << 5) /* round down */
+#define RUP (0x3 << 5) /* round up */
+#define RMM (0x4 << 5) /* round to nearest, tie to max magnitude */
+#define __rounding_mode RNE
+#endif /* configExtension_F */
+
+#ifdef configExtension_F
+#define F_reg 32
+#define F_fcsr 1
+#define __kstack_ext_reg_F (0x1 << 31)
+#ifdef configExtension_FastCTX
+#define FF
+#endif /* configExtension_FastCTX */
+#else
+#define F_reg 0
+#define F_fcsr 0
+#define __kstack_ext_reg_F 0
+#endif /* configExtension_F */
+#define F_reg_ctx (F_reg + F_fcsr)
+
+#ifdef configExtension_ACC
+#define ACC_reg 4*3
+#define __kstack_ext_reg_ACC (0x1 << 30)
+#ifdef configExtension_FastCTX
+#define FACC
+#endif /* configExtension_FastCTX */
+#else
+#define ACC_reg 0
+#define __kstack_ext_reg_ACC 0
+#endif /* configExtension_ACC */
+#define ACC_reg_ctx ACC_reg
+
+#ifdef configExtension_UAM
+#define UAM_reg 4*3
+#define __kstack_ext_reg_UAM (0x1 << 29)
+#ifdef configExtension_FastCTX
+#define FUAM
+#endif /* configExtension_FastCTX */
+#else
+#define UAM_reg 0
+#define __kstack_ext_reg_UAM 0
+#endif /* configExtension_UAM */
+#define UAM_reg_ctx UAM_reg
+
+
+#ifdef configExtension_HWDLP
+ #define HWDLP_reg 2*3
+ #define HWDLP_lf 1
+ #define __kstack_ext_reg_HWDLP (0x1 << 25)
+ #ifdef configExtension_FastCTX
+ #define FHWDLP
+ #define __kstack_ext_reg_FHWDLP (0x1 << 24)
+ #else
+ #define __kstack_ext_reg_FHWDLP 0
+ #endif /* configExtension_FastCTX */
+#else
+ #define HWDLP_reg 0
+ #define HWDLP_lf 0
+ #define __kstack_ext_reg_HWDLP 0
+ #define __kstack_ext_reg_FHWDLP 0
+#endif /* configExtension_HWDLP */
+#define HWDLP_reg_ctx (HWDLP_reg + HWDLP_lf)
+
+
+#define X_reg 32
+#define X_reg_ctx (X_reg+1)
+
+#define __kstack_ext_reg_value (__kstack_ext_reg_F | __kstack_ext_reg_ACC \
+ | __kstack_ext_reg_UAM)
+
+#define MSTATUS_UIE 0x00000001
+#define MSTATUS_SIE 0x00000002
+#define MSTATUS_HIE 0x00000004
+#define MSTATUS_MIE 0x00000008
+#define MSTATUS_UPIE 0x00000010
+#define MSTATUS_SPIE 0x00000020
+#define MSTATUS_HPIE 0x00000040
+#define MSTATUS_MPIE 0x00000080
+#define MSTATUS_SPP 0x00000100
+#define MSTATUS_HPP 0x00000600
+#define MSTATUS_MPP 0x00001800
+#define MSTATUS_FS 0x00006000
+#define MSTATUS_FS_I 0x00002000
+#define MSTATUS_FS_C 0x00004000
+#define MSTATUS_FS_D 0x00006000
+#define MSTATUS_XS 0x00018000
+#define MSTATUS_XS_I 0x00008000
+#define MSTATUS_XS_C 0x00010000
+#define MSTATUS_XS_D 0x00018000
+#define MSTATUS_MPRV 0x00020000
+#define MSTATUS_PUM 0x00040000
+#define MSTATUS_MXR 0x00080000
+#define MSTATUS_ACS 0x01800000
+#define MSTATUS_ACS_I 0x00800000
+#define MSTATUS_ACS_C 0x01000000
+#define MSTATUS_ACS_D 0x01800000
+#define MSTATUS_UAS 0x06000000
+#define MSTATUS_UAS_I 0x02000000
+#define MSTATUS_UAS_C 0x04000000
+#define MSTATUS_UAS_D 0x06000000
+#define MSTATUS_VM 0x1F000000
+#define MSTATUS32_SD 0x80000000
+#define MSTATUS64_SD 0x8000000000000000
+
+#define SSTATUS_UIE 0x00000001
+#define SSTATUS_SIE 0x00000002
+#define SSTATUS_UPIE 0x00000010
+#define SSTATUS_SPIE 0x00000020
+#define SSTATUS_SPP 0x00000100
+#define SSTATUS_FS 0x00006000
+#define SSTATUS_XS 0x00018000
+#define SSTATUS_PUM 0x00040000
+#define SSTATUS32_SD 0x80000000
+#define SSTATUS64_SD 0x8000000000000000
+
+#define DCSR_XDEBUGVER (3U<<30)
+#define DCSR_NDRESET (1<<29)
+#define DCSR_FULLRESET (1<<28)
+#define DCSR_EBREAKM (1<<15)
+#define DCSR_EBREAKH (1<<14)
+#define DCSR_EBREAKS (1<<13)
+#define DCSR_EBREAKU (1<<12)
+#define DCSR_STOPCYCLE (1<<10)
+#define DCSR_STOPTIME (1<<9)
+#define DCSR_CAUSE (7<<6)
+#define DCSR_DEBUGINT (1<<5)
+#define DCSR_HALT (1<<3)
+#define DCSR_STEP (1<<2)
+#define DCSR_PRV (3<<0)
+
+#define DCSR_CAUSE_NONE 0
+#define DCSR_CAUSE_SWBP 1
+#define DCSR_CAUSE_HWBP 2
+#define DCSR_CAUSE_DEBUGINT 3
+#define DCSR_CAUSE_STEP 4
+#define DCSR_CAUSE_HALT 5
+
+#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
+#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
+
+#define MCONTROL_SELECT (1<<19)
+#define MCONTROL_TIMING (1<<18)
+#define MCONTROL_ACTION (0x3f<<12)
+#define MCONTROL_CHAIN (1<<11)
+#define MCONTROL_MATCH (0xf<<7)
+#define MCONTROL_M (1<<6)
+#define MCONTROL_H (1<<5)
+#define MCONTROL_S (1<<4)
+#define MCONTROL_U (1<<3)
+#define MCONTROL_EXECUTE (1<<2)
+#define MCONTROL_STORE (1<<1)
+#define MCONTROL_LOAD (1<<0)
+
+#define MCONTROL_TYPE_NONE 0
+#define MCONTROL_TYPE_MATCH 2
+
+#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
+#define MCONTROL_ACTION_DEBUG_MODE 1
+#define MCONTROL_ACTION_TRACE_START 2
+#define MCONTROL_ACTION_TRACE_STOP 3
+#define MCONTROL_ACTION_TRACE_EMIT 4
+
+#define MCONTROL_MATCH_EQUAL 0
+#define MCONTROL_MATCH_NAPOT 1
+#define MCONTROL_MATCH_GE 2
+#define MCONTROL_MATCH_LT 3
+#define MCONTROL_MATCH_MASK_LOW 4
+#define MCONTROL_MATCH_MASK_HIGH 5
+
+#define MIP_SSIP (1 << IRQ_S_SOFT)
+#define MIP_HSIP (1 << IRQ_H_SOFT)
+#define MIP_MSIP (1 << IRQ_M_SOFT)
+#define MIP_STIP (1 << IRQ_S_TIMER)
+#define MIP_HTIP (1 << IRQ_H_TIMER)
+#define MIP_MTIP (1 << IRQ_M_TIMER)
+#define MIP_SEIP (1 << IRQ_S_EXT)
+#define MIP_HEIP (1 << IRQ_H_EXT)
+#define MIP_MEIP (1 << IRQ_M_EXT)
+#define MIP_LTIP (1 << IRQ_L_TIMER)
+#define MIP_AXI (1 << IRQ_AXI)
+#define MIP_LINT_0 (1 << IRQ_LINT_0)
+#define MIP_LINT_1 (1 << IRQ_LINT_1)
+#define MIP_LINT_2 (1 << IRQ_LINT_2)
+#define MIP_LINT_3 (1 << IRQ_LINT_3)
+#define MIP_LINT_4 (1 << IRQ_LINT_4)
+#define MIP_LINT_5 (1 << IRQ_LINT_5)
+#define MIP_LINT_6 (1 << IRQ_LINT_6)
+#define MIP_LINT_7 (1 << IRQ_LINT_7)
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define VM_MBARE 0
+#define VM_MBB 1
+#define VM_MBBID 2
+#define VM_SV32 8
+#define VM_SV39 9
+#define VM_SV48 10
+
+#define IRQ_S_SOFT 1
+#define IRQ_H_SOFT 2
+#define IRQ_M_SOFT 3
+#define IRQ_S_TIMER 5
+#define IRQ_H_TIMER 6
+#define IRQ_M_TIMER 7
+#define IRQ_S_EXT 9
+#define IRQ_H_EXT 10
+#define IRQ_M_EXT 11
+#define IRQ_COP 12
+#define IRQ_HOST 13
+#define IRQ_L_TIMER 16
+#define IRQ_AXI 17
+#define IRQ_LINT_0 24
+#define IRQ_LINT_1 25
+#define IRQ_LINT_2 26
+#define IRQ_LINT_3 27
+#define IRQ_LINT_4 28
+#define IRQ_LINT_5 29
+#define IRQ_LINT_6 30
+#define IRQ_LINT_7 31
+
+#define DEFAULT_RSTVEC 0x00001000
+#define DEFAULT_NMIVEC 0x00001004
+#define DEFAULT_MTVEC 0x00001010
+#define CONFIG_STRING_ADDR 0x0000100C
+#define EXT_IO_BASE 0x40000000
+#define DRAM_BASE 0x80000000
+
+/* page table entry (PTE) fields */
+#define PTE_V 0x001 /* Valid */
+#define PTE_R 0x002 /* Read */
+#define PTE_W 0x004 /* Write */
+#define PTE_X 0x008 /* Execute */
+#define PTE_U 0x010 /* User */
+#define PTE_G 0x020 /* Global */
+#define PTE_A 0x040 /* Accessed */
+#define PTE_D 0x080 /* Dirty */
+#define PTE_SOFT 0x300 /* Reserved for Software */
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#ifdef __riscv
+
+#ifdef __riscv64
+#define MSTATUS_SD MSTATUS64_SD
+#define SSTATUS_SD SSTATUS64_SD
+#define RISCV_PGLEVEL_BITS 9
+#else
+#define MSTATUS_SD MSTATUS32_SD
+#define SSTATUS_SD SSTATUS32_SD
+#define RISCV_PGLEVEL_BITS 10
+#endif
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#ifdef __GNUC__
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+ __tmp; })
+
+#define write_csr(reg, val) ({ \
+ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+ asm volatile ("csrwi " #reg ", %0" :: "i"(val)); \
+ else \
+ asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+
+#define mrv_read_csr(reg) ({ unsigned long __tmp; \
+ asm volatile("csrr %0, %1" : "=r"(__tmp) : "i"(reg)); \
+ __tmp; })
+
+#define mrv_write_csr(reg, val) ({ \
+ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+ asm volatile ("csrwi %0, %1" :: "i"(reg), "i"(val)); \
+ else \
+ asm volatile ("csrw %0, %1" :: "i"(reg), "r"(val)); })
+
+#define mrv_set_csr(reg, bit) ({ unsigned long __tmp; \
+ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+ asm volatile ("csrrsi %0, %1, %2" : "=r"(__tmp) : "i"(reg), "i"(bit)); \
+ else \
+ asm volatile ("csrrs %0, %1, %2" : "=r"(__tmp) : "i"(reg), "r"(bit)); \
+ __tmp; })
+
+#define mrv_clear_csr(reg, bit) ({ unsigned long __tmp; \
+ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+ asm volatile ("csrrci %0, %1, %2" : "=r"(__tmp) : "i"(reg), "i"(bit)); \
+ else \
+ asm volatile ("csrrc %0, %1, %2" : "=r"(__tmp) : "i"(reg), "r"(bit)); \
+ __tmp; })
+
+#define swap_csr(reg, val) ({ unsigned long __tmp; \
+ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+ asm volatile ("csrrwi %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
+ else \
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
+ __tmp; })
+
+#define set_csr(reg, bit) ({ unsigned long __tmp; \
+ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+ asm volatile ("csrrsi %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+ else \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+ __tmp; })
+
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+ asm volatile ("csrrci %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+ else \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+ __tmp; })
+
+#ifndef CFG_MRV_PATCH1
+#define mrv_icache_invalid_all() ({ unsigned long __tmp; \
+ asm volatile("li %0, 0x8\n" "cop %0": "=r"(__tmp)); \
+ })
+
+#define mrv_dcache_invalid_all() ({ unsigned long __tmp; \
+ asm volatile("li %0, 0x18\n" "cop %0": "=r"(__tmp)); \
+ })
+
+#define mrv_icache_invalid_addr(addr) ({ unsigned long __tmp; \
+ asm volatile("addi %0, %1, 0x9\n" "cop %0": "=r"(__tmp): "r"(addr)); \
+ })
+
+#define mrv_dcache_invalid_addr(addr) ({ unsigned long __tmp; \
+ asm volatile("addi %0, %1, 0x19\n" "cop %0": "=r"(__tmp): "r"(addr)); \
+ })
+
+#define mrv_dcache_flush_all() ({ unsigned long __tmp; \
+ asm volatile("li %0, 0x14\n" "cop %0": "=r"(__tmp)); \
+ })
+
+#define mrv_dcache_flush_addr(addr) ({ unsigned long __tmp; \
+ asm volatile("addi %0, %1, 0x15\n" "cop %0": "=r"(__tmp): "r"(addr)); \
+ })
+
+#define mrv_icache_barrier() ({ asm volatile("cop zero"); \
+ })
+
+#define mrv_dcache_barrier() ({ unsigned long __tmp; \
+ asm volatile("li %0, 0x10\n" "cop %0": "=r"(__tmp)); \
+ })
+
+#define mrv_icache_invalid_multi_addr(addr, length) ({ \
+ unsigned long __tmp = addr + 0x9; \
+ unsigned long __end_addr = __tmp + length; \
+ configASSERT(!((addr | length) & 0x1f)); \
+ asm volatile("1:" "cop %0\n" "addi %0, %0, 0x20\n" "bne %0, %1, 1b\n" \
+ : "+r"(__tmp): "r"(__end_addr)); \
+ })
+
+#define mrv_dcache_invalid_multi_addr(addr, length) ({ \
+ unsigned long __tmp = addr + 0x19; \
+ unsigned long __end_addr = __tmp + length; \
+ configASSERT(!((addr | length) & 0x1f)); \
+ asm volatile("1:" "cop %0\n" "addi %0, %0, 0x20\n" "bne %0, %1, 1b\n" \
+ : "+r"(__tmp): "r"(__end_addr)); \
+ })
+
+#define mrv_dcache_flush_multi_addr(addr, length) ({ \
+ unsigned long __tmp = addr + 0x15; \
+ unsigned long __end_addr = __tmp + length; \
+ configASSERT(!((addr | length) & 0x1f)); \
+ asm volatile("1:" "cop %0\n" "addi %0, %0, 0x20\n" "bne %0, %1, 1b\n" \
+ : "+r"(__tmp): "r"(__end_addr)); \
+ })
+#else
+#define mrv_icache_invalid_all() ({ unsigned long __tmp; \
+ unsigned long _flags; \
+ _flags = vPortSetInterruptMask(); \
+ asm volatile("li %0, 0x8\n" "cop %0": "=r"(__tmp)); \
+ vPortClearInterruptMask(_flags); \
+ })
+
+#define mrv_dcache_invalid_all() ({ unsigned long __tmp; \
+ unsigned long _flags; \
+ _flags = vPortSetInterruptMask(); \
+ asm volatile("li %0, 0x18\n" "cop %0": "=r"(__tmp)); \
+ vPortClearInterruptMask(_flags); \
+ })
+
+#define mrv_icache_invalid_addr(addr) ({ unsigned long __tmp; \
+ unsigned long _flags; \
+ _flags = vPortSetInterruptMask(); \
+ asm volatile("addi %0, %1, 0x9\n" "cop %0": "=r"(__tmp): "r"(addr)); \
+ vPortClearInterruptMask(_flags); \
+ })
+
+#define mrv_dcache_invalid_addr(addr) ({ unsigned long __tmp; \
+ unsigned long _flags; \
+ _flags = vPortSetInterruptMask(); \
+ asm volatile("addi %0, %1, 0x19\n" "cop %0": "=r"(__tmp): "r"(addr)); \
+ vPortClearInterruptMask(_flags); \
+ })
+
+#define mrv_dcache_flush_all() ({ unsigned long __tmp; \
+ unsigned long _flags; \
+ _flags = vPortSetInterruptMask(); \
+ asm volatile("li %0, 0x14\n" "cop %0": "=r"(__tmp)); \
+ vPortClearInterruptMask(_flags); \
+ })
+
+#define mrv_dcache_flush_addr(addr) ({ unsigned long __tmp; \
+ unsigned long _flags; \
+ _flags = vPortSetInterruptMask(); \
+ asm volatile("addi %0, %1, 0x15\n" "cop %0": "=r"(__tmp): "r"(addr)); \
+ vPortClearInterruptMask(_flags); \
+ })
+
+#define mrv_icache_barrier() ({ asm volatile("cop zero"); \
+ })
+
+#define mrv_dcache_barrier() ({ unsigned long __tmp; \
+ asm volatile("li %0, 0x10\n" "cop %0": "=r"(__tmp)); \
+ })
+
+#define mrv_icache_invalid_multi_addr(addr, length) ({ \
+ unsigned long __tmp = addr + 0x9; \
+ unsigned long __end_addr = __tmp + length; \
+ unsigned long _flags; \
+ configASSERT(!((addr | length) & 0x1f)); \
+ _flags = vPortSetInterruptMask(); \
+ asm volatile("1:" "cop %0\n" "addi %0, %0, 0x20\n" "bne %0, %1, 1b\n" \
+ : "+r"(__tmp): "r"(__end_addr)); \
+ vPortClearInterruptMask(_flags); \
+ })
+
+#define mrv_dcache_invalid_multi_addr(addr, length) ({ \
+ unsigned long __tmp = addr + 0x19; \
+ unsigned long __end_addr = __tmp + length; \
+ unsigned long _flags; \
+ configASSERT(!((addr | length) & 0x1f)); \
+ _flags = vPortSetInterruptMask(); \
+ asm volatile("1:" "cop %0\n" "addi %0, %0, 0x20\n" "bne %0, %1, 1b\n" \
+ : "+r"(__tmp): "r"(__end_addr)); \
+ vPortClearInterruptMask(_flags); \
+ })
+
+#define mrv_dcache_flush_multi_addr(addr, length) ({ \
+ unsigned long __tmp = addr + 0x15; \
+ unsigned long __end_addr = __tmp + length; \
+ unsigned long _flags; \
+ configASSERT(!((addr | length) & 0x1f)); \
+ _flags = vPortSetInterruptMask(); \
+ asm volatile("1:" "cop %0\n" "addi %0, %0, 0x20\n" "bne %0, %1, 1b\n" \
+ : "+r"(__tmp): "r"(__end_addr)); \
+ vPortClearInterruptMask(_flags); \
+ })
+#endif
+/* fence.i: flush all d-cache + invalid all icache */
+#define mrv_fence_i() \
+{ \
+ asm volatile("fence.i" ::: "memory"); \
+}
+
+/* fence: flush write buffer */
+#define mrv_fence_d() \
+{ \
+ asm volatile("fence" ::: "memory"); \
+}
+
+/* flush pipeline util barrier instr. finished */
+#define mrv_isb() ({ asm volatile("cop zero");})
+
+/* make sure memory r/w is finished */
+#define mrv_dmb() ({ unsigned long __tmp; \
+ asm volatile("li %0, 0x10\n" "cop %0": "=r"(__tmp)); \
+ })
+
+#define CACHE_LINE_SIZE 32
+#define CACHE_LINE_MASK (CACHE_LINE_SIZE - 1)
+#define CACHE_LINE_AND (~CACHE_LINE_MASK)
+#define cache_lower_addr(addr) (addr & CACHE_LINE_AND)
+#define cache_upper_size(addr, size) (((addr & CACHE_LINE_MASK) \
+ + size + CACHE_LINE_MASK) & CACHE_LINE_AND)
+
+#define L1TCM_REGION_RO __attribute__ ((section (".l1tcm_region_ro")))
+#define L1TCM_REGION_RW __attribute__ ((section (".l1tcm_region_rw")))
+
+#ifdef CFG_CACHE_SUPPORT
+#define SRAM_REGION_RO __attribute__ ((section (".sram_except_ro")))
+#define SRAM_REGION_RW __attribute__ ((section (".sram_except_rw")))
+#define SRAM_REGION_BSS __attribute__ ((section (".sram_except_bss")))
+#define SRAM_REGION_VARIABLE __attribute__ ((section (".sram_except_variable")))
+#define SRAM_REGION_FUNCTION __attribute__ ((section (".sram_except_func")))
+#define DRAM_REGION_RO __attribute__ ((section (".dram_region_ro")))
+#define DRAM_REGION_RW __attribute__ ((section (".dram_region_rw")))
+#define DRAM_REGION_BSS __attribute__ ((section (".dram_region_bss")))
+#define DRAM_REGION_VARIABLE __attribute__ ((section (".dram_region_variable")))
+#define DRAM_REGION_FUNCTION __attribute__ ((section (".dram_region_func")))
+
+#else
+#define SRAM_REGION_RO
+#define SRAM_REGION_RW
+#define SRAM_REGION_BSS
+#define SRAM_REGION_VARIABLE
+#define SRAM_REGION_FUNCTION
+#define DRAM_REGION_RO
+#define DRAM_REGION_RW
+#define DRAM_REGION_BSS
+#define DRAM_REGION_VARIABLE
+#define DRAM_REGION_FUNCTION
+#endif
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+#endif
+
+#endif
+
+#endif
+
+
+#define CLINT_BASE_ADDR 0x02000000
+#define CLINT_MSIP 0x0000
+#define CLINT_MSIP_size 0x4
+#define CLINT_MTIMECMP 0x4000
+#define CLINT_MTIMECMP_size 0x8
+#define CLINT_MTIME 0xBFF8
+#define CLINT_MTIME_size 0x8
+
+#define CSR_MTIME_BASE 0xbe0
+#define CSR_MTIME_MTMRCTR (CSR_MTIME_BASE + 0x000)
+#define CSR_MTIME_MTMRSTATUS (CSR_MTIME_BASE + 0x001)
+#define CSR_MTIME_MTMRCVR (CSR_MTIME_BASE + 0x002)
+#define CSR_MTIME_MTMRRVR (CSR_MTIME_BASE + 0x003)
+#define CSR_MTIME_MTMRDVR (CSR_MTIME_BASE + 0x004)
+
+/* centralized control enable */
+#define CSR_MCTREN (0x7c0)
+/* I$, D$, ITCM, DTCM, BTB, RAS, VIC, CG, mpu */
+#define CSR_MCTREN_ICACHE 0
+#define CSR_MCTREN_DCACHE 1
+#define CSR_MCTREN_ITCM 2
+#define CSR_MCTREN_DTCM 3
+#define CSR_MCTREN_BTB 4
+#define CSR_MCTREN_RAS 5
+#define CSR_MCTREN_VIC 6
+#define CSR_MCTREN_CG 7
+#define CSR_MCTREN_MPU 8
+
+/* VIC */
+#define CSR_VIC_MICAUSE (0x5c0)
+#define CSR_VIC_MIASWI (0x5c1)
+#define CSR_VIC_MIEMS (0x5c2)
+#define CSR_VIC_MIDBGMASK (0x5c3)
+#define CSR_VIC_MIDBGWAKEUP (0x5c4)
+#define CSR_VIC_MIPEND_G0 (0x5d0)
+#define CSR_VIC_MIPEND_G1 (0x5d1)
+#define CSR_VIC_MIPEND_G2 (0x5d2)
+#define CSR_VIC_MIPEND_G3 (0x5d3)
+#define CSR_VIC_MIPEND_G4 (0x5d4)
+#define CSR_VIC_MIPEND_G5 (0x5d5)
+#define CSR_VIC_MIPEND_G6 (0x5d6)
+#define CSR_VIC_MIPEND_G7 (0x5d7)
+#define CSR_VIC_MIMASK_G0 (0x5d8)
+#define CSR_VIC_MIMASK_G1 (0x5d9)
+#define CSR_VIC_MIMASK_G2 (0x5da)
+#define CSR_VIC_MIMASK_G3 (0x5db)
+#define CSR_VIC_MIMASK_G4 (0x5dc)
+#define CSR_VIC_MIMASK_G5 (0x5dd)
+#define CSR_VIC_MIMASK_G6 (0x5de)
+#define CSR_VIC_MIMASK_G7 (0x5df)
+#define CSR_VIC_MIWAKEUP_G0 (0x5e0)
+#define CSR_VIC_MIWAKEUP_G1 (0x5e1)
+#define CSR_VIC_MIWAKEUP_G2 (0x5e2)
+#define CSR_VIC_MIWAKEUP_G3 (0x5e3)
+#define CSR_VIC_MIWAKEUP_G4 (0x5e4)
+#define CSR_VIC_MIWAKEUP_G5 (0x5e5)
+#define CSR_VIC_MIWAKEUP_G6 (0x5e6)
+#define CSR_VIC_MIWAKEUP_G7 (0x5e7)
+#define CSR_VIC_MILSEL_G0 (0x5e8)
+#define CSR_VIC_MILSEL_G1 (0x5e9)
+#define CSR_VIC_MILSEL_G2 (0x5ea)
+#define CSR_VIC_MILSEL_G3 (0x5eb)
+#define CSR_VIC_MILSEL_G4 (0x5ec)
+#define CSR_VIC_MILSEL_G5 (0x5ed)
+#define CSR_VIC_MILSEL_G6 (0x5ee)
+#define CSR_VIC_MILSEL_G7 (0x5ef)
+#define CSR_VIC_MIEMASK_G0 (0x5f0)
+#define CSR_VIC_MIEMASK_G1 (0x5f1)
+#define CSR_VIC_MIEMASK_G2 (0x5f2)
+#define CSR_VIC_MIEMASK_G3 (0x5f3)
+#define CSR_VIC_MIEMASK_G4 (0x5f4)
+#define CSR_VIC_MIEMASK_G5 (0x5f5)
+#define CSR_VIC_MIEMASK_G6 (0x5f6)
+#define CSR_VIC_MIEMASK_G7 (0x5f7)
+
+#define CSR_MIMABTCAU (0x7c5)
+#define CSR_MIMABTADDR (0x7c6)
+
+/* MPU */
+#define CSR_MPU_ENTRY_EN (0x9c0)
+#define CSR_MPU_LITCM (0x9dc)
+#define CSR_MPU_LDTCM (0x9dd)
+#define CSR_MPU_HITCM (0x9de)
+#define CSR_MPU_HDTCM (0x9df)
+#define CSR_MPU_L00 (0x9e0)
+#define CSR_MPU_L01 (0x9e1)
+#define CSR_MPU_L02 (0x9e2)
+#define CSR_MPU_L03 (0x9e3)
+#define CSR_MPU_L04 (0x9e4)
+#define CSR_MPU_L05 (0x9e5)
+#define CSR_MPU_L06 (0x9e6)
+#define CSR_MPU_L07 (0x9e7)
+#define CSR_MPU_L08 (0x9e8)
+#define CSR_MPU_L09 (0x9e9)
+#define CSR_MPU_L10 (0x9ea)
+#define CSR_MPU_L11 (0x9eb)
+#define CSR_MPU_L12 (0x9ec)
+#define CSR_MPU_L13 (0x9ed)
+#define CSR_MPU_L14 (0x9ee)
+#define CSR_MPU_L15 (0x9ef)
+#define CSR_MPU_LXX_P 5
+#define CSR_MPU_LXX_R 6
+#define CSR_MPU_LXX_W 7
+#define CSR_MPU_LXX_C 8
+#define CSR_MPU_LXX_B 9
+#define CSR_MPU_H00 (0x9f0)
+#define CSR_MPU_H01 (0x9f1)
+#define CSR_MPU_H02 (0x9f2)
+#define CSR_MPU_H03 (0x9f3)
+#define CSR_MPU_H04 (0x9f4)
+#define CSR_MPU_H05 (0x9f5)
+#define CSR_MPU_H06 (0x9f6)
+#define CSR_MPU_H07 (0x9f7)
+#define CSR_MPU_H08 (0x9f8)
+#define CSR_MPU_H09 (0x9f9)
+#define CSR_MPU_H10 (0x9fa)
+#define CSR_MPU_H11 (0x9fb)
+#define CSR_MPU_H12 (0x9fc)
+#define CSR_MPU_H13 (0x9fd)
+#define CSR_MPU_H14 (0x9fe)
+#define CSR_MPU_H15 (0x9ff)
+
+/* PMU */
+#define CSR_PMU_MPMUCTR (0xbc0)
+#define CSR_PMU_MPMUCTR_C 0
+#define CSR_PMU_MPMUCTR_I 1
+#define CSR_PMU_MPMUCTR_H3 2
+#define CSR_PMU_MPMUCTR_H4 3
+#define CSR_PMU_MPMUCTR_H5 4
+#define CSR_PMU_MPMUCTR_H6 5
+#define CSR_PMU_MPMUCTR_H7 6
+
+#define CSR_PMU_MCYCLE (0xb00)
+#define CSR_PMU_MINSTRET (0xb02)
+#define CSR_PMU_MHPMCOUNTER3 (0xb03)
+#define CSR_PMU_MHPMCOUNTER4 (0xb04)
+#define CSR_PMU_MHPMCOUNTER5 (0xb05)
+#define CSR_PMU_MHPMCOUNTER6 (0xb06)
+#define CSR_PMU_MHPMCOUNTER7 (0xb07)
+
+#define CSR_PMU_MCYCLEH (0xb80)
+#define CSR_PMU_MINSTRETH (0xb82)
+#define CSR_PMU_MHPMCOUNTER3H (0xb83)
+#define CSR_PMU_MHPMCOUNTER4H (0xb84)
+#define CSR_PMU_MHPMCOUNTER5H (0xb85)
+#define CSR_PMU_MHPMCOUNTER6H (0xb86)
+#define CSR_PMU_MHPMCOUNTER7H (0xb87)
+
+#define CSR_PMU_MHPMEVENT3 (0x323)
+#define CSR_PMU_MHPMEVENT4 (0x324)
+#define CSR_PMU_MHPMEVENT5 (0x325)
+#define CSR_PMU_MHPMEVENT6 (0x326)
+#define CSR_PMU_MHPMEVENT7 (0x327)
+
+#define CSR_PMU_MPHSWEVENT (0xbc1)
+
+/* CACHE */
+#define CSR_CACHE_ICACHEMSK (0x9c1)
+#define CSR_CACHE_ICACHESTATUS (0x9c2)
+#define CSR_CACHE_ICACHEOP (0x9c3)
+#define CSR_CACHE_I_OP_SEL 4
+#define CSR_CACHE_I_OP_MB 0x0
+#define CSR_CACHE_I_OP_CA 0x4
+#define CSR_CACHE_I_OP_C 0x5
+#define CSR_CACHE_I_OP_IA 0x8
+#define CSR_CACHE_I_OP_I 0x9
+#define CSR_CACHE_I_OP_FA 0xc
+#define CSR_CACHE_I_OP_F 0xd
+#define CSR_CACHE_DCACHEMSK (0x9c4)
+#define CSR_CACHE_DCACHESTATUS (0x9c5)
+#define CSR_CACHE_DCACHEOP (0x9c6)
+#define CSR_CACHE_D_OP_SEL CSR_CACHE_I_OP_SEL
+#define CSR_CACHE_D_OP_MB CSR_CACHE_I_OP_MB
+#define CSR_CACHE_D_OP_CA CSR_CACHE_I_OP_CA
+#define CSR_CACHE_D_OP_C CSR_CACHE_I_OP_C
+#define CSR_CACHE_D_OP_IA CSR_CACHE_I_OP_IA
+#define CSR_CACHE_D_OP_I CSR_CACHE_I_OP_I
+#define CSR_CACHE_D_OP_FA CSR_CACHE_I_OP_FA
+#define CSR_CACHE_D_OP_F CSR_CACHE_I_OP_F
+
+/* Trace Buffer */
+#define CSR_TBUF_MTBUFCTR (0xbd0)
+#define CSR_TBUF_MTBUFCTR_EN 0
+#define CSR_TBUF_MTBUFCTR_M 4
+#define CSR_TBUF_MTBUFCLR (0xbd1)
+#define CSR_TBUF_MTBUFSTR (0xbd2)
+#define CSR_TBUF_MTBUFSTR_WP 4
+#define CSR_TBUF_MTBUFSTR_OF 16
+#define CSR_TBUF_MTBUFRCMD (0xbd3)
+#define CSR_TBUF_MTBUFRCMD_LOG 0
+#define CSR_TBUF_MTBUFRCMD_RP 4
+#define CSR_TBUF_MTBUFRCMD_R 16
+#define CSR_TBUF_MTBUFRDATA (0xbd4)
+
+/* misc */
+#define CSR_UFLAG (0xbff)
+
+#define CSR_TIMER (0xc01)
+#define CSR_TIMERH (0xc81)
+#define CSR_MNPC (0xfc1)
+#define CSR_MVERID0 (0xfc2)
+#define CSR_MVERID1 (0xfc3)
+#define CSR_MVERID2 (0xfc4)
+#define CSR_MDBGBP0 (0x7d0)
+#define CSR_MDBGBP1 (0x7d1)
+#define CSR_MDBGBP2 (0x7d2)
+#define CSR_MDBGBP3 (0x7d3)
+#define CSR_MDBGBPC (0x7d4)
+
+#define CSR_MDBGWPM0 (0x7d8)
+#define CSR_MDBGWPM1 (0x7d9)
+#define CSR_MDBGWPM2 (0x7da)
+#define CSR_MDBGWPM3 (0x7db)
+
+
+#endif
+/* Automatically generated by parse-opcodes */
+#ifndef RISCV_ENCODING_H
+#define RISCV_ENCODING_H
+#define MATCH_BEQ 0x63
+#define MASK_BEQ 0x707f
+#define MATCH_BNE 0x1063
+#define MASK_BNE 0x707f
+#define MATCH_BLT 0x4063
+#define MASK_BLT 0x707f
+#define MATCH_BGE 0x5063
+#define MASK_BGE 0x707f
+#define MATCH_BLTU 0x6063
+#define MASK_BLTU 0x707f
+#define MATCH_BGEU 0x7063
+#define MASK_BGEU 0x707f
+#define MATCH_JALR 0x67
+#define MASK_JALR 0x707f
+#define MATCH_JAL 0x6f
+#define MASK_JAL 0x7f
+#define MATCH_LUI 0x37
+#define MASK_LUI 0x7f
+#define MATCH_AUIPC 0x17
+#define MASK_AUIPC 0x7f
+#define MATCH_ADDI 0x13
+#define MASK_ADDI 0x707f
+#define MATCH_SLLI 0x1013
+#define MASK_SLLI 0xfc00707f
+#define MATCH_SLTI 0x2013
+#define MASK_SLTI 0x707f
+#define MATCH_SLTIU 0x3013
+#define MASK_SLTIU 0x707f
+#define MATCH_XORI 0x4013
+#define MASK_XORI 0x707f
+#define MATCH_SRLI 0x5013
+#define MASK_SRLI 0xfc00707f
+#define MATCH_SRAI 0x40005013
+#define MASK_SRAI 0xfc00707f
+#define MATCH_ORI 0x6013
+#define MASK_ORI 0x707f
+#define MATCH_ANDI 0x7013
+#define MASK_ANDI 0x707f
+#define MATCH_ADD 0x33
+#define MASK_ADD 0xfe00707f
+#define MATCH_SUB 0x40000033
+#define MASK_SUB 0xfe00707f
+#define MATCH_SLL 0x1033
+#define MASK_SLL 0xfe00707f
+#define MATCH_SLT 0x2033
+#define MASK_SLT 0xfe00707f
+#define MATCH_SLTU 0x3033
+#define MASK_SLTU 0xfe00707f
+#define MATCH_XOR 0x4033
+#define MASK_XOR 0xfe00707f
+#define MATCH_SRL 0x5033
+#define MASK_SRL 0xfe00707f
+#define MATCH_SRA 0x40005033
+#define MASK_SRA 0xfe00707f
+#define MATCH_OR 0x6033
+#define MASK_OR 0xfe00707f
+#define MATCH_AND 0x7033
+#define MASK_AND 0xfe00707f
+#define MATCH_ADDIW 0x1b
+#define MASK_ADDIW 0x707f
+#define MATCH_SLLIW 0x101b
+#define MASK_SLLIW 0xfe00707f
+#define MATCH_SRLIW 0x501b
+#define MASK_SRLIW 0xfe00707f
+#define MATCH_SRAIW 0x4000501b
+#define MASK_SRAIW 0xfe00707f
+#define MATCH_ADDW 0x3b
+#define MASK_ADDW 0xfe00707f
+#define MATCH_SUBW 0x4000003b
+#define MASK_SUBW 0xfe00707f
+#define MATCH_SLLW 0x103b
+#define MASK_SLLW 0xfe00707f
+#define MATCH_SRLW 0x503b
+#define MASK_SRLW 0xfe00707f
+#define MATCH_SRAW 0x4000503b
+#define MASK_SRAW 0xfe00707f
+#define MATCH_LB 0x3
+#define MASK_LB 0x707f
+#define MATCH_LH 0x1003
+#define MASK_LH 0x707f
+#define MATCH_LW 0x2003
+#define MASK_LW 0x707f
+#define MATCH_LD 0x3003
+#define MASK_LD 0x707f
+#define MATCH_LBU 0x4003
+#define MASK_LBU 0x707f
+#define MATCH_LHU 0x5003
+#define MASK_LHU 0x707f
+#define MATCH_LWU 0x6003
+#define MASK_LWU 0x707f
+#define MATCH_SB 0x23
+#define MASK_SB 0x707f
+#define MATCH_SH 0x1023
+#define MASK_SH 0x707f
+#define MATCH_SW 0x2023
+#define MASK_SW 0x707f
+#define MATCH_SD 0x3023
+#define MASK_SD 0x707f
+#define MATCH_FENCE 0xf
+#define MASK_FENCE 0x707f
+#define MATCH_FENCE_I 0x100f
+#define MASK_FENCE_I 0x707f
+#define MATCH_MUL 0x2000033
+#define MASK_MUL 0xfe00707f
+#define MATCH_MULH 0x2001033
+#define MASK_MULH 0xfe00707f
+#define MATCH_MULHSU 0x2002033
+#define MASK_MULHSU 0xfe00707f
+#define MATCH_MULHU 0x2003033
+#define MASK_MULHU 0xfe00707f
+#define MATCH_DIV 0x2004033
+#define MASK_DIV 0xfe00707f
+#define MATCH_DIVU 0x2005033
+#define MASK_DIVU 0xfe00707f
+#define MATCH_REM 0x2006033
+#define MASK_REM 0xfe00707f
+#define MATCH_REMU 0x2007033
+#define MASK_REMU 0xfe00707f
+#define MATCH_MULW 0x200003b
+#define MASK_MULW 0xfe00707f
+#define MATCH_DIVW 0x200403b
+#define MASK_DIVW 0xfe00707f
+#define MATCH_DIVUW 0x200503b
+#define MASK_DIVUW 0xfe00707f
+#define MATCH_REMW 0x200603b
+#define MASK_REMW 0xfe00707f
+#define MATCH_REMUW 0x200703b
+#define MASK_REMUW 0xfe00707f
+#define MATCH_AMOADD_W 0x202f
+#define MASK_AMOADD_W 0xf800707f
+#define MATCH_AMOXOR_W 0x2000202f
+#define MASK_AMOXOR_W 0xf800707f
+#define MATCH_AMOOR_W 0x4000202f
+#define MASK_AMOOR_W 0xf800707f
+#define MATCH_AMOAND_W 0x6000202f
+#define MASK_AMOAND_W 0xf800707f
+#define MATCH_AMOMIN_W 0x8000202f
+#define MASK_AMOMIN_W 0xf800707f
+#define MATCH_AMOMAX_W 0xa000202f
+#define MASK_AMOMAX_W 0xf800707f
+#define MATCH_AMOMINU_W 0xc000202f
+#define MASK_AMOMINU_W 0xf800707f
+#define MATCH_AMOMAXU_W 0xe000202f
+#define MASK_AMOMAXU_W 0xf800707f
+#define MATCH_AMOSWAP_W 0x800202f
+#define MASK_AMOSWAP_W 0xf800707f
+#define MATCH_LR_W 0x1000202f
+#define MASK_LR_W 0xf9f0707f
+#define MATCH_SC_W 0x1800202f
+#define MASK_SC_W 0xf800707f
+#define MATCH_AMOADD_D 0x302f
+#define MASK_AMOADD_D 0xf800707f
+#define MATCH_AMOXOR_D 0x2000302f
+#define MASK_AMOXOR_D 0xf800707f
+#define MATCH_AMOOR_D 0x4000302f
+#define MASK_AMOOR_D 0xf800707f
+#define MATCH_AMOAND_D 0x6000302f
+#define MASK_AMOAND_D 0xf800707f
+#define MATCH_AMOMIN_D 0x8000302f
+#define MASK_AMOMIN_D 0xf800707f
+#define MATCH_AMOMAX_D 0xa000302f
+#define MASK_AMOMAX_D 0xf800707f
+#define MATCH_AMOMINU_D 0xc000302f
+#define MASK_AMOMINU_D 0xf800707f
+#define MATCH_AMOMAXU_D 0xe000302f
+#define MASK_AMOMAXU_D 0xf800707f
+#define MATCH_AMOSWAP_D 0x800302f
+#define MASK_AMOSWAP_D 0xf800707f
+#define MATCH_LR_D 0x1000302f
+#define MASK_LR_D 0xf9f0707f
+#define MATCH_SC_D 0x1800302f
+#define MASK_SC_D 0xf800707f
+#define MATCH_ECALL 0x73
+#define MASK_ECALL 0xffffffff
+#define MATCH_EBREAK 0x100073
+#define MASK_EBREAK 0xffffffff
+#define MATCH_URET 0x200073
+#define MASK_URET 0xffffffff
+#define MATCH_SRET 0x10200073
+#define MASK_SRET 0xffffffff
+#define MATCH_HRET 0x20200073
+#define MASK_HRET 0xffffffff
+#define MATCH_MRET 0x30200073
+#define MASK_MRET 0xffffffff
+#define MATCH_DRET 0x7b200073
+#define MASK_DRET 0xffffffff
+#define MATCH_SFENCE_VM 0x10400073
+#define MASK_SFENCE_VM 0xfff07fff
+#define MATCH_WFI 0x10500073
+#define MASK_WFI 0xffffffff
+#define MATCH_CSRRW 0x1073
+#define MASK_CSRRW 0x707f
+#define MATCH_CSRRS 0x2073
+#define MASK_CSRRS 0x707f
+#define MATCH_CSRRC 0x3073
+#define MASK_CSRRC 0x707f
+#define MATCH_CSRRWI 0x5073
+#define MASK_CSRRWI 0x707f
+#define MATCH_CSRRSI 0x6073
+#define MASK_CSRRSI 0x707f
+#define MATCH_CSRRCI 0x7073
+#define MASK_CSRRCI 0x707f
+#define MATCH_FADD_S 0x53
+#define MASK_FADD_S 0xfe00007f
+#define MATCH_FSUB_S 0x8000053
+#define MASK_FSUB_S 0xfe00007f
+#define MATCH_FMUL_S 0x10000053
+#define MASK_FMUL_S 0xfe00007f
+#define MATCH_FDIV_S 0x18000053
+#define MASK_FDIV_S 0xfe00007f
+#define MATCH_FSGNJ_S 0x20000053
+#define MASK_FSGNJ_S 0xfe00707f
+#define MATCH_FSGNJN_S 0x20001053
+#define MASK_FSGNJN_S 0xfe00707f
+#define MATCH_FSGNJX_S 0x20002053
+#define MASK_FSGNJX_S 0xfe00707f
+#define MATCH_FMIN_S 0x28000053
+#define MASK_FMIN_S 0xfe00707f
+#define MATCH_FMAX_S 0x28001053
+#define MASK_FMAX_S 0xfe00707f
+#define MATCH_FSQRT_S 0x58000053
+#define MASK_FSQRT_S 0xfff0007f
+#define MATCH_FADD_D 0x2000053
+#define MASK_FADD_D 0xfe00007f
+#define MATCH_FSUB_D 0xa000053
+#define MASK_FSUB_D 0xfe00007f
+#define MATCH_FMUL_D 0x12000053
+#define MASK_FMUL_D 0xfe00007f
+#define MATCH_FDIV_D 0x1a000053
+#define MASK_FDIV_D 0xfe00007f
+#define MATCH_FSGNJ_D 0x22000053
+#define MASK_FSGNJ_D 0xfe00707f
+#define MATCH_FSGNJN_D 0x22001053
+#define MASK_FSGNJN_D 0xfe00707f
+#define MATCH_FSGNJX_D 0x22002053
+#define MASK_FSGNJX_D 0xfe00707f
+#define MATCH_FMIN_D 0x2a000053
+#define MASK_FMIN_D 0xfe00707f
+#define MATCH_FMAX_D 0x2a001053
+#define MASK_FMAX_D 0xfe00707f
+#define MATCH_FCVT_S_D 0x40100053
+#define MASK_FCVT_S_D 0xfff0007f
+#define MATCH_FCVT_D_S 0x42000053
+#define MASK_FCVT_D_S 0xfff0007f
+#define MATCH_FSQRT_D 0x5a000053
+#define MASK_FSQRT_D 0xfff0007f
+#define MATCH_FLE_S 0xa0000053
+#define MASK_FLE_S 0xfe00707f
+#define MATCH_FLT_S 0xa0001053
+#define MASK_FLT_S 0xfe00707f
+#define MATCH_FEQ_S 0xa0002053
+#define MASK_FEQ_S 0xfe00707f
+#define MATCH_FLE_D 0xa2000053
+#define MASK_FLE_D 0xfe00707f
+#define MATCH_FLT_D 0xa2001053
+#define MASK_FLT_D 0xfe00707f
+#define MATCH_FEQ_D 0xa2002053
+#define MASK_FEQ_D 0xfe00707f
+#define MATCH_FCVT_W_S 0xc0000053
+#define MASK_FCVT_W_S 0xfff0007f
+#define MATCH_FCVT_WU_S 0xc0100053
+#define MASK_FCVT_WU_S 0xfff0007f
+#define MATCH_FCVT_L_S 0xc0200053
+#define MASK_FCVT_L_S 0xfff0007f
+#define MATCH_FCVT_LU_S 0xc0300053
+#define MASK_FCVT_LU_S 0xfff0007f
+#define MATCH_FMV_X_S 0xe0000053
+#define MASK_FMV_X_S 0xfff0707f
+#define MATCH_FCLASS_S 0xe0001053
+#define MASK_FCLASS_S 0xfff0707f
+#define MATCH_FCVT_W_D 0xc2000053
+#define MASK_FCVT_W_D 0xfff0007f
+#define MATCH_FCVT_WU_D 0xc2100053
+#define MASK_FCVT_WU_D 0xfff0007f
+#define MATCH_FCVT_L_D 0xc2200053
+#define MASK_FCVT_L_D 0xfff0007f
+#define MATCH_FCVT_LU_D 0xc2300053
+#define MASK_FCVT_LU_D 0xfff0007f
+#define MATCH_FMV_X_D 0xe2000053
+#define MASK_FMV_X_D 0xfff0707f
+#define MATCH_FCLASS_D 0xe2001053
+#define MASK_FCLASS_D 0xfff0707f
+#define MATCH_FCVT_S_W 0xd0000053
+#define MASK_FCVT_S_W 0xfff0007f
+#define MATCH_FCVT_S_WU 0xd0100053
+#define MASK_FCVT_S_WU 0xfff0007f
+#define MATCH_FCVT_S_L 0xd0200053
+#define MASK_FCVT_S_L 0xfff0007f
+#define MATCH_FCVT_S_LU 0xd0300053
+#define MASK_FCVT_S_LU 0xfff0007f
+#define MATCH_FMV_S_X 0xf0000053
+#define MASK_FMV_S_X 0xfff0707f
+#define MATCH_FCVT_D_W 0xd2000053
+#define MASK_FCVT_D_W 0xfff0007f
+#define MATCH_FCVT_D_WU 0xd2100053
+#define MASK_FCVT_D_WU 0xfff0007f
+#define MATCH_FCVT_D_L 0xd2200053
+#define MASK_FCVT_D_L 0xfff0007f
+#define MATCH_FCVT_D_LU 0xd2300053
+#define MASK_FCVT_D_LU 0xfff0007f
+#define MATCH_FMV_D_X 0xf2000053
+#define MASK_FMV_D_X 0xfff0707f
+#define MATCH_FLW 0x2007
+#define MASK_FLW 0x707f
+#define MATCH_FLD 0x3007
+#define MASK_FLD 0x707f
+#define MATCH_FSW 0x2027
+#define MASK_FSW 0x707f
+#define MATCH_FSD 0x3027
+#define MASK_FSD 0x707f
+#define MATCH_FMADD_S 0x43
+#define MASK_FMADD_S 0x600007f
+#define MATCH_FMSUB_S 0x47
+#define MASK_FMSUB_S 0x600007f
+#define MATCH_FNMSUB_S 0x4b
+#define MASK_FNMSUB_S 0x600007f
+#define MATCH_FNMADD_S 0x4f
+#define MASK_FNMADD_S 0x600007f
+#define MATCH_FMADD_D 0x2000043
+#define MASK_FMADD_D 0x600007f
+#define MATCH_FMSUB_D 0x2000047
+#define MASK_FMSUB_D 0x600007f
+#define MATCH_FNMSUB_D 0x200004b
+#define MASK_FNMSUB_D 0x600007f
+#define MATCH_FNMADD_D 0x200004f
+#define MASK_FNMADD_D 0x600007f
+#define MATCH_C_NOP 0x1
+#define MASK_C_NOP 0xffff
+#define MATCH_C_ADDI16SP 0x6101
+#define MASK_C_ADDI16SP 0xef83
+#define MATCH_C_JR 0x8002
+#define MASK_C_JR 0xf07f
+#define MATCH_C_JALR 0x9002
+#define MASK_C_JALR 0xf07f
+#define MATCH_C_EBREAK 0x9002
+#define MASK_C_EBREAK 0xffff
+#define MATCH_C_LD 0x6000
+#define MASK_C_LD 0xe003
+#define MATCH_C_SD 0xe000
+#define MASK_C_SD 0xe003
+#define MATCH_C_ADDIW 0x2001
+#define MASK_C_ADDIW 0xe003
+#define MATCH_C_LDSP 0x6002
+#define MASK_C_LDSP 0xe003
+#define MATCH_C_SDSP 0xe002
+#define MASK_C_SDSP 0xe003
+#define MATCH_C_ADDI4SPN 0x0
+#define MASK_C_ADDI4SPN 0xe003
+#define MATCH_C_FLD 0x2000
+#define MASK_C_FLD 0xe003
+#define MATCH_C_LW 0x4000
+#define MASK_C_LW 0xe003
+#define MATCH_C_FLW 0x6000
+#define MASK_C_FLW 0xe003
+#define MATCH_C_FSD 0xa000
+#define MASK_C_FSD 0xe003
+#define MATCH_C_SW 0xc000
+#define MASK_C_SW 0xe003
+#define MATCH_C_FSW 0xe000
+#define MASK_C_FSW 0xe003
+#define MATCH_C_ADDI 0x1
+#define MASK_C_ADDI 0xe003
+#define MATCH_C_JAL 0x2001
+#define MASK_C_JAL 0xe003
+#define MATCH_C_LI 0x4001
+#define MASK_C_LI 0xe003
+#define MATCH_C_LUI 0x6001
+#define MASK_C_LUI 0xe003
+#define MATCH_C_SRLI 0x8001
+#define MASK_C_SRLI 0xec03
+#define MATCH_C_SRAI 0x8401
+#define MASK_C_SRAI 0xec03
+#define MATCH_C_ANDI 0x8801
+#define MASK_C_ANDI 0xec03
+#define MATCH_C_SUB 0x8c01
+#define MASK_C_SUB 0xfc63
+#define MATCH_C_XOR 0x8c21
+#define MASK_C_XOR 0xfc63
+#define MATCH_C_OR 0x8c41
+#define MASK_C_OR 0xfc63
+#define MATCH_C_AND 0x8c61
+#define MASK_C_AND 0xfc63
+#define MATCH_C_SUBW 0x9c01
+#define MASK_C_SUBW 0xfc63
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW 0xfc63
+#define MATCH_C_J 0xa001
+#define MASK_C_J 0xe003
+#define MATCH_C_BEQZ 0xc001
+#define MASK_C_BEQZ 0xe003
+#define MATCH_C_BNEZ 0xe001
+#define MASK_C_BNEZ 0xe003
+#define MATCH_C_SLLI 0x2
+#define MASK_C_SLLI 0xe003
+#define MATCH_C_FLDSP 0x2002
+#define MASK_C_FLDSP 0xe003
+#define MATCH_C_LWSP 0x4002
+#define MASK_C_LWSP 0xe003
+#define MATCH_C_FLWSP 0x6002
+#define MASK_C_FLWSP 0xe003
+#define MATCH_C_MV 0x8002
+#define MASK_C_MV 0xf003
+#define MATCH_C_ADD 0x9002
+#define MASK_C_ADD 0xf003
+#define MATCH_C_FSDSP 0xa002
+#define MASK_C_FSDSP 0xe003
+#define MATCH_C_SWSP 0xc002
+#define MASK_C_SWSP 0xe003
+#define MATCH_C_FSWSP 0xe002
+#define MASK_C_FSWSP 0xe003
+#define MATCH_CUSTOM0 0xb
+#define MASK_CUSTOM0 0x707f
+#define MATCH_CUSTOM0_RS1 0x200b
+#define MASK_CUSTOM0_RS1 0x707f
+#define MATCH_CUSTOM0_RS1_RS2 0x300b
+#define MASK_CUSTOM0_RS1_RS2 0x707f
+#define MATCH_CUSTOM0_RD 0x400b
+#define MASK_CUSTOM0_RD 0x707f
+#define MATCH_CUSTOM0_RD_RS1 0x600b
+#define MASK_CUSTOM0_RD_RS1 0x707f
+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
+#define MASK_CUSTOM0_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM1 0x2b
+#define MASK_CUSTOM1 0x707f
+#define MATCH_CUSTOM1_RS1 0x202b
+#define MASK_CUSTOM1_RS1 0x707f
+#define MATCH_CUSTOM1_RS1_RS2 0x302b
+#define MASK_CUSTOM1_RS1_RS2 0x707f
+#define MATCH_CUSTOM1_RD 0x402b
+#define MASK_CUSTOM1_RD 0x707f
+#define MATCH_CUSTOM1_RD_RS1 0x602b
+#define MASK_CUSTOM1_RD_RS1 0x707f
+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
+#define MASK_CUSTOM1_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM2 0x5b
+#define MASK_CUSTOM2 0x707f
+#define MATCH_CUSTOM2_RS1 0x205b
+#define MASK_CUSTOM2_RS1 0x707f
+#define MATCH_CUSTOM2_RS1_RS2 0x305b
+#define MASK_CUSTOM2_RS1_RS2 0x707f
+#define MATCH_CUSTOM2_RD 0x405b
+#define MASK_CUSTOM2_RD 0x707f
+#define MATCH_CUSTOM2_RD_RS1 0x605b
+#define MASK_CUSTOM2_RD_RS1 0x707f
+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
+#define MASK_CUSTOM2_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM3 0x7b
+#define MASK_CUSTOM3 0x707f
+#define MATCH_CUSTOM3_RS1 0x207b
+#define MASK_CUSTOM3_RS1 0x707f
+#define MATCH_CUSTOM3_RS1_RS2 0x307b
+#define MASK_CUSTOM3_RS1_RS2 0x707f
+#define MATCH_CUSTOM3_RD 0x407b
+#define MASK_CUSTOM3_RD 0x707f
+#define MATCH_CUSTOM3_RD_RS1 0x607b
+#define MASK_CUSTOM3_RD_RS1 0x707f
+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
+#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
+#define CSR_FFLAGS 0x1
+#define CSR_FRM 0x2
+#define CSR_FCSR 0x3
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+#define CSR_INSTRET 0xc02
+#define CSR_HPMCOUNTER3 0xc03
+#define CSR_HPMCOUNTER4 0xc04
+#define CSR_HPMCOUNTER5 0xc05
+#define CSR_HPMCOUNTER6 0xc06
+#define CSR_HPMCOUNTER7 0xc07
+#define CSR_HPMCOUNTER8 0xc08
+#define CSR_HPMCOUNTER9 0xc09
+#define CSR_HPMCOUNTER10 0xc0a
+#define CSR_HPMCOUNTER11 0xc0b
+#define CSR_HPMCOUNTER12 0xc0c
+#define CSR_HPMCOUNTER13 0xc0d
+#define CSR_HPMCOUNTER14 0xc0e
+#define CSR_HPMCOUNTER15 0xc0f
+#define CSR_HPMCOUNTER16 0xc10
+#define CSR_HPMCOUNTER17 0xc11
+#define CSR_HPMCOUNTER18 0xc12
+#define CSR_HPMCOUNTER19 0xc13
+#define CSR_HPMCOUNTER20 0xc14
+#define CSR_HPMCOUNTER21 0xc15
+#define CSR_HPMCOUNTER22 0xc16
+#define CSR_HPMCOUNTER23 0xc17
+#define CSR_HPMCOUNTER24 0xc18
+#define CSR_HPMCOUNTER25 0xc19
+#define CSR_HPMCOUNTER26 0xc1a
+#define CSR_HPMCOUNTER27 0xc1b
+#define CSR_HPMCOUNTER28 0xc1c
+#define CSR_HPMCOUNTER29 0xc1d
+#define CSR_HPMCOUNTER30 0xc1e
+#define CSR_HPMCOUNTER31 0xc1f
+#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_SBADADDR 0x143
+#define CSR_SIP 0x144
+#define CSR_SPTBR 0x180
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MTVAL 0x343
+#define CSR_MIP 0x344
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH 0x7b2
+#define CSR_MCYCLE 0xb00
+#define CSR_MINSTRET 0xb02
+#define CSR_MHPMCOUNTER3 0xb03
+#define CSR_MHPMCOUNTER4 0xb04
+#define CSR_MHPMCOUNTER5 0xb05
+#define CSR_MHPMCOUNTER6 0xb06
+#define CSR_MHPMCOUNTER7 0xb07
+#define CSR_MHPMCOUNTER8 0xb08
+#define CSR_MHPMCOUNTER9 0xb09
+#define CSR_MHPMCOUNTER10 0xb0a
+#define CSR_MHPMCOUNTER11 0xb0b
+#define CSR_MHPMCOUNTER12 0xb0c
+#define CSR_MHPMCOUNTER13 0xb0d
+#define CSR_MHPMCOUNTER14 0xb0e
+#define CSR_MHPMCOUNTER15 0xb0f
+#define CSR_MHPMCOUNTER16 0xb10
+#define CSR_MHPMCOUNTER17 0xb11
+#define CSR_MHPMCOUNTER18 0xb12
+#define CSR_MHPMCOUNTER19 0xb13
+#define CSR_MHPMCOUNTER20 0xb14
+#define CSR_MHPMCOUNTER21 0xb15
+#define CSR_MHPMCOUNTER22 0xb16
+#define CSR_MHPMCOUNTER23 0xb17
+#define CSR_MHPMCOUNTER24 0xb18
+#define CSR_MHPMCOUNTER25 0xb19
+#define CSR_MHPMCOUNTER26 0xb1a
+#define CSR_MHPMCOUNTER27 0xb1b
+#define CSR_MHPMCOUNTER28 0xb1c
+#define CSR_MHPMCOUNTER29 0xb1d
+#define CSR_MHPMCOUNTER30 0xb1e
+#define CSR_MHPMCOUNTER31 0xb1f
+#define CSR_MUCOUNTEREN 0x320
+#define CSR_MSCOUNTEREN 0x321
+#define CSR_MHPMEVENT3 0x323
+#define CSR_MHPMEVENT4 0x324
+#define CSR_MHPMEVENT5 0x325
+#define CSR_MHPMEVENT6 0x326
+#define CSR_MHPMEVENT7 0x327
+#define CSR_MHPMEVENT8 0x328
+#define CSR_MHPMEVENT9 0x329
+#define CSR_MHPMEVENT10 0x32a
+#define CSR_MHPMEVENT11 0x32b
+#define CSR_MHPMEVENT12 0x32c
+#define CSR_MHPMEVENT13 0x32d
+#define CSR_MHPMEVENT14 0x32e
+#define CSR_MHPMEVENT15 0x32f
+#define CSR_MHPMEVENT16 0x330
+#define CSR_MHPMEVENT17 0x331
+#define CSR_MHPMEVENT18 0x332
+#define CSR_MHPMEVENT19 0x333
+#define CSR_MHPMEVENT20 0x334
+#define CSR_MHPMEVENT21 0x335
+#define CSR_MHPMEVENT22 0x336
+#define CSR_MHPMEVENT23 0x337
+#define CSR_MHPMEVENT24 0x338
+#define CSR_MHPMEVENT25 0x339
+#define CSR_MHPMEVENT26 0x33a
+#define CSR_MHPMEVENT27 0x33b
+#define CSR_MHPMEVENT28 0x33c
+#define CSR_MHPMEVENT29 0x33d
+#define CSR_MHPMEVENT30 0x33e
+#define CSR_MHPMEVENT31 0x33f
+#define CSR_MVENDORID 0xf11
+#define CSR_MARCHID 0xf12
+#define CSR_MIMPID 0xf13
+#define CSR_MHARTID 0xf14
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MCYCLEH 0xb80
+#define CSR_MINSTRETH 0xb82
+#define CSR_MHPMCOUNTER3H 0xb83
+#define CSR_MHPMCOUNTER4H 0xb84
+#define CSR_MHPMCOUNTER5H 0xb85
+#define CSR_MHPMCOUNTER6H 0xb86
+#define CSR_MHPMCOUNTER7H 0xb87
+#define CSR_MHPMCOUNTER8H 0xb88
+#define CSR_MHPMCOUNTER9H 0xb89
+#define CSR_MHPMCOUNTER10H 0xb8a
+#define CSR_MHPMCOUNTER11H 0xb8b
+#define CSR_MHPMCOUNTER12H 0xb8c
+#define CSR_MHPMCOUNTER13H 0xb8d
+#define CSR_MHPMCOUNTER14H 0xb8e
+#define CSR_MHPMCOUNTER15H 0xb8f
+#define CSR_MHPMCOUNTER16H 0xb90
+#define CSR_MHPMCOUNTER17H 0xb91
+#define CSR_MHPMCOUNTER18H 0xb92
+#define CSR_MHPMCOUNTER19H 0xb93
+#define CSR_MHPMCOUNTER20H 0xb94
+#define CSR_MHPMCOUNTER21H 0xb95
+#define CSR_MHPMCOUNTER22H 0xb96
+#define CSR_MHPMCOUNTER23H 0xb97
+#define CSR_MHPMCOUNTER24H 0xb98
+#define CSR_MHPMCOUNTER25H 0xb99
+#define CSR_MHPMCOUNTER26H 0xb9a
+#define CSR_MHPMCOUNTER27H 0xb9b
+#define CSR_MHPMCOUNTER28H 0xb9c
+#define CSR_MHPMCOUNTER29H 0xb9d
+#define CSR_MHPMCOUNTER30H 0xb9e
+#define CSR_MHPMCOUNTER31H 0xb9f
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FAULT_FETCH 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT 0x3
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_FAULT_LOAD 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_FAULT_STORE 0x7
+#define CAUSE_USER_ECALL 0x8
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_HYPERVISOR_ECALL 0xa
+#define CAUSE_MACHINE_ECALL 0xb
+#define CAUSE_FETCH_PAGE_FAULT 0xc
+#define CAUSE_LOAD_PAGE_FAULT 0xd
+#define CAUSE_RESERVED 0xe
+#define CAUSE_STORE_PAGE_FAULT 0xf
+#endif
+#ifdef DECLARE_INSN
+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
+ DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
+ DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
+ DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
+ DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
+ DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
+ DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
+ DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
+ DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
+ DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
+ DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
+ DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
+ DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
+ DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
+ DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
+ DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
+ DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
+ DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
+ DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
+ DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
+ DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
+ DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
+ DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
+ DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
+ DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
+ DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
+ DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
+ DECLARE_INSN(or, MATCH_OR, MASK_OR)
+ DECLARE_INSN(and, MATCH_AND, MASK_AND)
+ DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
+ DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
+ DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
+ DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
+ DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
+ DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
+ DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
+ DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
+ DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
+ DECLARE_INSN(lb, MATCH_LB, MASK_LB)
+ DECLARE_INSN(lh, MATCH_LH, MASK_LH)
+ DECLARE_INSN(lw, MATCH_LW, MASK_LW)
+ DECLARE_INSN(ld, MATCH_LD, MASK_LD)
+ DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
+ DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+ DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
+ DECLARE_INSN(sb, MATCH_SB, MASK_SB)
+ DECLARE_INSN(sh, MATCH_SH, MASK_SH)
+ DECLARE_INSN(sw, MATCH_SW, MASK_SW)
+ DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+ DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
+ DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
+ DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
+ DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
+ DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
+ DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
+ DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
+ DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
+ DECLARE_INSN(rem, MATCH_REM, MASK_REM)
+ DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
+ DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
+ DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
+ DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
+ DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
+ DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
+ DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
+ DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
+ DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
+ DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
+ DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
+ DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
+ DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
+ DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
+ DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
+ DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
+ DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
+ DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
+ DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
+ DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
+ DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
+ DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
+ DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
+ DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
+ DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
+ DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
+ DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
+ DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
+ DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
+ DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
+ DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+ DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+ DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
+ DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+ DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+ DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
+ DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
+ DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
+ DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
+ DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
+ DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
+ DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
+ DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+ DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
+ DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
+ DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
+ DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
+ DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
+ DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
+ DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
+ DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
+ DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
+ DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
+ DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
+ DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
+ DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
+ DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
+ DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
+ DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
+ DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
+ DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
+ DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
+ DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
+ DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
+ DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+ DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
+ DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
+ DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+ DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+ DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+ DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+ DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
+ DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
+ DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
+ DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
+ DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
+ DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+ DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
+ DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
+ DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+ DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+ DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+ DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+ DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
+ DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
+ DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
+ DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
+ DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
+ DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
+ DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+ DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+ DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+ DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
+ DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+ DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+ DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+ DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+ DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
+ DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
+ DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
+ DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
+ DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+ DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+ DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+ DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+ DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
+ DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
+ DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
+ DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
+ DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
+ DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
+ DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
+ DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
+ DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+ DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+ DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
+ DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
+ DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
+ DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
+ DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
+ DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
+ DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
+ DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
+ DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
+ DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
+ DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
+ DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
+ DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
+ DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
+ DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
+ DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
+ DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
+ DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
+ DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+ DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
+ DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
+ DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
+ DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
+ DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
+ DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
+ DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
+ DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
+ DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
+ DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
+ DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
+ DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
+ DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
+ DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
+ DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
+ DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
+ DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
+ DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
+ DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2,
+ MASK_CUSTOM0_RD_RS1_RS2)
+ DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
+ DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
+ DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
+ DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
+ DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
+ DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2,
+ MASK_CUSTOM1_RD_RS1_RS2)
+ DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
+ DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
+ DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
+ DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
+ DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
+ DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2,
+ MASK_CUSTOM2_RD_RS1_RS2)
+ DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
+ DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
+ DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
+ DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
+ DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
+ DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2,
+ MASK_CUSTOM3_RD_RS1_RS2)
+#endif
+#ifdef DECLARE_CSR
+ DECLARE_CSR(fflags, CSR_FFLAGS)
+ DECLARE_CSR(frm, CSR_FRM)
+ DECLARE_CSR(fcsr, CSR_FCSR)
+ DECLARE_CSR(cycle, CSR_CYCLE)
+ DECLARE_CSR(time, CSR_TIME)
+ DECLARE_CSR(instret, CSR_INSTRET)
+ DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
+ DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
+ DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
+ DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
+ DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
+ DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
+ DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
+ DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
+ DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
+ DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
+ DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
+ DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
+ DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
+ DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
+ DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
+ DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
+ DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
+ DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
+ DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
+ DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
+ DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
+ DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
+ DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
+ DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
+ DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
+ DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
+ DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
+ DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
+ DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+ DECLARE_CSR(sstatus, CSR_SSTATUS)
+ DECLARE_CSR(sie, CSR_SIE)
+ DECLARE_CSR(stvec, CSR_STVEC)
+ DECLARE_CSR(sscratch, CSR_SSCRATCH)
+ DECLARE_CSR(sepc, CSR_SEPC)
+ DECLARE_CSR(scause, CSR_SCAUSE)
+ DECLARE_CSR(sbadaddr, CSR_SBADADDR)
+ DECLARE_CSR(sip, CSR_SIP)
+ DECLARE_CSR(sptbr, CSR_SPTBR)
+ DECLARE_CSR(mstatus, CSR_MSTATUS)
+ DECLARE_CSR(misa, CSR_MISA)
+ DECLARE_CSR(medeleg, CSR_MEDELEG)
+ DECLARE_CSR(mideleg, CSR_MIDELEG)
+ DECLARE_CSR(mie, CSR_MIE)
+ DECLARE_CSR(mtvec, CSR_MTVEC)
+ DECLARE_CSR(mscratch, CSR_MSCRATCH)
+ DECLARE_CSR(mepc, CSR_MEPC)
+ DECLARE_CSR(mcause, CSR_MCAUSE)
+ DECLARE_CSR(mbadaddr, CSR_MTVAL)
+ DECLARE_CSR(mip, CSR_MIP)
+ DECLARE_CSR(tselect, CSR_TSELECT)
+ DECLARE_CSR(tdata1, CSR_TDATA1)
+ DECLARE_CSR(tdata2, CSR_TDATA2)
+ DECLARE_CSR(tdata3, CSR_TDATA3)
+ DECLARE_CSR(dcsr, CSR_DCSR)
+ DECLARE_CSR(dpc, CSR_DPC)
+ DECLARE_CSR(dscratch, CSR_DSCRATCH)
+ DECLARE_CSR(mcycle, CSR_MCYCLE)
+ DECLARE_CSR(minstret, CSR_MINSTRET)
+ DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
+ DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
+ DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
+ DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
+ DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
+ DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
+ DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
+ DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
+ DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
+ DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
+ DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
+ DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
+ DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
+ DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
+ DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
+ DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
+ DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
+ DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
+ DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
+ DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
+ DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
+ DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
+ DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
+ DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
+ DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
+ DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
+ DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
+ DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
+ DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
+ DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
+ DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
+ DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
+ DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
+ DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
+ DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
+ DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
+ DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
+ DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
+ DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
+ DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
+ DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
+ DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
+ DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
+ DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
+ DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
+ DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
+ DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
+ DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
+ DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
+ DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
+ DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
+ DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
+ DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
+ DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
+ DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
+ DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
+ DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
+ DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
+ DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
+ DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
+ DECLARE_CSR(mvendorid, CSR_MVENDORID)
+ DECLARE_CSR(marchid, CSR_MARCHID)
+ DECLARE_CSR(mimpid, CSR_MIMPID)
+ DECLARE_CSR(mhartid, CSR_MHARTID)
+ DECLARE_CSR(cycleh, CSR_CYCLEH)
+ DECLARE_CSR(timeh, CSR_TIMEH)
+ DECLARE_CSR(instreth, CSR_INSTRETH)
+ DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
+ DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
+ DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
+ DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
+ DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
+ DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
+ DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
+ DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
+ DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
+ DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
+ DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
+ DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
+ DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
+ DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
+ DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
+ DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
+ DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
+ DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
+ DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
+ DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
+ DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
+ DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
+ DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
+ DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
+ DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
+ DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
+ DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
+ DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
+ DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+ DECLARE_CSR(mcycleh, CSR_MCYCLEH)
+ DECLARE_CSR(minstreth, CSR_MINSTRETH)
+ DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
+ DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
+ DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
+ DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
+ DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
+ DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
+ DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
+ DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
+ DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
+ DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
+ DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
+ DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
+ DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
+ DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
+ DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
+ DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
+ DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
+ DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
+ DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
+ DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
+ DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
+ DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
+ DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
+ DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
+ DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
+ DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
+ DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
+ DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
+ DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+#endif
+#ifdef DECLARE_CAUSE
+ DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
+ DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
+ DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
+ DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
+ DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
+ DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
+ DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
+ DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
+ DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
+ DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
+ DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
+ DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
+#endif
diff --git a/src/tinysys/medmcu/drivers/common/MemMang/mt_heap_2.c b/src/tinysys/medmcu/drivers/common/MemMang/mt_heap_2.c
new file mode 100644
index 0000000..b6c1f13
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/MemMang/mt_heap_2.c
@@ -0,0 +1,292 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
+ * ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
+ * THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
+ * SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
+ * RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
+ * FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
+ * WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
+ * AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
+ * RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation
+ * ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
+ * subject to any receiver\'s applicable license agreements with MediaTek Inc.
+ */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers. That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "encoding.h"
+#include "mt_driver_api.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+ #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* A few bytes might be lost to byte aligning the heap start address. */
+#ifdef CFG_AMP_CORE1_EN
+#define configADJUSTED_HEAP_SIZE (mrv_read_csr(CSR_MHARTID) ? ( configTOTAL_HEAP_SIZE_1 - portBYTE_ALIGNMENT ) : ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT ))
+#else
+#define configADJUSTED_HEAP_SIZE ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
+#endif
+
+/*
+ * Initialises the heap structures before their first use.
+ */
+static void prvHeapInit( void );
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+ /* The application writer has already defined the array used for the RTOS
+ heap - probably so it can be placed in a special segment or address. */
+ extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ] L1TCM_REGION_RW;
+#ifdef CFG_AMP_CORE1_EN
+ extern uint8_t ucHeap_1[ configTOTAL_HEAP_SIZE_1 ] CORE1_DATA;
+#endif
+#else
+ static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ] L1TCM_REGION_RW;
+#ifdef CFG_AMP_CORE1_EN
+ static uint8_t ucHeap_1[ configTOTAL_HEAP_SIZE_1 ] CORE1_DATA;
+#endif
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+
+/* Define the linked list structure. This is used to link free blocks in order
+of their size. */
+typedef struct A_BLOCK_LINK
+{
+ struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */
+ size_t xBlockSize; /*<< The size of the free block. */
+} BlockLink_t;
+
+
+static const uint16_t heapSTRUCT_SIZE = ( ( sizeof ( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );
+#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, xEnd;
+
+/* Keeps track of the number of free bytes remaining, but says nothing about
+fragmentation. */
+static size_t xFreeBytesRemaining;
+
+/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */
+
+/*
+ * Insert a block into the list of free blocks - which is ordered by size of
+ * the block. Small blocks at the start of the list and large blocks at the end
+ * of the list.
+ */
+#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \
+{ \
+BlockLink_t *pxIterator; \
+size_t xBlockSize; \
+ \
+ xBlockSize = pxBlockToInsert->xBlockSize; \
+ \
+ /* Iterate through the list until a block is found that has a larger size */ \
+ /* than the block we are inserting. */ \
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \
+ { \
+ /* There is nothing to do here - just iterate to the correct position. */ \
+ } \
+ \
+ /* Update the list to include the block being inserted in the correct */ \
+ /* position. */ \
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \
+ pxIterator->pxNextFreeBlock = pxBlockToInsert; \
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+static BaseType_t xHeapHasBeenInitialised = pdFALSE;
+void *pvReturn = NULL;
+
+ vTaskSuspendAll();
+ {
+ /* If this is the first call to malloc then the heap will require
+ initialisation to setup the list of free blocks. */
+ if( xHeapHasBeenInitialised == pdFALSE )
+ {
+ prvHeapInit();
+ xHeapHasBeenInitialised = pdTRUE;
+ }
+
+ /* The wanted size is increased so it can contain a BlockLink_t
+ structure in addition to the requested amount of bytes. */
+ if( xWantedSize > 0 )
+ {
+ xWantedSize += heapSTRUCT_SIZE;
+
+ /* Ensure that blocks are always aligned to the required number of bytes. */
+ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0 )
+ {
+ /* Byte alignment required. */
+ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+ }
+ }
+
+ if( ( xWantedSize > 0 ) && ( xWantedSize < configADJUSTED_HEAP_SIZE ) )
+ {
+ /* Blocks are stored in byte order - traverse the list from the start
+ (smallest) block until one of adequate size is found. */
+ pxPreviousBlock = &xStart;
+ pxBlock = xStart.pxNextFreeBlock;
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ {
+ pxPreviousBlock = pxBlock;
+ pxBlock = pxBlock->pxNextFreeBlock;
+ }
+
+ /* If we found the end marker then a block of adequate size was not found. */
+ if( pxBlock != &xEnd )
+ {
+ /* Return the memory space - jumping over the BlockLink_t structure
+ at its start. */
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );
+
+ /* This block is being returned for use so must be taken out of the
+ list of free blocks. */
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+ /* If the block is larger than required it can be split into two. */
+ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+ {
+ /* This block is to be split into two. Create a new block
+ following the number of bytes requested. The void cast is
+ used to prevent byte alignment warnings from the compiler. */
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+
+ /* Calculate the sizes of two blocks split from the single
+ block. */
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+ pxBlock->xBlockSize = xWantedSize;
+
+ /* Insert the new block into the list of free blocks. */
+ prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
+ }
+
+ xFreeBytesRemaining -= pxBlock->xBlockSize;
+ }
+ }
+
+ traceMALLOC( pvReturn, xWantedSize );
+ }
+ ( void ) xTaskResumeAll();
+
+ #if( configUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
+ {
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
+ }
+ }
+ #endif
+
+ return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+ if( pv != NULL )
+ {
+ /* The memory being freed will have an BlockLink_t structure immediately
+ before it. */
+ puc -= heapSTRUCT_SIZE;
+
+ /* This unexpected casting is to keep some compilers from issuing
+ byte alignment warnings. */
+ pxLink = ( void * ) puc;
+
+ vTaskSuspendAll();
+ {
+ /* Add this block to the list of free blocks. */
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+ xFreeBytesRemaining += pxLink->xBlockSize;
+ traceFREE( pv, pxLink->xBlockSize );
+ }
+ ( void ) xTaskResumeAll();
+ }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+ return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+ /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+
+ xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;
+ /* Ensure the heap starts on a correctly aligned boundary. */
+#ifdef CFG_AMP_CORE1_EN
+ if (mrv_read_csr(CSR_MHARTID) == 1)
+ pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap_1[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+ else
+#endif
+ {
+ pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+ }
+
+ /* xStart is used to hold a pointer to the first item in the list of free
+ blocks. The void cast is used to prevent compiler warnings. */
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+ xStart.xBlockSize = ( size_t ) 0;
+
+ /* xEnd is used to mark the end of the list of free blocks. */
+ xEnd.xBlockSize = configADJUSTED_HEAP_SIZE;
+ xEnd.pxNextFreeBlock = NULL;
+
+ /* To start with there is a single free block that is sized to take up the
+ entire heap space. */
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+ pxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE;
+ pxFirstFreeBlock->pxNextFreeBlock = &xEnd;
+}
+/*-----------------------------------------------------------*/
diff --git a/src/tinysys/medmcu/drivers/common/bus_tracker/inc/bus_tracker.h b/src/tinysys/medmcu/drivers/common/bus_tracker/inc/bus_tracker.h
new file mode 100644
index 0000000..84d25fe
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/bus_tracker/inc/bus_tracker.h
@@ -0,0 +1,136 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ */
+/* MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
+ * ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
+ * THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
+ * SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
+ * RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
+ * FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
+ * WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
+ * AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
+ * RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation
+ * ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
+ * subject to any receiver\'s applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __BUS_TRACKER_H__
+#define __BUS_TRACKER_H__
+
+#include <encoding.h>
+#include <peripheral.h>
+#ifdef CFG_WDT_SUPPORT
+#include <wdt.h>
+#endif
+#define BUS_TRACKER_DEBUG 1
+#define BUS_TRACKER_LOG 1
+
+#if BUS_TRACKER_DEBUG
+#define TRACKER_DBG(x...) printf(x)
+#else
+#define TRACKER_DBG(x...)
+#endif
+#define BUS_TRACKER_DEBUG 1
+
+#if BUS_TRACKER_LOG
+#define TRACKER_LOG(x...) printf(x)
+#else
+#define TRACKER_LOG(x...)
+#endif
+
+#ifndef CFG_FPGA
+#define BUS_TRACKER_STAGE1_TIMEOUT (19600) /* 1ms @ 196Mhz = 19600 *0x10 */
+#define BUS_TRACKER_STAGE2_TIMEOUT (196000000) /* 16s @ 196Mhz = 19600000 *0x10*/
+#else
+#define BUS_TRACKER_STAGE1_TIMEOUT (19600)
+#define BUS_TRACKER_STAGE2_TIMEOUT (19600)
+#endif
+#define BUS_TRACKER_WATCHPOINT (0)
+#define BUS_TRACKER_WATCHPOINT_MASK (0)
+
+void dump_bus_tracker_status(void);
+unsigned int bus_tracker_handler(void *ptr);
+void bus_tracker_init(void);
+
+/* AXI abort */
+static inline unsigned int axi_get_cause(void)
+{
+ unsigned long reg;
+ reg = mrv_read_csr(CSR_MIMABTCAU);
+ return (unsigned int) reg;
+}
+static inline unsigned int axi_get_address(void)
+{
+ unsigned long reg;
+ reg = mrv_read_csr(CSR_MIMABTADDR);
+ return (unsigned int) reg;
+}
+static inline void axi_clear_status(void)
+{
+ mrv_write_csr(CSR_MIMABTCAU, 0);
+ return;
+}
+
+static inline void bus_tracker_plat_init(void)
+{
+
+/* due to scp bus idle is simulated by register,
+ bus tracker should be initialed before bus transaction start */
+ drv_write_reg32(SCP_DBG_CTRL, TRACKER_FORCE_IDLE);
+
+#ifdef CFG_BUS_TRACKER_INTERRUPT_MODE
+ drv_write_reg32(SCP_TRACKER_CTRL,
+ BUS_WP_SLV_ERR_EN | DBG_AW_TIMEOUT_IRQ_EN |
+ DBG_AR_TIMEOUT_IRQ_EN | DBG_SLV_ERR_EN |
+ DBG_TIMEOUT_EN | DBG_CON_EN);
+
+#else
+ drv_write_reg32(SCP_TRACKER_CTRL,
+ BUS_WP_SLV_ERR_EN | DBG_SLV_ERR_EN | DBG_TIMEOUT_EN
+ | DBG_CON_EN);
+#endif
+}
+
+static inline void bus_tracker_handler_plat_start(void)
+{
+#ifndef CFG_BUS_TRACKER_INTERRUPT_MODE
+ TRACKER_LOG("bus err cause/addr %08x %08x\n", axi_get_cause(),
+ axi_get_address());
+#endif
+}
+static inline void bus_tracker_handler_plat_end(void)
+{
+ axi_clear_status();
+ vic_set_mask(0, 0x0);
+ vic_set_wakeup_mask(0, 0x0);
+#ifdef CFG_WDT_SUPPORT
+ mtk_wdt_set_time_out_value(10); /*assign a small value to make ee sooner */
+ mtk_wdt_restart();
+
+#endif
+ /* Halt CPU */
+ __asm volatile ("wfi");
+}
+
+#endif /* __BUS_TRACKER_H__ */
diff --git a/src/tinysys/medmcu/drivers/common/cache/inc/dmgr.h b/src/tinysys/medmcu/drivers/common/cache/inc/dmgr.h
new file mode 100644
index 0000000..ec551ce
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/cache/inc/dmgr.h
@@ -0,0 +1,130 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek Software")
+ * have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+ * applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __CACHE_DRAM_MANAGEMENT_H__
+#define __CACHE_DRAM_MANAGEMENT_H__
+
+#include <stdint.h>
+#include <FreeRTOS.h>
+#include <task.h>
+
+#define IDX_STACK_PC (6)
+#define IDX_STACK_PSR (7)
+
+#define MAX_DMGR_QUEUE_EVENT (10)
+#define MAX_DMGR_LIST_ITEM MAX_DMGR_QUEUE_EVENT
+
+#define OSTICKS_TO_NS (77)
+#define DURATION_LIMIT_NS (20000000) /* 20ms */
+
+#define UNUSED(x) (void)(x)
+
+#ifdef CFG_DMGR_DEBUG
+/*
+ * Use the flag to categorize the log message according to different operations.
+ * Each bit in uxLogBitmap is a switch for printing message specified by the flag.
+ * The uxLogBitmap is initialized by the config, CFG_DMGR_DEBUG, and the default
+ * value is 9, meaning that log belonged to categories LOG_REGAPI and LOG_LATENCY
+ * will be shown on the screen.
+ */
+#define DMGR_PRINTF(flag, fmt, ...) \
+ do { \
+ if(uxLogBitmap & (1 << flag)) \
+ PRINTF_E("%s <%d> " fmt "\n", pcPrompt, flag, ##__VA_ARGS__); \
+ } while(0)
+#else
+#define DMGR_PRINTF(flag, fmt, ...)
+#endif
+#define DMGR_ERROR(fmt, ...) \
+ PRINTF_E("%s Err, " fmt "\n", pcPrompt, ##__VA_ARGS__); \
+ configASSERT(0);
+#define DMGR_WARN(fmt, ...) \
+ PRINTF_E("%s WARN, " fmt "\n", pcPrompt, ##__VA_ARGS__);
+
+enum dramMgrState {
+ STAT_DRAM_PW_OFF,
+ STAT_DRAM_WARM_UP,
+ STAT_DRAM_PW_ON,
+};
+
+enum dramMgrAction {
+ ACT_DRAM_DETECT_ACCESS,
+ ACT_DRAM_POWER_ON,
+ ACT_DRAM_POWER_OFF,
+
+ ACT_EXCEPT_POWER_ON,
+};
+
+typedef enum dramMgrAccssType {
+ TYPE_INVALID,
+ TYPE_NORMAL,
+ TYPE_EXCEPTION,
+ TYPE_CRITICAL
+} DramMgrAccssType_t;
+
+struct dramMgrQueueEvent {
+ enum dramMgrAction eAction;
+ TaskHandle_t xHandle;
+};
+
+#ifdef CFG_DMGR_DEBUG
+/*
+ * Control DMGR's log by specifying the bits of the control
+ * variable, uxLogBitmap, with the enum, logBitPos
+ */
+enum logBitPos {
+ LOG_TASKTRACE,
+ LOG_ONOFF,
+ LOG_LATENCY,
+ LOG_TRAP,
+ LOG_STATE,
+};
+#endif
+
+extern char *pcPrompt;
+extern UBaseType_t uxLogBitmap;
+
+void vDmgrPortEnRegion(void);
+void vDmgrPortDisRegion(void);
+
+void vDmgrPortEnDRAMFromISR(void);
+void vDmgrPortDisDRAM(void);
+
+int32_t vDmgrPortGetDramAckFromISR(void);
+void vDmgrPortEnDRAMUnblock(void);
+
+DramMgrAccssType_t xDmgrPortAccessType(void);
+
+#endif
diff --git a/src/tinysys/medmcu/drivers/common/cache/inc/dmgr_api.h b/src/tinysys/medmcu/drivers/common/cache/inc/dmgr_api.h
new file mode 100644
index 0000000..9f6d64e
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/cache/inc/dmgr_api.h
@@ -0,0 +1,56 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek Software")
+ * have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+ * applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __DRAM_MANAGEMENT_API_H__
+#define __DRAM_MANAGEMENT_API_H__
+
+#ifdef CFG_CACHE_SUPPORT
+void vDmgrHookDVFSDramOn(void);
+void vDmgrHookDVFSDramOff(void);
+void vDmgrHookIdleApplication(void);
+BaseType_t xDmgrHookSwitchOnDramPower(void);
+BaseType_t xDmgrHookInit(void);
+
+#else
+/* Empty function */
+#define vDmgrHookDVFSDramOn() do {} while(0)
+#define vDmgrHookDVFSDramOff() do {} while(0)
+#define vDmgrHookIdleApplication() do {} while(0)
+#define xDmgrHookSwitchOnDramPower(x) (pdFALSE)
+#define xDmgrHookInit() (pdFALSE)
+
+#endif /* CFG_CACHE_SUPPORT */
+
+#endif /* __DRAM_MANAGEMENT_API_H__ */
diff --git a/src/tinysys/medmcu/drivers/common/cache/src/dmgr.c b/src/tinysys/medmcu/drivers/common/cache/src/dmgr.c
new file mode 100644
index 0000000..f65fb1c
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/cache/src/dmgr.c
@@ -0,0 +1,391 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek Software")
+ * have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+ * applicable license agreements with MediaTek Inc.
+ */
+
+#include <tinysys_config.h>
+#include <FreeRTOS.h>
+#include <task.h>
+#include <timers.h>
+#include <queue.h>
+#ifdef CFG_XGPT_SUPPORT
+#include <interrupt.h>
+#include <xgpt.h>
+#endif
+#include <FreeRTOSConfig.h>
+#include <dmgr.h>
+#include <dmgr_api.h>
+#include <mt_printf.h>
+#include <sleep.h>
+#include <dvfs_common.h>
+
+extern void *pxCurrentTCB;
+
+enum dramMgrState eExceptState;
+char *pcPrompt = "[DMGR]";
+
+#ifdef CFG_DMGR_DEBUG
+UBaseType_t uxLogBitmap = CFG_DMGR_DEBUG;
+#endif /* CFG_DMGR_DEBUG */
+
+/*****************************************************************************
+** CFG_DYNAMIC_DRAM_V2, Switch on/off DRAM in the context of a task.
+*****************************************************************************/
+
+#ifdef CFG_DYNAMIC_DRAM_V2
+
+struct {
+ unsigned long long ullDmgrMaxCost;
+ unsigned long long ullDmgrSendQTimeStamp;
+ unsigned long long ullDmgrLastDetectTimeStamp;
+ unsigned long long ullDmgrLastPowerOnTimeStamp;
+ unsigned long long ullDmgrDetectWfiSTimeStamp;
+ unsigned long long ullDmgrDetectWfiETimeStamp;
+ uint32_t ullDmgrDetectSlpCnt;
+ uint32_t ullDmgrPowerOnSlpCnt;
+ uint32_t ullDmgrDetectWFICnt;
+ uint32_t ullDmgrPowerOnWFICnt;
+ uint32_t ullDmgrTmrCnt;
+} xDmgrCost = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+enum dramMgrState eDramMgrState;
+static QueueHandle_t xDramMgrRxQueue;
+static List_t xDramMgrSuspendList;
+static List_t xDramMgrFreeList;
+static ListItem_t dramMgrItemPool[MAX_DMGR_LIST_ITEM];
+
+static void prvDmgrHwTimerStart(void)
+{
+ struct timer_device *pxDev = id_to_dev(DMGR_TIMER);
+ unsigned int ulBaseAddr = pxDev->base_addr;
+
+ DRV_WriteReg32(ulBaseAddr + TIMER_RST_VAL, DMGR_TIMER_RSTVAL);
+ DRV_SetReg32(ulBaseAddr + TIMER_IRQ_CTRL_REG, TIMER_ENABLE);
+ /* select clock source to clk_32k and enable timer */
+ DRV_SetReg32(ulBaseAddr + TIMER_EN,
+ (TIMER_CLK_SRC_CLK_32K << TIMER_CLK_SRC_SHIFT) |
+ TIMER_IRQ_ENABLE);
+}
+
+static void prvDmgrHwTimerStop(void)
+{
+ struct timer_device *pxDev = id_to_dev(DMGR_TIMER);
+ unsigned int ulBaseAddr = pxDev->base_addr;
+
+ DRV_ClrReg32(ulBaseAddr + TIMER_EN, TIMER_ENABLE);
+ DRV_ClrReg32(ulBaseAddr + TIMER_IRQ_CTRL_REG, TIMER_IRQ_ENABLE);
+ /* act timer interrupt */
+ DRV_SetReg32(ulBaseAddr + TIMER_IRQ_CTRL_REG, TIMER_IRQ_CLEAR);
+ //DRV_WriteReg32(ulBaseAddr + TIMER_RST_VAL, 0);
+}
+
+static void prvDmgrEventSend(TaskHandle_t xHandle, enum dramMgrAction eAction)
+{
+ struct dramMgrQueueEvent xEvent;
+ BaseType_t xHigherPriorityTaskWoken;
+ BaseType_t xRet = pdPASS;
+
+ xEvent.xHandle = (TaskHandle_t) xHandle;
+ xEvent.eAction = eAction;
+ /* send the current tcb to DramMgr to be suspended */
+ xDmgrCost.ullDmgrSendQTimeStamp = read_xgpt_stamp_ns();
+ xRet =
+ xQueueSendFromISR(xDramMgrRxQueue, &xEvent,
+ &xHigherPriorityTaskWoken);
+ configASSERT(xRet == pdTRUE);
+ /* context switching to dram manager */
+ portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+}
+
+static unsigned int prvDmgrPollingAck(void *arg)
+{
+ uint32_t ulIsAck = vDmgrPortGetDramAckFromISR();
+
+ UNUSED(arg);
+ configASSERT(eDramMgrState == STAT_DRAM_WARM_UP);
+
+ xDmgrCost.ullDmgrTmrCnt++;
+ prvDmgrHwTimerStop();
+ if (ulIsAck) {
+ DMGR_PRINTF(LOG_ONOFF, "p:dram on");
+ prvDmgrEventSend((TaskHandle_t) NULL, ACT_DRAM_POWER_ON);
+ } else
+ prvDmgrHwTimerStart();
+
+ return 0;
+}
+
+static void prvSuspendTask(TaskHandle_t xHandle)
+{
+ ListItem_t *pxDramMgrItem = NULL;
+
+ configASSERT(listLIST_IS_EMPTY(&xDramMgrFreeList) != pdTRUE);
+
+ /* get a empty item from free list */
+ pxDramMgrItem = listGET_HEAD_ENTRY(&xDramMgrFreeList);
+ uxListRemove(pxDramMgrItem);
+
+ /* initialize the item and then insert it into suspend list */
+ vListInitialiseItem(pxDramMgrItem);
+ listSET_LIST_ITEM_VALUE(pxDramMgrItem, (TickType_t) xHandle);
+ vListInsertEnd(&xDramMgrSuspendList, pxDramMgrItem);
+
+ /* as we have recorded the task in suspend list, it can be suspended */
+ vTaskSuspend(xHandle);
+ DMGR_PRINTF(LOG_TASKTRACE, "Suspend %s", pcTaskGetTaskName(xHandle));
+}
+
+static void prvResumeTask(TaskHandle_t xHandle)
+{
+ ListItem_t *pxDramMgrItem = NULL;
+
+ configASSERT(listLIST_IS_EMPTY(&xDramMgrSuspendList) != pdTRUE);
+
+ /* get an item from suspend list */
+ pxDramMgrItem = listGET_HEAD_ENTRY(&xDramMgrSuspendList);
+ xHandle = (TaskHandle_t) listGET_LIST_ITEM_VALUE(pxDramMgrItem);
+ uxListRemove(pxDramMgrItem);
+
+ vTaskResume(xHandle);
+ DMGR_PRINTF(LOG_TASKTRACE, "Resume %s", pcTaskGetTaskName(xHandle));
+
+ /* insert the empty item into free list */
+ vListInitialiseItem(pxDramMgrItem);
+ vListInsertEnd(&xDramMgrFreeList, pxDramMgrItem);
+}
+
+static void prvTaskDramManager(void *pvParameters)
+{
+ struct dramMgrQueueEvent xEvent;
+ enum dramMgrAction eAction;
+ TaskHandle_t xHandle;
+ BaseType_t xRet;
+ unsigned long long ullDiff;
+
+ UNUSED(pvParameters);
+
+ while (1) {
+ xRet = xQueueReceive(xDramMgrRxQueue, &xEvent, portMAX_DELAY);
+ if (xRet != pdPASS) {
+ PRINTF_E("[DMGR] xQueueReceive failed, %ld\n\r", xRet);
+ continue;
+ }
+
+ xHandle = xEvent.xHandle;
+ eAction = xEvent.eAction;
+
+ /*
+ * Normal FSM for DRAM Manager
+ */
+ DMGR_PRINTF(LOG_STATE, "State=%d, Action=%d", eDramMgrState,
+ eAction);
+
+ switch (eDramMgrState) {
+ case STAT_DRAM_PW_OFF:
+ switch (eAction) {
+ case ACT_DRAM_DETECT_ACCESS:
+ vDmgrPortEnDRAMUnblock();
+ xDmgrCost.ullDmgrDetectWfiSTimeStamp = get_last_wfi_s_time();
+ xDmgrCost.ullDmgrDetectWfiETimeStamp = get_last_wfi_e_time();
+
+ /* Record starting time for cost computation */
+ xDmgrCost.ullDmgrLastDetectTimeStamp = read_xgpt_stamp_ns();
+ xDmgrCost.ullDmgrDetectSlpCnt = get_sleep_cnt();
+ xDmgrCost.ullDmgrDetectWFICnt = get_wfi_cnt();
+ xDmgrCost.ullDmgrTmrCnt = 0;
+
+ prvSuspendTask(xHandle);
+ eDramMgrState = STAT_DRAM_WARM_UP;
+ prvDmgrHwTimerStart();
+ break;
+ default:
+ configASSERT(0);
+ }
+
+ break;
+ case STAT_DRAM_WARM_UP:
+ switch (eAction) {
+ case ACT_DRAM_DETECT_ACCESS:
+ prvSuspendTask(xHandle);
+ break;
+ case ACT_DRAM_POWER_ON:
+ /* Supposed there are no events following POWER_ON events,
+ * so task resuming is only done here.
+ */
+ while (listLIST_IS_EMPTY(&xDramMgrSuspendList)
+ != pdTRUE) {
+ prvResumeTask(xHandle);
+ }
+ eDramMgrState = STAT_DRAM_PW_ON;
+
+ /* Calculate the cost and record the max one */
+ xDmgrCost.ullDmgrLastPowerOnTimeStamp = read_xgpt_stamp_ns();
+ xDmgrCost.ullDmgrPowerOnSlpCnt = get_sleep_cnt();
+ xDmgrCost.ullDmgrPowerOnWFICnt = get_wfi_cnt();
+ ullDiff = xDmgrCost.ullDmgrLastPowerOnTimeStamp -
+ xDmgrCost.ullDmgrLastDetectTimeStamp;
+
+ if (ullDiff > xDmgrCost.ullDmgrMaxCost) {
+ xDmgrCost.ullDmgrMaxCost = ullDiff;
+ DMGR_PRINTF(LOG_LATENCY, "update Max Cost = %llu",
+ xDmgrCost.ullDmgrMaxCost);
+#ifdef CFG_IRQ_MONITOR_SUPPORT
+ if (ullDiff > DURATION_LIMIT_NS)
+ configASSERT(0);
+#endif
+ }
+
+ break;
+ default:
+ configASSERT(0);
+ }
+
+ break;
+ case STAT_DRAM_PW_ON:
+ configASSERT(0);
+
+ default:
+ ;
+ }
+ }
+}
+
+#endif
+
+/****************************************************************************/
+
+/*****************************************************************************
+** Hook functions are the functions that must be embedded in some places of
+** the new platform and then deliver the events to the DRAM Manager.
+*****************************************************************************/
+
+BaseType_t xDmgrHookSwitchOnDramPower(void)
+{
+ BaseType_t xRet = pdPASS;
+
+ switch (xDmgrPortAccessType()) {
+ case TYPE_NORMAL:
+#ifdef CFG_DYNAMIC_DRAM_V2
+ /* the access is located in cacheable memory */
+ DMGR_PRINTF(LOG_ONOFF, "p:notify dmgr");
+ prvDmgrEventSend((TaskHandle_t) pxCurrentTCB,
+ ACT_DRAM_DETECT_ACCESS);
+ break;
+#endif
+ case TYPE_EXCEPTION:
+ case TYPE_CRITICAL:
+#ifdef CFG_L1C_ISR_SUPPORT
+ DMGR_PRINTF(LOG_ONOFF, "e:dram on");
+ vDmgrPortEnDRAMFromISR();
+ eExceptState = STAT_DRAM_PW_ON;
+ break;
+#else
+ /* Don't allow access DRAM in Critical Section and Interrupt */
+ //configASSERT(0); let it enter exception and coredump
+#endif
+ default:
+ xRet = pdFALSE;
+ }
+
+ return xRet;
+}
+
+void vDmgrHookIdleApplication(void)
+{
+ taskENTER_CRITICAL();
+ {
+#ifdef CFG_DYNAMIC_DRAM_V2
+ if (eDramMgrState == STAT_DRAM_PW_ON) {
+ vDmgrPortDisDRAM();
+ eDramMgrState = STAT_DRAM_PW_OFF;
+ DMGR_PRINTF(LOG_ONOFF, "p:dram off");
+ }
+#endif
+
+ if (eExceptState == STAT_DRAM_PW_ON) {
+ vDmgrPortDisDRAM();
+ eExceptState = STAT_DRAM_PW_OFF;
+ DMGR_PRINTF(LOG_ONOFF, "e:dram off");
+ }
+ }
+ taskEXIT_CRITICAL();
+}
+
+void vDmgrHookDVFSDramOn(void)
+{
+ vDmgrPortEnRegion();
+}
+
+void vDmgrHookDVFSDramOff(void)
+{
+ vDmgrPortDisRegion();
+}
+
+BaseType_t xDmgrHookInit(void)
+{
+ BaseType_t xRet = pdPASS;
+
+#ifdef CFG_DYNAMIC_DRAM_V2
+ uint32_t i;
+ struct timer_device *pxDev;
+
+ xDramMgrRxQueue =
+ xQueueCreate(MAX_DMGR_QUEUE_EVENT,
+ sizeof (struct dramMgrQueueEvent));
+ vListInitialise(&xDramMgrSuspendList);
+ vListInitialise(&xDramMgrFreeList);
+ /* insert all list items into free list */
+
+ for (i = 0; i < MAX_DMGR_LIST_ITEM; i++) {
+ vListInitialiseItem(&dramMgrItemPool[i]);
+ vListInsertEnd(&xDramMgrFreeList, &dramMgrItemPool[i]);
+ }
+
+ xRet =
+ xTaskCreate(prvTaskDramManager, "DMgr", configMINIMAL_STACK_SIZE,
+ NULL, PRI_DMGR, NULL);
+
+ /* timer for polling the dram ack state by every 1ms */
+ pxDev = id_to_dev(DMGR_TIMER);
+ intc_irq_request(&pxDev->irq, prvDmgrPollingAck, (void *) "DMGR_Timer");
+ prvDmgrHwTimerStop();
+ eDramMgrState = STAT_DRAM_PW_OFF;
+#endif
+
+ eExceptState = STAT_DRAM_PW_OFF;
+ vDmgrPortDisRegion();
+
+ return xRet;
+}
+
+/****************************************************************************/
diff --git a/src/tinysys/medmcu/drivers/common/cache/src/dmgr_port.c b/src/tinysys/medmcu/drivers/common/cache/src/dmgr_port.c
new file mode 100644
index 0000000..66caaca
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/cache/src/dmgr_port.c
@@ -0,0 +1,159 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek Software")
+ * have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+ * applicable license agreements with MediaTek Inc.
+ */
+
+#include <FreeRTOS.h>
+#include <dmgr_api.h>
+#include <dmgr.h>
+#include <peripheral.h>
+#include <irq.h>
+#include <encoding.h>
+#include <mt_printf.h>
+#include <dvfs.h>
+
+#define e_GET_MCAUSE(x) __asm volatile("csrr %0, mcause":"=r"(x)::)
+#define e_GET_MEPC(x) __asm volatile("csrr %0, mepc":"=r"(x)::)
+
+#ifdef GCC_7_2
+#define e_GET_MTVAL(x) __asm volatile("csrr %0, mbadaddr":"=r"(x)::)
+#else
+#define e_GET_MTVAL(x) __asm volatile("csrr %0, mtval":"=r"(x)::)
+#endif /* GCC_7_2 */
+
+/*****************************************************************************
+ * Setting for Platform-Specific DRAM access detect, like MPU
+ ****************************************************************************/
+
+inline void vDmgrPortEnRegion(void)
+{
+#ifdef CFG_MPU_SUPPORT
+#if CFG_L1C_DRAM_SIZE_0
+ mpu_region_enable(MPU_REGION_DRAM_RO);
+ mpu_region_enable(MPU_REGION_DRAM_RW);
+#endif
+#if CFG_L1C_DRAM_SIZE_1
+ mpu_region_enable(MPU_REGION_DRAM);
+#endif
+#endif
+}
+
+inline void vDmgrPortDisRegion(void)
+{
+#ifdef CFG_MPU_SUPPORT
+ mrv_dcache_flush_all();
+#if CFG_L1C_DRAM_SIZE_0
+ mpu_region_disable(MPU_REGION_DRAM_RO);
+ mpu_region_disable(MPU_REGION_DRAM_RW);
+#endif
+#if CFG_L1C_DRAM_SIZE_1
+ mpu_region_disable(MPU_REGION_DRAM);
+#endif
+#endif
+}
+
+/*****************************************************************************
+ * Logic to tell if the execution instruction or load/store data is in DRAM
+ ****************************************************************************/
+
+DramMgrAccssType_t xDmgrPortAccessType(void)
+{
+ uint32_t ulCause, ulMMFAR, ulPC;
+
+ e_GET_MCAUSE(ulCause);
+ e_GET_MTVAL(ulMMFAR);
+ e_GET_MEPC(ulPC);
+
+ DMGR_PRINTF(LOG_TRAP, "mcause=0x%08x, mepc=0x%08x, vtval=0x%08x",
+ (unsigned int) ulCause, (unsigned int) ulPC,
+ (unsigned int) ulMMFAR);
+
+ if ((CFG_L1C_DRAM_ADDR <= ulPC &&
+ ulPC < CFG_L1C_DRAM_ADDR + CFG_L1C_DRAM_SIZE) ||
+ (CFG_L1C_DRAM_ADDR <= ulMMFAR &&
+ ulMMFAR < CFG_L1C_DRAM_ADDR + CFG_L1C_DRAM_SIZE)) {
+ /* if ISR execution locates in the range of cacheable memory */
+ if (is_in_isr()) {
+ DMGR_WARN("Access DRAM in ISR, PC=0x%x, MMFAR=0x%08x!!!",
+ (unsigned int) ulPC, (unsigned int) ulMMFAR);
+ return TYPE_EXCEPTION;
+ }
+
+ /* if dram access is in critical secton */
+ if (xGetCriticalNesting() > 0) {
+ DMGR_WARN
+ ("Access DRAM in CRITICAL SECTION, PC=0x%x, MMFAR=0x%08x!!!",
+ (unsigned int) ulPC, (unsigned int) ulMMFAR);
+ return TYPE_CRITICAL;
+ }
+
+ /* if instruction accessed locates in the range of cacheable memory */
+ if (ulCause == CAUSE_FAULT_FETCH) {
+ return TYPE_NORMAL;
+ }
+ /* if data accessed locates in the range of cacheable memory */
+ if (ulCause == CAUSE_FAULT_LOAD || ulCause == CAUSE_FAULT_STORE) {
+ return TYPE_NORMAL;
+ }
+
+ }
+ return TYPE_INVALID;
+}
+
+/*****************************************************************************
+ * Sync operation porting for DRAM On/Off
+ ****************************************************************************/
+
+inline void vDmgrPortEnDRAMFromISR(void)
+{
+ dvfs_enable_DRAM_resource_from_isr(DRAM_MANAGER_MEM_ID);
+}
+
+inline void vDmgrPortDisDRAM(void)
+{
+ dvfs_disable_DRAM_resource(DRAM_MANAGER_MEM_ID);
+}
+
+/*****************************************************************************
+ * Async operation porting for DRAM On/Off
+ ****************************************************************************/
+
+inline int32_t vDmgrPortGetDramAckFromISR(void)
+{
+ return get_dram_ack_from_isr_for_dmgr();
+}
+
+inline void vDmgrPortEnDRAMUnblock(void)
+{
+ enable_dram_resource_for_dmgr(DRAM_MANAGER_MEM_ID);
+}
diff --git a/src/tinysys/medmcu/drivers/common/cache/test/cache_unit_test.c b/src/tinysys/medmcu/drivers/common/cache/test/cache_unit_test.c
new file mode 100644
index 0000000..f8bda4a
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/cache/test/cache_unit_test.c
@@ -0,0 +1,245 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek Software")
+ * have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+ * applicable license agreements with MediaTek Inc.
+ */
+
+#include <FreeRTOS.h>
+#include <task.h>
+#include <tinysys_config.h>
+#include <mt_printf.h>
+#include <peripheral.h>
+#ifdef CFG_XGPT_SUPPORT
+#include <interrupt.h>
+#include <xgpt.h>
+#endif
+
+#define TEST_PRINTF PRINTF_E
+#define INT_TIMER TMR5
+#define UNUSED(x) (void)(x)
+
+#define DRAM_REGION_RO __attribute__ ((section (".dram_region_ro")))
+#define DRAM_REGION_RW __attribute__ ((section (".dram_region_rw")))
+#define DRAM_REGION_BSS __attribute__ ((section (".dram_region_bss")))
+#define DRAM_REGION_VARIABLE __attribute__ ((section (".dram_region_variable")))
+#define DRAM_REGION_FUNCTION __attribute__ ((section (".dram_region_func")))
+
+DRAM_REGION_VARIABLE int dram_addr_a[256];
+DRAM_REGION_VARIABLE int dram_addr_b[128];
+DRAM_REGION_VARIABLE int dram_addr_c[64];
+volatile int sram_var;
+
+static void task1_s_d(void *pvParameters)
+{
+ unsigned int *dram_addr = (unsigned int *) dram_addr_a;
+ portTickType xLastExecutionTime, xDelayTime;
+ unsigned int task1_param;
+
+ UNUSED(pvParameters);
+ xLastExecutionTime = xTaskGetTickCount();
+ xDelayTime = ((portTickType) 223 / portTICK_RATE_MS);
+
+ do {
+ task1_param = 10000;
+ TEST_PRINTF("...> task 1 works\n");
+
+ while (task1_param) {
+ *dram_addr = 0xaa5555aa;
+ task1_param--;
+ }
+ vTaskDelayUntil(&xLastExecutionTime, xDelayTime);
+ } while (1);
+}
+
+DRAM_REGION_FUNCTION static void task2_d_d(void *pvParameters)
+{
+ unsigned int *dram_addr = (unsigned int *) dram_addr_b;
+ portTickType xLastExecutionTime, xDelayTime;
+ unsigned int task2_param;
+
+ UNUSED(pvParameters);
+ xLastExecutionTime = xTaskGetTickCount();
+ xDelayTime = ((portTickType) 101 / portTICK_RATE_MS);
+
+ do {
+ task2_param = 20000;
+ TEST_PRINTF("...> task 2 works\n");
+
+ while (task2_param) {
+ *dram_addr = 0xaa5555aa;
+ task2_param--;
+ }
+ vTaskDelayUntil(&xLastExecutionTime, xDelayTime);
+ } while (1);
+}
+
+DRAM_REGION_FUNCTION static void task3_d_s(void *pvParameters)
+{
+ unsigned int sram;
+ unsigned int *sram_addr = (unsigned int *) &sram;
+ portTickType xLastExecutionTime, xDelayTime;
+ unsigned int task3_param;
+
+ UNUSED(pvParameters);
+ xLastExecutionTime = xTaskGetTickCount();
+ xDelayTime = ((portTickType) 53 / portTICK_RATE_MS);
+
+ do {
+ task3_param = 10000;
+ TEST_PRINTF("...> task 3 works\n");
+
+ while (task3_param) {
+ *sram_addr = 0xaa5555aa;
+ task3_param--;
+ }
+
+ vTaskDelayUntil(&xLastExecutionTime, xDelayTime);
+ } while (1);
+}
+
+static void task4_s_d(void *pvParameters)
+{
+ unsigned int *dram_addr = (unsigned int *) dram_addr_c;
+ portTickType xLastExecutionTime, xDelayTime;
+ unsigned int task4_param;
+
+ UNUSED(pvParameters);
+ xLastExecutionTime = xTaskGetTickCount();
+ xDelayTime = ((portTickType) 167 / portTICK_RATE_MS);
+
+ *dram_addr = 0xaa5555aa;
+
+ do {
+ task4_param = 10000;
+ TEST_PRINTF("...> task 4 works\n");
+
+ while (task4_param) {
+ sram_var = *dram_addr;
+ task4_param--;
+ }
+ vTaskDelayUntil(&xLastExecutionTime, xDelayTime);
+ } while (1);
+}
+
+DRAM_REGION_FUNCTION static void task5_d_d(void *pvParameters)
+{
+ unsigned int *dram_addr = (unsigned int *) dram_addr_a;
+ portTickType xLastExecutionTime, xDelayTime;
+ unsigned int task5_param;
+
+ UNUSED(pvParameters);
+ xLastExecutionTime = xTaskGetTickCount();
+ xDelayTime = ((portTickType) 313 / portTICK_RATE_MS);
+
+ do {
+ task5_param = 20000;
+ TEST_PRINTF("...> task 5 works\n");
+
+ while (task5_param) {
+ *dram_addr = 0xaa5555aa;
+ task5_param--;
+ }
+ vTaskDelayUntil(&xLastExecutionTime, xDelayTime);
+ } while (1);
+}
+
+DRAM_REGION_FUNCTION static void task6_d_s(void *pvParameters)
+{
+ unsigned int sram;
+ unsigned int *sram_addr = (unsigned int *) &sram;
+ portTickType xLastExecutionTime, xDelayTime;
+ unsigned int task6_param;
+
+ UNUSED(pvParameters);
+ xLastExecutionTime = xTaskGetTickCount();
+ xDelayTime = ((portTickType) 71 / portTICK_RATE_MS);
+
+ do {
+ task6_param = 10000;
+ TEST_PRINTF("...> task 6 works\n");
+
+ while (task6_param) {
+ *sram_addr = 0xaa5555aa;
+ task6_param--;
+ }
+
+ vTaskDelayUntil(&xLastExecutionTime, xDelayTime);
+ } while (1);
+}
+
+static void prvTestTimerStart(void)
+{
+ struct timer_device *pxDev = id_to_dev(INT_TIMER);
+ unsigned int ulBaseAddr = pxDev->base_addr;
+
+ DRV_WriteReg32(ulBaseAddr + TIMER_RST_VAL, TIME_TO_TICK_MS(97));
+ DRV_SetReg32(ulBaseAddr + TIMER_IRQ_CTRL_REG, TIMER_ENABLE);
+ /* select clock source to clk_32k and enable timer */
+ DRV_SetReg32(ulBaseAddr + TIMER_EN,
+ (TIMER_CLK_SRC_CLK_32K << TIMER_CLK_SRC_SHIFT) |
+ TIMER_IRQ_ENABLE);
+}
+
+DRAM_REGION_FUNCTION static unsigned int prvTestTimerIntTask(void *pvParameters)
+{
+ struct timer_device *pxDev = id_to_dev(INT_TIMER);
+ unsigned int ulBaseAddr = pxDev->base_addr;
+
+ UNUSED(pvParameters);
+ DRV_SetReg32(ulBaseAddr + TIMER_IRQ_CTRL_REG, TIMER_IRQ_CLEAR);
+ mbi();
+ TEST_PRINTF("...> timer interrupt\n");
+
+ return 0;
+}
+
+void dmgr_test(void)
+{
+ struct timer_device *pxDev;
+
+ xTaskCreate(task1_s_d, "task1", configMINIMAL_STACK_SIZE, NULL,
+ PRI_TEST, NULL);
+ xTaskCreate(task2_d_d, "task2", configMINIMAL_STACK_SIZE, NULL,
+ PRI_TEST, NULL);
+ xTaskCreate(task3_d_s, "task3", configMINIMAL_STACK_SIZE, NULL,
+ PRI_TEST, NULL);
+ xTaskCreate(task4_s_d, "task4", configMINIMAL_STACK_SIZE, NULL,
+ PRI_TEST, NULL);
+ xTaskCreate(task5_d_d, "task5", configMINIMAL_STACK_SIZE, NULL,
+ PRI_TEST, NULL);
+ xTaskCreate(task6_d_s, "task6", configMINIMAL_STACK_SIZE, NULL,
+ PRI_TEST, NULL);
+
+ pxDev = id_to_dev(INT_TIMER);
+ intc_irq_request(&pxDev->irq, prvTestTimerIntTask, "TST_Timer");
+ prvTestTimerStart();
+}
diff --git a/src/tinysys/medmcu/drivers/common/dma/dma_api.c b/src/tinysys/medmcu/drivers/common/dma/dma_api.c
new file mode 100644
index 0000000..7d1e545
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/dma/dma_api.c
@@ -0,0 +1,253 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2015. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include <string.h>
+#include <driver_api.h>
+#include <interrupt.h>
+#include <dma_api.h>
+#ifdef CFG_VCORE_DVFS_SUPPORT
+#include <dvfs.h>
+#endif
+#include "irq.h"
+#ifdef CFG_COMMON_WAKELOCK_SUPPORT
+#include <wakelock.h>
+#endif
+#ifdef CFG_XGPT_SUPPORT
+#include <xgpt.h>
+#endif
+
+#include "mt_printf.h"
+
+#define DMA_DEBUG 0
+#define DMA_LARGE_DRAM 0
+
+#if(DMA_DEBUG == 1)
+#define dbgmsg PRINTF_D
+#else
+#define dbgmsg(...)
+#endif
+
+#if DMA_PROFILING
+volatile unsigned int *ITM_CONTROL = (unsigned int *) 0xE0000E80;
+volatile unsigned int *DWT_CONTROL = (unsigned int *) 0xE0001000;
+volatile unsigned int *DWT_CYCCNT = (unsigned int *) 0xE0001004;
+volatile unsigned int *DEMCR = (unsigned int *) 0xE000EDFC;
+
+#define CPU_RESET_CYCLECOUNTER() \
+ do { \
+ *DEMCR = *DEMCR | 0x01000000; \
+ *DWT_CYCCNT = 0; \
+ *DWT_CONTROL = *DWT_CONTROL | 1 ; \
+ } while(0)
+unsigned int start_time;
+unsigned int end_time;
+#endif
+
+#if DMA_TRACE_DEBUG
+#define DMA_TRACE_SECTION __attribute__ ((section (".sync")))
+struct dma_trace_t {
+ unsigned int last_src;
+ unsigned int last_dst;
+ unsigned int last_len;
+ unsigned long long last_timestamp;
+};
+struct dma_trace_t DMA_TRACE_SECTION dma_trace[2] = {{0,0,0,0},{0,0,0,0}};
+#endif
+
+extern void *__sync_start;
+extern struct dma_channel_t dma_channel[NR_GDMA_CHANNEL];
+
+#if DMA_KEEP_AWAKE
+wakelock_t scp_dma_wakelock;
+#endif
+
+typedef struct {
+ uint32_t ap_addr;
+ uint32_t scp_addr;
+} scp_addr_map_t;
+
+static scp_addr_map_t scp_addr_map[] = {
+ {.ap_addr = 0x60000000,.scp_addr = 0x10000000,},
+ {.ap_addr = 0x70000000,.scp_addr = 0x20000000,},
+ {.ap_addr = 0x00000000,.scp_addr = 0x50000000,},
+ {.ap_addr = 0x10000000,.scp_addr = 0x60000000,},
+ {.ap_addr = 0x80000000,.scp_addr = 0x90000000,},
+ {.ap_addr = 0x90000000,.scp_addr = 0xA0000000,},
+ {.ap_addr = 0x20000000,.scp_addr = 0xD0000000,},
+ {.ap_addr = 0x30000000,.scp_addr = 0xE0000000,},
+ {.ap_addr = 0x50000000,.scp_addr = 0xF0000000,},
+};
+
+uint32_t ap_to_scp(uint32_t ap_addr)
+{
+ uint32_t i;
+ uint32_t num = sizeof (scp_addr_map) / sizeof (scp_addr_map_t);
+
+ for (i = 0; i < num; i++)
+ if (scp_addr_map[i].ap_addr == (0xf0000000 & ap_addr))
+ return (scp_addr_map[i].scp_addr |
+ (0x0fffffff & ap_addr));
+
+ PRINTF_E("err ap_addr:0x%x\n", ap_addr);
+
+ return 0;
+}
+
+uint32_t scp_to_ap(uint32_t scp_addr)
+{
+ uint32_t i;
+ uint32_t num = sizeof (scp_addr_map) / sizeof (scp_addr_map_t);
+
+ for (i = 0; i < num; i++)
+ if (scp_addr_map[i].scp_addr == (0xf0000000 & scp_addr))
+ return (scp_addr_map[i].ap_addr |
+ (0x0fffffff & scp_addr));
+
+ PRINTF_E("err scp_addr:0x%x\n", scp_addr);
+
+ return 0;
+}
+
+/*
+ * In order to send the physical address for dma or other masters,
+ * address view in core1 needs to be remapped with a hardware offset.
+ */
+uint32_t scp_get_phy_addr(uint32_t addr)
+{
+ if (mrv_read_csr(CSR_MHARTID) == 1) {
+ if (addr > DRV_Reg32(R_L2TCM_OFFSET_RANGE_0_LOW)
+ && addr < DRV_Reg32(R_L2TCM_OFFSET_RANGE_0_HIGH))
+ addr += DRV_Reg32(R_L2TCM_OFFSET_ADD);
+ }
+
+ return addr;
+}
+
+#if DMA_KEEP_AWAKE
+void dma_wake_lock_init(void)
+{
+ wake_lock_init(&scp_dma_wakelock, "dmawk");
+}
+
+void dma_wake_lock(void)
+{
+ if (!is_in_isr())
+ wake_lock(&scp_dma_wakelock);
+ else
+ wake_lock_FromISR(&scp_dma_wakelock);
+}
+
+void dma_wake_unlock(void)
+{
+ uint32_t scp_sleep_flag;
+ int32_t channel;
+
+ /*scp_sleep_flag :0 release lock, 1:can not release lock */
+ scp_sleep_flag = 0;
+ for (channel = NR_GDMA_CHANNEL - 1; channel >= 0; channel--)
+ if (dma_channel[channel].in_use == 1)
+ scp_sleep_flag = 1;
+
+ if (scp_sleep_flag == 0) {
+ if (!is_in_isr())
+ wake_unlock(&scp_dma_wakelock);
+ else
+ wake_unlock_FromISR(&scp_dma_wakelock);
+ }
+}
+#endif
+
+#if DMA_TRACE_DEBUG
+void scp_dma_tracing(uint32_t dst, uint32_t src, uint32_t len);
+void scp_dma_tracing(uint32_t dst, uint32_t src, uint32_t len)
+{
+ int core_id = mrv_read_csr(CSR_MHARTID);
+
+ dma_trace[core_id].last_dst = dst;
+ dma_trace[core_id].last_src = src;
+ dma_trace[core_id].last_len = len;
+#ifdef CFG_XGPT_SUPPORT
+ dma_trace[core_id].last_timestamp = read_xgpt_stamp_ns();
+#endif
+}
+#endif
+
+void scp_dma_dstCheck(uint32_t dst);
+void scp_dma_dstCheck(uint32_t dst)
+{
+ if (dst < (uint32_t)(&__sync_start))
+ configASSERT(0);
+}
+
+DMA_RESULT scp_dma_transaction(uint32_t dst_addr, uint32_t src_addr,
+ uint32_t len, int8_t scp_dma_id,
+ int32_t ch)
+{
+ DMA_RESULT ret = 0;
+
+ dst_addr = scp_get_phy_addr(dst_addr);
+ src_addr = scp_get_phy_addr(src_addr);
+#if DMA_TRACE_DEBUG
+ scp_dma_tracing(dst_addr, src_addr, len);
+#endif
+ scp_dma_dstCheck(dst_addr);
+ ret =
+ dma_transaction(dst_addr, src_addr, len, scp_dma_id, ch, NULL, SYNC);
+
+ return ret;
+}
+
+DMA_RESULT scp_dma_transaction_dram(uint32_t dst_addr, uint32_t src_addr,
+ uint32_t len, int8_t scp_dma_id,
+ int32_t ch)
+{
+ DMA_RESULT ret;
+
+#ifdef CFG_VCORE_DVFS_SUPPORT
+ dvfs_enable_DRAM_resource(DMA_MEM_ID);
+#endif
+ dst_addr = scp_get_phy_addr(dst_addr);
+ src_addr = scp_get_phy_addr(src_addr);
+#if DMA_TRACE_DEBUG
+ scp_dma_tracing(dst_addr, src_addr, len);
+#endif
+ scp_dma_dstCheck(dst_addr);
+ ret =
+ dma_transaction(dst_addr, src_addr, len, scp_dma_id, ch, NULL, SYNC);
+#ifdef CFG_VCORE_DVFS_SUPPORT
+ dvfs_disable_DRAM_resource(DMA_MEM_ID);
+#endif
+ return ret;
+}
+
diff --git a/src/tinysys/medmcu/drivers/common/dma/inc/dma_api.h b/src/tinysys/medmcu/drivers/common/dma/inc/dma_api.h
new file mode 100644
index 0000000..ada53fd
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/dma/inc/dma_api.h
@@ -0,0 +1,50 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2015. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ */
+
+#ifndef _DMA_API_H_
+#define _DMA_API_H_
+
+#include <mt_dma.h>
+#include <dma.h>
+
+DMA_RESULT scp_dma_transaction_dram(uint32_t dst_addr, uint32_t src_addr,
+ uint32_t len, int8_t scp_dma_id,
+ int32_t ch);
+DMA_RESULT scp_dma_transaction(uint32_t dst_addr, uint32_t src_addr,
+ uint32_t len, int8_t scp_dma_id,
+ int32_t ch);
+
+uint32_t ap_to_scp(uint32_t ap);
+uint32_t scp_to_ap(uint32_t scp);
+uint32_t scp_get_phy_addr(uint32_t addr);
+void scp_remap_init(void);
+
+#endif /* !_DMA_API_H_ */
diff --git a/src/tinysys/medmcu/drivers/common/dvfs/inc/dvfs_common.h b/src/tinysys/medmcu/drivers/common/dvfs/inc/dvfs_common.h
new file mode 100644
index 0000000..728d880
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/dvfs/inc/dvfs_common.h
@@ -0,0 +1,115 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2015. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ */
+
+#ifndef _DVFS_COMMON_
+#define _DVFS_COMMON_
+
+#ifdef CFG_DMA_SUPPORT
+#include <mt_dma.h>
+#endif
+#include <sleep.h>
+#ifdef CFG_XGPT_SUPPORT
+#include <xgpt.h>
+#endif
+
+/***********************************************************************************
+** Definitions
+************************************************************************************/
+
+/* DVFS Status */
+#define DVFS_STATUS_OK 0
+#define DVFS_STATUS_BUSY -1
+#define DVFS_REQUEST_SAME_CLOCK -2
+#define DVFS_STATUS_ERR -3
+#define DVFS_STATUS_TIMEOUT -4
+#define DVFS_CLK_ERROR -5
+#define DVFS_STATUS_CMD_FIX -6
+#define DVFS_STATUS_CMD_LIMITED -7
+#define DVFS_STATUS_CMD_DISABLE -8
+
+#define SCP_IDLE_MODE 0
+#define SCP_SLEEP_MODE 1
+
+#define SCP_ENABLE 1
+#define SCP_DISABLE 0
+
+#define NEED_WAIT 1
+#define NO_WAIT 0
+
+/***********************************************************************************
+** Enum for Time Profiling
+************************************************************************************/
+enum dvfs_profile_mode {
+ SLP_TMR_M = 0,
+ WK_TMR_M = 1,
+ RTOS_TMR_M = 2,
+ WAIT_TMR_M= 3,
+ UPDATE_TMR_M = 4,
+ BLOCK_TMR_M = 5,
+ DVFS_TMR_M = 6,
+ WFI_TMR_M = 7,
+ DRAM_TMR_M = 8,
+ PROFILE_MODE_NUM = 9,
+};
+
+enum dvfs_profile_type {
+ TMR_START_T = 0,
+ TMR_END_T,
+ TMR_DURATION_T,
+ TMR_RESET_T,
+ TMR_RESTART_T,
+ PROFILE_TYPE_NUM,
+};
+
+/*****************************************
+* ADB CMD Control APIs
+****************************************/
+void dvfs_debug_set(int id, void *data, unsigned int len);
+
+/*****************************************
+ * AP/INFRA Resource APIs
+ ****************************************/
+#ifdef CFG_DMA_SUPPORT
+void enable_AP_resource(scp_reserve_mem_id_t dma_id);
+void disable_AP_resource(scp_reserve_mem_id_t dma_id);
+void enable_infra(scp_reserve_mem_id_t dma_id, uint32_t wait_ack);
+void disable_infra(scp_reserve_mem_id_t dma_id);
+#endif
+
+/*****************************************
+ * Time Profiling APIs
+ ****************************************/
+void dvfs_time_profiling(enum dvfs_profile_mode mode, enum dvfs_profile_type type);
+uint64_t dvfs_get_time_duarion(enum dvfs_profile_mode mode);
+void dvfs_dump_time_profiling(enum dvfs_profile_mode mode);
+uint64_t get_last_wfi_s_time(void);
+uint64_t get_last_wfi_e_time(void);
+#endif /* _DVFS_COMMON_ */
diff --git a/src/tinysys/medmcu/drivers/common/dvfs/src/dvfs_common.c b/src/tinysys/medmcu/drivers/common/dvfs/src/dvfs_common.c
new file mode 100644
index 0000000..e36aa9a
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/dvfs/src/dvfs_common.c
@@ -0,0 +1,247 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2015. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ */
+
+#include <FreeRTOS.h>
+#include <task.h>
+#include <stdio.h>
+#include <driver_api.h>
+#include <interrupt.h>
+#include <mtk_sem.h>
+#include <mt_printf.h>
+#ifdef CFG_XGPT_SUPPORT
+#include <xgpt.h>
+#endif
+#include <dvfs.h>
+#include <dvfs_common.h>
+
+#define DVFS_DEBUG 0
+
+#if DVFS_DEBUG
+#define DVFSLOG(fmt, arg...) \
+ do { \
+ PRINTF_D(DVFSTAG fmt, ##arg); \
+ } while (0)
+#else
+#define DVFSLOG(...)
+#endif
+
+#if DVFS_DEBUG
+#define DVFSFUC(fmt, arg...) \
+ do { \
+ PRINTF_D(DVFSTAG "%s("fmt")\n", __func__, ##arg); \
+ } while (0)
+#else
+#define DVFSFUC(...)
+#endif
+
+#if DVFS_DEBUG
+#define DVFSDBG(fmt, arg...) \
+ do { \
+ PRINTF_W(DVFSTAG fmt, ##arg); \
+ } while (0)
+#else
+#define DVFSDBG(fmt, arg...)
+#endif
+
+#ifdef CFG_XGPT_SUPPORT
+static volatile uint64_t dvfs_profile_time[PROFILE_MODE_NUM][PROFILE_TYPE_NUM];
+
+static char dvfs_profile_name[PROFILE_MODE_NUM][10] = {
+ "SLEEP",
+ "WAKE-UP",
+ "RTOS",
+ "WAIT-ISR",
+ "UPDATE",
+ "BLOCK",
+ "DVFS",
+ "WFI",
+ "DRAM",
+};
+#endif
+
+extern int g_scp_dvfs_debug;
+
+/*****************************************
+* ADB CMD Control APIs
+****************************************/
+void dvfs_debug_set(int id, void *data, unsigned int len)
+{
+ (void)id;
+ (void)len;
+ uint8_t *msg = (uint8_t *) data;
+
+ g_scp_dvfs_debug = *msg;
+ DVFSLOG("set g_scp_dvfs_debug = %d\n", *msg);
+}
+
+/*****************************************
+ * AP/INFRA Resource APIs
+ ****************************************/
+#ifdef CFG_DMA_SUPPORT
+void enable_clk_bus(scp_reserve_mem_id_t dma_id)
+{
+ DVFSFUC("%d", dma_id);
+ taskENTER_CRITICAL();
+ enable_infra(dma_id, NEED_WAIT);
+ taskEXIT_CRITICAL();
+}
+
+void disable_clk_bus(scp_reserve_mem_id_t dma_id)
+{
+ DVFSFUC("%d", dma_id);
+ taskENTER_CRITICAL();
+ disable_infra(dma_id);
+ taskEXIT_CRITICAL();
+}
+
+void enable_clk_bus_from_isr(scp_reserve_mem_id_t dma_id)
+{
+ DVFSFUC("%d", dma_id);
+ enable_infra(dma_id, NEED_WAIT);
+}
+
+void disable_clk_bus_from_isr(scp_reserve_mem_id_t dma_id)
+{
+ DVFSFUC("%d", dma_id);
+ disable_infra(dma_id);
+}
+
+void dvfs_disable_DRAM_resource(scp_reserve_mem_id_t dma_id)
+{
+ DVFSFUC("%d", dma_id);
+ taskENTER_CRITICAL();
+ disable_AP_resource(dma_id);
+ disable_infra(dma_id);
+ taskEXIT_CRITICAL();
+}
+
+/*****************************************
+ * Time Profiling APIs
+ ****************************************/
+static bool __dvfs_chk_profile_cond(enum dvfs_profile_mode mode,
+ enum dvfs_profile_type type)
+{
+ if (mode >= PROFILE_MODE_NUM || type >= PROFILE_TYPE_NUM)
+ return false;
+
+#if !(SLEEP_TIMER_PROFILING)
+ if (mode == SLP_TMR_M || mode == WK_TMR_M || mode == RTOS_TMR_M)
+ return false;
+#endif
+
+#if !(DVFS_TIMER_PROFILING)
+ if (mode == DVFS_TMR_M)
+ return false;
+#endif
+
+#if !(WFI_TIMER_PROFILING)
+ if (mode == WFI_TMR_M)
+ return false;
+#endif
+
+#if !(DRAM_TIMER_PROFILING)
+ if (mode == DRAM_TMR_M)
+ return false;
+#endif
+ return true;
+}
+
+void dvfs_time_profiling(enum dvfs_profile_mode mode,
+ enum dvfs_profile_type type)
+{
+#ifdef CFG_XGPT_SUPPORT
+ uint64_t t1, t2;
+
+ if (!__dvfs_chk_profile_cond(mode, type))
+ return;
+
+ switch (type) {
+ case TMR_START_T:
+ case TMR_END_T:
+ dvfs_profile_time[mode][type] = read_xgpt_stamp_ns();
+ break;
+ case TMR_DURATION_T:
+ t2 = dvfs_profile_time[mode][TMR_END_T];
+ t1 = dvfs_profile_time[mode][TMR_START_T];
+ dvfs_profile_time[mode][type] = (t2 -t1) / 1000;
+ break;
+ case TMR_RESET_T:
+ dvfs_profile_time[mode][type] = 0;
+ break;
+ case TMR_RESTART_T:
+ dvfs_profile_time[mode][TMR_START_T] =
+ dvfs_profile_time[mode][TMR_END_T];
+ break;
+ default:
+ PRINTF_W("this time profiling type not support.\n");
+ break;
+ }
+#endif
+}
+
+uint64_t dvfs_get_time_duarion(enum dvfs_profile_mode mode)
+{
+#ifdef CFG_XGPT_SUPPORT
+ if (__dvfs_chk_profile_cond(mode, TMR_DURATION_T)) {
+ dvfs_time_profiling(mode, TMR_DURATION_T);
+
+ return dvfs_profile_time[mode][TMR_DURATION_T];
+ }
+#endif
+ return 0;
+}
+
+void dvfs_dump_time_profiling(enum dvfs_profile_mode mode)
+{
+#ifdef CFG_XGPT_SUPPORT
+ if (!__dvfs_chk_profile_cond(mode, TMR_DURATION_T))
+ return;
+
+ dvfs_time_profiling(mode, TMR_DURATION_T);
+
+ PRINTF_E("%s sw time: %llu(tick) => %llu(tick) = %lluus\n",
+ dvfs_profile_name[mode],
+ dvfs_profile_time[mode][TMR_START_T],
+ dvfs_profile_time[mode][TMR_END_T],
+ dvfs_profile_time[mode][TMR_DURATION_T]);
+#endif
+}
+#endif
+
+uint64_t get_last_wfi_s_time(void)
+{
+ return dvfs_profile_time[WFI_TMR_M][TMR_START_T];
+}
+
+uint64_t get_last_wfi_e_time(void)
+{
+ return dvfs_profile_time[WFI_TMR_M][TMR_END_T];
+}
diff --git a/src/tinysys/medmcu/drivers/common/err_info/scp_err_info.c b/src/tinysys/medmcu/drivers/common/err_info/scp_err_info.c
new file mode 100644
index 0000000..ade041a
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/err_info/scp_err_info.c
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ */
+
+
+/******************************************************************************
+******************************************************************************/
+#include "scp_err_info.h"
+#include "encoding.h"
+#include <ipi.h>
+#include "ipi_id.h"
+#include "mbox_pin.h"
+
+
+/******************************************************************************
+* Note that this function cannot be called in the ISR context.
+******************************************************************************/
+int scp_send_err_to_ap(error_info *info)
+{
+ int ret;
+
+ if (!info)
+ return IPI_NO_MEMORY;
+
+ /* Ensure the context[] is terminated by the NULL character. */
+ info->context[ERR_MAX_CONTEXT_LEN - 1] = '\0';
+
+ if (mrv_read_csr(CSR_MHARTID) == 0)
+ ret = ipi_send(IPI_OUT_SCP_ERROR_INFO_0, info,
+ PIN_OUT_SIZE_SCP_ERROR_INFO_0, 0);
+ else
+ ret = ipi_send(IPI_OUT_SCP_ERROR_INFO_1, info,
+ PIN_OUT_SIZE_SCP_ERROR_INFO_1, 0);
+
+ return ret;
+}
+
+
diff --git a/src/tinysys/medmcu/drivers/common/err_info/scp_err_info.h b/src/tinysys/medmcu/drivers/common/err_info/scp_err_info.h
new file mode 100644
index 0000000..be0b552
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/err_info/scp_err_info.h
@@ -0,0 +1,103 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ */
+
+
+#ifndef _SCP_ERR_INFO_H_
+#define _SCP_ERR_INFO_H_
+
+
+/******************************************************************************
+******************************************************************************/
+#include <stdint.h> // for uint32_t
+
+
+/******************************************************************************
+* The following definitions are used in error_info::case_id.
+******************************************************************************/
+typedef enum err_case_id_t {
+ ERR_CASE_ACC_GYR_INIT = 926006001,
+ ERR_CASE_ACC_INIT = 926006002,
+ ERR_CASE_GYR_INIT = 926006003,
+ ERR_CASE_MAG_INIT = 926006004,
+ ERR_CASE_ALS_PS_INIT = 926006005,
+ ERR_CASE_ALS_INIT = 926006006,
+ ERR_CASE_PS_INIT = 926006007,
+ ERR_CASE_BARO_INIT = 926006008,
+ ERR_CASE_I2C = 926006009,
+ ERR_CASE_SPI = 926006010,
+ ERR_CASE_DEV_CHECK = 926006011,
+ ERR_CASE_UNKNOWN = 0xffffffff
+} err_case_id_t;
+
+
+/******************************************************************************
+* The following definitions are used in error_info::sensor_id.
+******************************************************************************/
+typedef enum err_sensor_id_t {
+ ERR_SENSOR_ACC_GYR = 0x00000001,
+ ERR_SENSOR_ACC = 0x00000002,
+ ERR_SENSOR_GYR = 0x00000003,
+ ERR_SENSOR_MAG = 0x00000004,
+ ERR_SENSOR_ALS_PS = 0x00000005,
+ ERR_SENSOR_ALS = 0x00000006,
+ ERR_SENSOR_PS = 0x00000007,
+ ERR_SENSOR_BARO = 0x00000008,
+ ERR_SENSOR_I2C = 0x00000009,
+ ERR_SENSOR_SPI = 0x0000000a,
+ ERR_SENSOR_UNKNOWN = 0xffffffff
+} err_sensor_id_t;
+
+
+/******************************************************************************
+* The following definitions are used in error_info::context[].
+******************************************************************************/
+#define ERR_CONTEXT_LSM6DS3 "ST-LSM6DS3"
+
+
+#define ERR_MAX_CONTEXT_LEN 32
+
+typedef struct error_info
+{
+ err_case_id_t case_id;
+ err_sensor_id_t sensor_id;
+ char context[ERR_MAX_CONTEXT_LEN];
+} error_info;
+
+
+/******************************************************************************
+* Note that this function cannot be called in the ISR context.
+******************************************************************************/
+__attribute__((weak)) int scp_send_err_to_ap(error_info *info);
+
+
+#endif // _SCP_ERR_INFO_H_
+
+
diff --git a/src/tinysys/medmcu/drivers/common/mbox/inc/scp_ipi.h b/src/tinysys/medmcu/drivers/common/mbox/inc/scp_ipi.h
new file mode 100644
index 0000000..ed0a0a7
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/mbox/inc/scp_ipi.h
@@ -0,0 +1,83 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ */
+/* MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
+ * ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
+ * THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
+ * SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
+ * RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
+ * FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
+ * WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
+ * AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
+ * RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation
+ * ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
+ * subject to any receiver\'s applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __SCP_IPI_H__
+#define __SCP_IPI_H__
+
+#include <ipi.h>
+#include <ipi_id.h>
+#include "ipi_legacy_wrap.h"
+
+enum ipi_status {
+ ERROR = -1,
+ DONE,
+ BUSY,
+};
+
+enum ipi_dir {
+ IPI_SCP2AP = 0,
+ IPI_SCP2SPM,
+ IPI_SCP2CONN,
+ IPI_SCP2MD
+};
+
+struct ipi_wrapper {
+ uint8_t out_id_0;
+ uint8_t out_id_1;
+ uint8_t in_id_0;
+ uint8_t in_id_1;
+ uint32_t out_size;
+ uint32_t in_size;
+ void *msg;
+};
+
+#define IPI_WAIT_LEGACY 0xFFFFFFFF //retry with maximum times
+
+typedef enum ipi_status ipi_status;
+typedef void(*ipi_handler_t)(int id, void * data, unsigned int len);
+
+
+ipi_status scp_ipi_send(enum ipi_id id, void* buf, uint32_t len, uint32_t wait,
+ enum ipi_dir dir);
+ipi_status scp_ipi_registration(enum ipi_id id, ipi_handler_t handler,
+ const char *name);
+
+void scp_legacy_ipi_init(void);
+void ipi_awake_init(void);
+uint32_t is_ipi_busy(void);
+
+#endif
diff --git a/src/tinysys/medmcu/drivers/common/mbox/ipi_port.c b/src/tinysys/medmcu/drivers/common/mbox/ipi_port.c
new file mode 100644
index 0000000..b7d0ae3
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/mbox/ipi_port.c
@@ -0,0 +1,204 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ */
+/* MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
+ * ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
+ * THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
+ * SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
+ * RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
+ * FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
+ * WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
+ * AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
+ * RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation
+ * ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
+ * subject to any receiver\'s applicable license agreements with MediaTek Inc.
+ */
+
+#include "tinysys_reg.h"
+#include "mbox_common_type.h"
+#include "mbox_common.h"
+#ifdef CFG_XGPT_SUPPORT
+#include <xgpt.h>
+#endif
+
+#ifdef CFG_LEGACY_IPI_SUPPORT
+#include "scp_ipi.h"
+#else
+#include <ipi.h>
+#include <ipi_id.h>
+#endif
+
+
+#ifdef CFG_IPI_TEST
+#include "ipi_id.h"
+#include "mbox_common.h"
+#include "mt_printf.h"
+#endif
+
+#ifdef CFG_COMMON_WAKELOCK_SUPPORT
+#include <wakelock.h>
+#endif
+
+#ifdef CFG_PBFR_SUPPORT
+#include "mt_pbfr.h"
+#endif
+
+wakelock_t ap_wakelock;
+wakelock_t connsys_wakelock;
+unsigned int msg_test;
+#ifdef CFG_PBFR_SUPPORT
+int pbfr_start = 0; //pbfr control flag
+#endif
+
+unsigned long long ipi_get_ts(void);
+void ipi_notify_receiver(int ipi_id);
+void ipi_mdelay(unsigned long ms);
+void ipi_platform_init(void);
+
+
+/**
+ * @brief check SCP -> AP IPI is using now
+ * @return pdFALSE, IPI is NOT using now
+ * @return pdTRUE, IPI is using, and AP does not receive the IPI yet.
+ */
+uint32_t is_ipi_busy(void)
+{
+ int i;
+
+ for (i = 0; i < IPI_MBOX_TOTAL; i++)
+ if (DRV_Reg32(mbox_table[i].send_status_reg))
+ return pdTRUE;
+
+ return pdFALSE;
+}
+
+unsigned long long ipi_get_ts(void)
+{
+#ifdef CFG_XGPT_SUPPORT
+ return read_xgpt_stamp_ns();
+#else
+ return 0;
+#endif
+}
+
+/**
+ * @brief send notify to SPM to wakeup AP
+ */
+void ipi_notify_receiver(int ipi_id)
+{
+ /* wakeup APMCU */
+ DRV_SetReg32(SCP2SPM_IPC_SET, 0x1);
+
+ return;
+}
+
+void ipi_mdelay(unsigned long ms)
+{
+#ifdef CFG_XGPT_SUPPORT
+ mdelay(ms);
+#else
+ // do busy waiting w/o xgpt ...
+#endif
+}
+
+/**
+ * @brief AP wakeup SCP and keep SCP awake
+ */
+static void infra_irq_handler(void)
+{
+ unsigned int reg_val;
+
+ reg_val = DRV_Reg32(INFRA_IRQ_SET) & 0xf;
+
+ /* clr interrupt as early as possible to let AP leave busy waiting */
+ DRV_WriteReg32(INFRA_IRQ_CLR, reg_val);
+
+ if (reg_val & (1 << AP_AWAKE_LOCK))
+ wake_lock_FromISR(&ap_wakelock);
+
+ if (reg_val & (1 << AP_AWAKE_UNLOCK))
+ wake_unlock_FromISR(&ap_wakelock);
+
+ if (reg_val & (1 << CONNSYS_AWAKE_LOCK))
+ wake_lock_FromISR(&connsys_wakelock);
+
+ if (reg_val & (1 << CONNSYS_AWAKE_UNLOCK))
+ wake_unlock_FromISR(&connsys_wakelock);
+
+}
+
+void ipi_awake_init(void)
+{
+ wake_lock_init(&ap_wakelock, "AP_W");
+ wake_lock_init(&connsys_wakelock, "CO_W");
+ if (intc_irq_request(&INTC_IRQ_INFRA, (void *)infra_irq_handler, NULL))
+ PRINTF_E("infra irq request failed\n");
+ intc_irq_wakeup_set(&INTC_IRQ_INFRA, 1);
+}
+
+static void scp_ipi_debug(unsigned int id, void *prdata, void *data)
+{
+ unsigned int buffer;
+
+ buffer = *(unsigned int *)data;
+ PRINTF_D("scp get debug ipi buf=%u, id=%u\n", buffer, id);
+#ifdef CFG_PBFR_SUPPORT
+ if (pbfr_start == PBFR_STOP) {
+ pbfr_start = PBFR_START;
+ PRINTF_D("pbfr start load info....\n");
+ pbfr_start_loadinfo(0);
+ } else if (pbfr_start == PBFR_START) {
+ pbfr_start = PBFR_REPORT;
+ pbfr_report_loadinfo(0);
+ } else if (pbfr_start == PBFR_REPORT) {
+ pbfr_start = PBFR_STOP;
+ PRINTF_D("pbfr stop load info.\n");
+ pbfr_stop_loadinfo();
+ }
+#endif
+}
+
+void ipi_platform_init(void)
+{
+ int ret = -1;
+
+ ipi_init();
+#ifdef CFG_LEGACY_IPI_SUPPORT
+ scp_legacy_ipi_init();
+#endif
+
+#ifdef CFG_AMP_CORE1_EN
+ if (mrv_read_csr(CSR_MHARTID) == 0)
+#endif
+ {
+ ipi_awake_init();
+ }
+
+ if (mrv_read_csr(CSR_MHARTID) == 0)
+ ret = ipi_register(IPI_IN_TEST_0, scp_ipi_debug, 0, &msg_test);
+ else
+ ret = ipi_register(IPI_IN_TEST_1, scp_ipi_debug, 0, &msg_test);
+ if (ret)
+ PRINTF_E("ipi test register failed, ret %d\n", ret);
+}
diff --git a/src/tinysys/medmcu/drivers/common/mbox/mbox_port.c b/src/tinysys/medmcu/drivers/common/mbox/mbox_port.c
new file mode 100644
index 0000000..a34e38a
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/mbox/mbox_port.c
@@ -0,0 +1,211 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ */
+/* MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
+ * ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
+ * THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
+ * SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
+ * RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
+ * FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
+ * WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
+ * AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
+ * RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation
+ * ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
+ * subject to any receiver\'s applicable license agreements with MediaTek Inc.
+ */
+
+#include "tinysys_reg.h"
+#include "mbox_common_type.h"
+#include "mbox_common.h"
+#include "mbox_platform.h"
+#include "mbox_pin.h"
+#include "interrupt.h"
+#include "mt_printf.h"
+#include "ipi_id.h"
+#include "driver_api.h"
+#include "mt_printf.h"
+#include "irq.h"
+#include "ipi_table.h"
+#ifdef CFG_XGPT_SUPPORT
+#include <xgpt.h>
+#endif
+
+#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
+
+void init_pin_number(void);
+unsigned int find_mbox_num(unsigned int irq_num);
+int set_mbox_64d(unsigned int mbox, unsigned int is64d, void *data);
+void mbox_setup_pin_table(int mbox);
+void dump_pin_table(int8_t);
+int register_irq_handler(void (*mbox_isr)(void *data), void *prdata);
+extern void mbox_isr_pre_cb(void);
+extern void mbox_isr_post_cb(void);
+
+void mbox_isr_pre_cb(void) {return;}
+void mbox_isr_post_cb(void) {return;}
+
+/*
+ * init send/recv pin function, must in mbox_port.c
+ */
+void init_pin_number(void)
+{
+ TOTAL_RECV_PIN = sizeof(mbox_pin_recv_table)/sizeof(struct pin_recv);
+ TOTAL_SEND_PIN = sizeof(mbox_pin_send_table)/sizeof(struct pin_send);
+}
+
+
+/*
+ * find mbox number in mbox_isr funtion
+ */
+unsigned int find_mbox_num(unsigned int irq_num)
+{
+ return irq_num;
+}
+
+/*
+ * set mbox 64d function
+ */
+int set_mbox_64d(unsigned int mbox, unsigned int is64d, void *data)
+{
+ //set mbox is 64d
+ if (is64d == MBOX_OPT_32_SLOT)
+ DRV_ClrReg32(R_SECURE_CTRL, B_MBOX0_SIZE << mbox);
+ else
+ DRV_SetReg32(R_SECURE_CTRL, B_MBOX0_SIZE << mbox);
+
+ return 0;
+}
+
+/*
+ * set send/recv offset and pin by is64d
+ */
+void mbox_setup_pin_table(int mbox)
+{
+ unsigned int i;
+ int last_ofs = 0, last_idx = 0, last_slot = 0, last_sz = 0;
+
+ for (i = 0; i < TOTAL_RECV_PIN; i++) {
+ if (mbox == mbox_pin_recv_table[i].mbox) {
+ /* update pin offset, idex */
+ mbox_pin_recv_table[i].offset = last_ofs + last_slot;
+ mbox_pin_recv_table[i].pin_index = last_idx + last_sz;
+
+ /* calculate occupied msg size, offset, slots*/
+ last_idx = mbox_pin_recv_table[i].pin_index;
+ last_sz = DIV_ROUND_UP(mbox_pin_recv_table[i].msg_size,
+ mbox_table[mbox].is64d + 1);
+ last_ofs = last_sz * (mbox_table[mbox].is64d + 1);
+ last_slot = last_idx * (mbox_table[mbox].is64d + 1);
+ } else if (mbox < mbox_pin_recv_table[i].mbox)
+ break; /* no need to search the rest ipi */
+ }
+
+ for (i = 0; i < TOTAL_SEND_PIN; i++) {
+ if (mbox == mbox_pin_send_table[i].mbox) {
+ /* update pin offset, idex */
+ mbox_pin_send_table[i].offset = last_ofs + last_slot;
+ mbox_pin_send_table[i].pin_index = last_idx + last_sz;
+
+ /* calculate occupied msg size, offset, slots*/
+ last_idx = mbox_pin_send_table[i].pin_index;
+ last_sz = DIV_ROUND_UP(mbox_pin_send_table[i].msg_size,
+ mbox_table[mbox].is64d + 1);
+ last_ofs = last_sz * (mbox_table[mbox].is64d + 1);
+ last_slot = last_idx * (mbox_table[mbox].is64d + 1);
+ } else if (mbox < mbox_pin_send_table[i].mbox)
+ break; /* no need to search the rest ipi */
+ }
+
+ if (last_idx > 32 ||
+ (last_ofs + last_slot) > (mbox_table[mbox].is64d + 1) * 32) {
+ PRINTF_E("mbox%d index(%d)/slot(%d) exceed the maximum\n",
+ mbox, last_idx, last_ofs);
+ configASSERT(0);
+ }
+}
+
+extern uint64_t mbox_get_time_stamp(void);
+uint64_t mbox_get_time_stamp(void)
+{
+#ifdef CFG_XGPT_SUPPORT
+ return (uint64_t) read_xgpt_stamp_ns();
+#else
+ return 0;
+#endif
+}
+
+/*
+ * dump pin table with selected mbox
+ * bit[0:3] represent to mbox0~mbox4
+ */
+void dump_pin_table(int8_t mbox)
+{
+ unsigned int i;
+
+ PRINTF_D("pin recv table:\n");
+ for (i = 0; i < TOTAL_RECV_PIN; i++) {
+ if ((1 << mbox_pin_recv_table[i].mbox) & mbox)
+ PRINTF_D(" mbox%d pin%02d index: %02u, offset: %02u, sz: %02u\n",
+ mbox_pin_recv_table[i].mbox,
+ mbox_pin_recv_table[i].ipi_id,
+ mbox_pin_recv_table[i].pin_index,
+ mbox_pin_recv_table[i].offset,
+ mbox_pin_recv_table[i].msg_size);
+ }
+
+ PRINTF_D("pin send table:\n");
+ for (i = 0; i < TOTAL_SEND_PIN; i++) {
+ if ((1 << mbox_pin_send_table[i].mbox) & mbox)
+ PRINTF_D(" mbox%d pin%02d index: %02u, offset: %02u, sz: %02u\n",
+ mbox_pin_send_table[i].mbox,
+ mbox_pin_send_table[i].ipi_id,
+ mbox_pin_send_table[i].pin_index,
+ mbox_pin_send_table[i].offset,
+ mbox_pin_send_table[i].msg_size);
+ }
+
+}
+
+/*
+ * register_irq_handler
+ */
+int register_irq_handler(void (*mbox_isr)(void *data), void *prdata)
+{
+ int mbox;
+
+ mbox = *(int *)prdata;
+
+ /* clear mbox interrupt to ensure mbox is clean before request */
+ mbox_clr_irq(mbox, 0xffffffff);
+
+ if (intc_irq_request(&INTC_IRQ_MBOX[mbox],
+ (void *)mbox_isr, &mbox_table[mbox]) != 0) {
+ PRINTF_E("mbox %d irq request failed\n", mbox);
+ return MBOX_CONFIG_ERR;
+ } else {
+ intc_irq_wakeup_set(&INTC_IRQ_MBOX[mbox], 0x1);
+ return MBOX_DONE;
+ }
+}
+
diff --git a/src/tinysys/medmcu/drivers/common/mbox/scp_ipi.c b/src/tinysys/medmcu/drivers/common/mbox/scp_ipi.c
new file mode 100644
index 0000000..8f8c39c
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/mbox/scp_ipi.c
@@ -0,0 +1,168 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ */
+/* MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
+ * ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
+ * THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
+ * SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
+ * RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
+ * FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
+ * WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
+ * AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
+ * RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation
+ * ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
+ * subject to any receiver\'s applicable license agreements with MediaTek Inc.
+ */
+
+#include "scp_ipi.h"
+#include "encoding.h"
+
+
+static struct ipi_wrapper ipi_legacy_id [] = IPI_LEGACY_GROUP;
+ipi_handler_t mpool_handle_list[IPI_WRAPPER_TOTAL - IPI_MPOOL - 1];
+struct ipi_legacy_pkt {
+ unsigned int id;
+ unsigned int len;
+ void *data;
+};
+
+/*
+ * This is a handler for handling legacy ipi callback function
+ */
+static void legacy_handler(int id, void *prdata, void *data, unsigned int len)
+{
+ ipi_handler_t handler;
+ unsigned int ptr = (unsigned int)data;
+ struct ipi_legacy_pkt pkt;
+
+ /* variation length will only support chre, chrex and sensor for reducing
+ * slot and cpu time cost by memcpy.
+ */
+ pkt.id = *(unsigned int *)ptr;
+ pkt.len = *(unsigned int *)(ptr + 4);
+ pkt.data = (void *)(ptr + 8);
+
+ if (pkt.id > IPI_MPOOL)
+ handler = mpool_handle_list[pkt.id - IPI_MPOOL - 1];
+ else
+ handler = (ipi_handler_t)prdata;
+ handler(pkt.id, pkt.data, pkt.len);
+}
+
+/*
+ * Wrapper api for legacy api and supports only legacy features
+ * which is listed in ipi_legacy_id[]
+ */
+ipi_status scp_ipi_send(enum ipi_id id, void* buf, uint32_t len, uint32_t wait,
+ enum ipi_dir dir)
+{
+ int ret = 0, tmp_id;
+ void *ptr;
+
+ if (id >= IPI_WRAPPER_TOTAL || id == IPI_MPOOL) {
+ PRINTF_E("%s: id not support\n", __func__);
+ return ERROR;
+ }
+
+ if (id > IPI_MPOOL)
+ tmp_id = IPI_MPOOL;
+ else
+ tmp_id = id;
+
+ if (len > (ipi_legacy_id[tmp_id].out_size - 2) * MBOX_SLOT_SIZE) {
+ PRINTF_E("%s: len overflow\n", __func__);
+ return ERROR;
+ }
+
+ /* variation length will only support chre and sensor for reducing slot
+ * and cpu time cost by memcpy.
+ */
+ char pkt[ipi_legacy_id[tmp_id].out_size * MBOX_SLOT_SIZE];
+ memcpy((void *)pkt, (void *)&id, sizeof(uint32_t));
+ memcpy((void *)(pkt + 4), (void *)&len, sizeof(uint32_t));
+ memcpy((void *)(pkt + 8), buf, len);
+ ptr = pkt;
+
+ if (mrv_read_csr(CSR_MHARTID) == 0)
+ ret = ipi_send(ipi_legacy_id[tmp_id].out_id_0, ptr,
+ (int)ipi_legacy_id[tmp_id].out_size,
+ wait * IPI_WAIT_LEGACY);
+ else
+ ret = ipi_send(ipi_legacy_id[tmp_id].out_id_1, ptr,
+ (int)ipi_legacy_id[tmp_id].out_size,
+ wait * IPI_WAIT_LEGACY);
+
+ if (ret == IPI_ACTION_DONE)
+ return DONE;
+ else if (ret == IPI_PIN_BUSY)
+ return BUSY;
+ else
+ return ERROR;
+}
+
+ipi_status scp_ipi_registration(enum ipi_id id, ipi_handler_t handler,
+ const char *name)
+{
+ int ret = 0;
+
+ if (id >= IPI_WRAPPER_TOTAL || id == IPI_MPOOL) {
+ PRINTF_E("%s: id not support\n", __func__);
+ return ERROR;
+ }
+
+ if (id > IPI_MPOOL) {
+ /* if there's any new ipi, hook handler only */
+ mpool_handle_list[id - IPI_MPOOL - 1] = handler;
+ return DONE;
+ }
+
+ if (mrv_read_csr(CSR_MHARTID) == 0) {
+ ret = ipi_register(ipi_legacy_id[id].in_id_0, legacy_handler,
+ handler, ipi_legacy_id[id].msg);
+ } else {
+ ret = ipi_register(ipi_legacy_id[id].in_id_1, legacy_handler,
+ handler, ipi_legacy_id[id].msg);
+ }
+
+ if (ret == IPI_ACTION_DONE)
+ return DONE;
+ else
+ return ERROR;
+}
+
+void scp_legacy_ipi_init(void)
+{
+ int ret = 0;
+
+ if (mrv_read_csr(CSR_MHARTID) == 0) {
+ ret = ipi_register(IPI_IN_SCP_MPOOL_0, legacy_handler, 0,
+ msg_legacy_ipi_mpool);
+ } else {
+ ret = ipi_register(IPI_IN_SCP_MPOOL_1, legacy_handler, 0,
+ msg_legacy_ipi_mpool);
+ }
+
+ if (ret)
+ PRINTF_E("ipi mpool register fail, ret %d\n", ret);
+}
diff --git a/src/tinysys/medmcu/drivers/common/scpctl/inc/scp_scpctl.h b/src/tinysys/medmcu/drivers/common/scpctl/inc/scp_scpctl.h
new file mode 100644
index 0000000..60d4a94
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/scpctl/inc/scp_scpctl.h
@@ -0,0 +1,66 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek Software")
+ * have been modified by MediaTek Inc. All revisions are subject to any receiver's
+ * applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __SCP_SCPCTL_H__
+#define __SCP_SCPCTL_H__
+
+#include <stdint.h>
+
+enum SCPCTL_TYPE_E {
+ SCPCTL_TYPE_TMON,
+ SCPCTL_STRESS_TEST,
+};
+
+enum SCPCTL_OP_E {
+ SCPCTL_OP_INACTIVE = 0,
+ SCPCTL_OP_ACTIVE,
+};
+
+struct scpctl_cmd_s {
+ uint32_t type;
+ uint32_t op;
+};
+
+void scpctl_init(void);
+void scpctl_idlehook(void);
+void vTaskMonitor(void *pvParameters);
+
+#ifdef CFG_MRV_UNALIGN_SUPPORT
+extern unsigned int misalignedLoad;
+extern unsigned int misalignedStore;
+#endif
+
+#endif /* __SCP_SCPCTL_H__ */
+
diff --git a/src/tinysys/medmcu/drivers/common/scpctl/scp_scpctl.c b/src/tinysys/medmcu/drivers/common/scpctl/scp_scpctl.c
new file mode 100644
index 0000000..994d583
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/scpctl/scp_scpctl.c
@@ -0,0 +1,215 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2015. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ */
+
+#include <FreeRTOS.h>
+#include <task.h>
+#ifdef CFG_LEGACY_IPI_SUPPORT
+#include <scp_ipi.h>
+#else
+#include <ipi.h>
+#include <ipi_id.h>
+#endif
+
+#include <scp_scpctl.h>
+#include <main.h>
+#include "encoding.h"
+#include "irq.h"
+#ifdef CFG_XGPT_SUPPORT
+#include <mt_gpt.h>
+#endif
+
+enum SCPCTL_STAT_E {
+ SCPCTL_STAT_INACTIVE = 0,
+ SCPCTL_STAT_ACTIVE,
+};
+
+struct scpctl_ctl_s {
+ enum SCPCTL_OP_E op;
+ enum SCPCTL_STAT_E stat;
+};
+
+#define mainCHECK_DELAY ((portTickType) 10000 / portTICK_RATE_MS)
+
+static struct scpctl_ctl_s scpctl __attribute__ ((section(".sync")));
+static char *prompt = "[SCPCTL]";
+static TaskHandle_t xMonitorTask = NULL;
+struct scpctl_cmd_s scpctl_cmd_s_buf __attribute__ ((section(".sync")));
+
+#ifdef CFG_SCP_STRESS_SUPPORT
+unsigned int task_stress_flag __attribute__((section(".sync"))) = 0;
+#endif
+
+#ifdef CFG_SCPCTL_TASK_STATUS
+static char list_buffer[512];
+
+static void __task_status(void)
+{
+ vTaskList(list_buffer);
+ PRINTF_E("Heap:free/total:%lu/%u\n", xPortGetFreeHeapSize(), configTOTAL_HEAP_SIZE);
+ PRINTF_E("Task Status:\n\r%s", list_buffer);
+// PRINTF_E("max dur.:%llu,limit:%llu\n", get_max_cs_duration_time(), get_max_cs_limit());
+}
+#endif
+
+void vTaskMonitor(void *pvParameters)
+{
+ portTickType xLastExecutionTime, xDelayTime;
+ xDelayTime = mainCHECK_DELAY;
+
+ do {
+ xLastExecutionTime = xTaskGetTickCount();
+
+#ifdef CFG_SCPCTL_TASK_STATUS
+ __task_status();
+#endif
+#ifdef CFG_MRV_UNALIGN_SUPPORT
+ PRINTF_E("unaligned Load/Store times (%u/%u)\n", misalignedLoad, misalignedStore);
+#endif
+ vTaskDelayUntil(&xLastExecutionTime, xDelayTime);
+ } while (1);
+}
+
+
+/****************************************************************************
+ * The ISR is to receive the IPI commands sent by ADB and then modify
+ * the operation, op, of the control state.
+ ****************************************************************************/
+static void scpctl_handler(unsigned int id, void *prdata, void *data, unsigned int len)
+{
+ struct scpctl_cmd_s *cmd = (struct scpctl_cmd_s *)data;
+ enum SCPCTL_TYPE_E type = cmd->type;
+ enum SCPCTL_OP_E op = cmd->op;
+
+ switch (type) {
+ case SCPCTL_TYPE_TMON:
+ scpctl.op = (op == SCPCTL_OP_ACTIVE)
+ ? SCPCTL_OP_ACTIVE
+ : SCPCTL_OP_INACTIVE;
+
+ PRINTF_E("%s: type/op=%d/%d,stat=%d\n", prompt, type, op, scpctl.stat);
+ break;
+#ifdef CFG_SCP_STRESS_SUPPORT
+ case SCPCTL_STRESS_TEST:
+ task_stress_flag = 1;
+ PRINTF_E("Stress enabled\n");
+ break;
+#endif
+ default:
+ PRINTF_E("%s: unknown cmd, %d, %d\n", prompt, type, op);
+ break;
+ }
+}
+
+/****************************************************************************
+ * The function is called by in vApplicationIdleHook and determine whether
+ * to resume or to suspend monitor task depending on the command and the
+ * current status.
+ *
+ * op = active, state = inactive --> resume monitor task.
+ * op = inactive, state = active --> suspend monitor task.
+ * others, keep the same status.
+ ****************************************************************************/
+void scpctl_idlehook(void)
+{
+ int op = scpctl.op;
+
+ if (op == SCPCTL_OP_ACTIVE && scpctl.stat == SCPCTL_STAT_INACTIVE) {
+ vTaskResume(xMonitorTask);
+ scpctl.stat = SCPCTL_STAT_ACTIVE;
+ }
+ else if (op == SCPCTL_OP_INACTIVE && scpctl.stat == SCPCTL_STAT_ACTIVE) {
+ vTaskSuspend(xMonitorTask);
+ scpctl.stat = SCPCTL_STAT_INACTIVE;
+ }
+}
+
+
+#ifdef CFG_SCP_STRESS_SUPPORT
+
+/* run on both core */
+static void vTaskSCPStress(void *pvParameters)
+{
+ portTickType xLastExecutionTime, xDelayTime;
+ xLastExecutionTime = xTaskGetTickCount();
+ unsigned int get_random_time;
+ xDelayTime = (portTickType) 60000 / portTICK_RATE_MS ;
+ do {
+ PRINTF_E("Task Stress ");
+ if (task_stress_flag == 0) {
+ PRINTF_E("status=%u\n", task_stress_flag);
+ } else {
+ /* stress flag is enable*/
+ PRINTF_E("status=%u, stress enable!\n", task_stress_flag);
+ /* get 60 ~120 sec delay*/
+#ifdef CFG_XGPT_SUPPORT
+ get_random_time = (unsigned int)(get_boot_time_ns() % 60);
+ get_random_time = (30 + get_random_time) * 1000;
+ xDelayTime = (portTickType) get_random_time / portTICK_RATE_MS ;
+#endif
+ PRINTF_E("after:%ums, will abort...\n", xDelayTime);
+ vTaskDelayUntil(&xLastExecutionTime, xDelayTime);
+ configASSERT(0);
+ }
+ xDelayTime = (portTickType) 60000 / portTICK_RATE_MS ;
+ vTaskDelayUntil(&xLastExecutionTime, xDelayTime);
+ } while (1);
+}
+#endif
+
+void scpctl_init(void)
+{
+ int ret = 0;
+
+ xTaskCreate(vTaskMonitor, "TMon", 384, (void*)4, PRI_MONITOR, &xMonitorTask);
+ configASSERT(xMonitorTask != NULL);
+#ifdef CFG_SCP_STRESS_SUPPORT
+ xTaskCreate(vTaskSCPStress, "Stres", 384, (void*)4, PRI_STRESS, NULL);
+#endif /* CFG_SCP_STRESS_SUPPORT */
+
+ if (scp_region_info.scpctl & (1 << SCPCTL_TYPE_TMON)) {
+ scpctl.stat = SCPCTL_STAT_ACTIVE;
+ scpctl.op = SCPCTL_OP_ACTIVE;
+ }
+ else { /* monitor task is in suspened state */
+ scpctl.stat = SCPCTL_STAT_INACTIVE;
+ scpctl.op = SCPCTL_OP_INACTIVE;
+ vTaskSuspend(xMonitorTask);
+ }
+ /* uni-control, do it only ine one core */
+ if (mrv_read_csr(CSR_MHARTID) == 1) {
+ ret = ipi_register(IPI_IN_SCPCTL_1, scpctl_handler, 0, &scpctl_cmd_s_buf);
+ if (ret)
+ PRINTF_E("IPI_IN_SCPCTL_1 %d\n", ret);
+ }
+
+
+}
+
diff --git a/src/tinysys/medmcu/drivers/common/sem/inc/mtk_sem.h b/src/tinysys/medmcu/drivers/common/sem/inc/mtk_sem.h
new file mode 100644
index 0000000..b77e7f2
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/sem/inc/mtk_sem.h
@@ -0,0 +1,47 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
+ * ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
+ * THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
+ * SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
+ * RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
+ * FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
+ * WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
+ * AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
+ * RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation
+ * ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
+ * subject to any receiver\'s applicable license agreements with MediaTek Inc.
+ */
+
+#include <tinysys_reg.h>
+#include <encoding.h>
+#define SEMAPHORE_REG R_SEMAPHORE
+#define SEMA_TIMEOUT 5
+
+#ifdef CFG_SEMAPHORE_3WAY_SUPPORT
+#define SEMAPHORE_3WAY_REG R_SEMAPHORE_3MST
+#define SEMAPHORE_3WAY_BITS 4
+#define DSP_CORE_ID (mrv_read_csr(CSR_MHARTID))//SCP_A_ID
+#endif
diff --git a/src/tinysys/medmcu/drivers/common/tiny_ipc/inc/tiny_ipc.h b/src/tinysys/medmcu/drivers/common/tiny_ipc/inc/tiny_ipc.h
new file mode 100644
index 0000000..37747d0
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/tiny_ipc/inc/tiny_ipc.h
@@ -0,0 +1,82 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
+ * ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
+ * THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
+ * SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
+ * RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
+ * FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
+ * WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
+ * AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
+ * RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation
+ * ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
+ * subject to any receiver\'s applicable license agreements with MediaTek Inc.
+ */
+
+/* buff at end of l2_tcm, total 512 byte
+include send and receive */
+#define TINY_IPC_BUFF_SIZE 512
+
+enum ipi_id {
+ TIPC_SCP_CORE0_READY = 0,
+ TIPC_SLT_CORE0_CTL,
+ TIPC_CORE0_END = 15,
+ TIPC_SCP_CORE1_READY = 16,
+ TIPC_SLT_CORE1_CTL,
+ TIPC_CORE1_END,
+ NR_TIPC,
+};
+
+typedef void(*tipc_handler_t)(int id, void *data, unsigned int len);
+
+struct tipc_desc_t {
+ tipc_handler_t handler;
+ const char *name;
+};
+
+enum tipc_status {
+ T_ERROR =-1,
+ T_DONE,
+ T_BUSY,
+};
+#define IPC_WAIT 1
+#define IPC_NOWAIT 0
+
+
+#define TIPC_RECEIVE_BUFF (L2TCM_START + L2TCM_SIZE - TINY_IPC_BUFF_SIZE)
+#define TIPC_SEND_BUFF (L2TCM_START + L2TCM_SIZE - (TINY_IPC_BUFF_SIZE/2))
+
+enum tipc_status tiny_ipc_send(int id, void* buf, uint32_t len, uint32_t wait);
+
+enum tipc_status tiny_ipc_registration(int id, tipc_handler_t handler, const char *name);
+
+extern struct INTC_IRQ INTC_IRQ_GIPC0;
+
+void tiny_ipc_init(void);
+
+void tiny_ipc_isr(void);
+
+
+
diff --git a/src/tinysys/medmcu/drivers/common/tiny_ipc/tiny_ipc.c b/src/tinysys/medmcu/drivers/common/tiny_ipc/tiny_ipc.c
new file mode 100644
index 0000000..9d37d1a
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/tiny_ipc/tiny_ipc.c
@@ -0,0 +1,193 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
+ * ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
+ * THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
+ * SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
+ * RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
+ * FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
+ * WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
+ * AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
+ * RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation
+ * ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
+ * subject to any receiver\'s applicable license agreements with MediaTek Inc.
+ */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "tiny_ipc.h"
+#include <tinysys_reg.h>
+#include <driver_api.h>
+#include <mt_printf.h>
+#include "irq.h"
+#ifdef CFG_ATOMIC_PLAT_SUPPORT
+#include "mtk_atomic.h"
+#endif
+#ifdef CFG_XGPT_SUPPORT
+#include <xgpt.h>
+#endif
+
+#ifdef CFG_COMMON_WAKELOCK_SUPPORT
+#include <wakelock.h>
+#endif
+
+
+static struct tipc_desc_t tipc_desc[NR_TIPC];
+spinlock_t SYNC_SECTION tipc_lock;
+
+#ifdef CFG_COMMON_WAKELOCK_SUPPORT
+wakelock_t ap_wakelock;
+#endif
+
+/*
+@param id: IPI ID
+@param handler: IPI handler
+@param name: IPI name
+*/
+enum tipc_status tiny_ipc_registration(int id, tipc_handler_t handler, const char *name)
+{
+ PRINTF_E("%s id:%d: %s", __func__, id, name);
+ if (handler == NULL)
+ return T_ERROR;
+
+ if (id >= NR_TIPC)
+ return T_ERROR;
+
+ tipc_desc[id].name = name;
+ tipc_desc[id].handler = handler;
+ return T_DONE;
+}
+
+
+static void try_to_wakeup_ap(void)
+{
+ //ipi_scp2spm(); //wake APMCU up
+}
+/*
+ return fail when resource not ready
+*/
+
+enum tipc_status tiny_ipc_send(int id, void* buf, uint32_t len, uint32_t wait)
+{
+ unsigned long flags;
+ int i = 0;
+
+ //PRINTF_I("%s %d\n", __func__, __LINE__);
+ if(len > (TINY_IPC_BUFF_SIZE/2)) {
+ PRINTF_D("%s len %d over\n", __func__, len);
+ return T_ERROR;
+ }
+
+ flags = spinlock_lock_irqsave(&tipc_lock);
+
+ /* Check if there is already an ipi pending in AP. */
+ //while (readl(SCP2APMCU_IPC_SET) & SCP2APMCU_BIT0) {
+ while (readl(MBOX1_OUT_IRQ_SET) & SCP2APMCU_BIT0) {
+ /*If the following conditions meet,
+ * 1)there is an ipi pending in AP
+ * 2)the coming IPI is a wakeup IPI
+ * so it assumes that AP is in suspend state
+ * send a AP wakeup request to SPM
+ * */
+ /*the coming IPI will be checked if it's a wakeup source*/
+ try_to_wakeup_ap();
+ mdelay(1);
+
+ i++;
+ if( i > 1000) {
+ PRINTF_D("%s id:%d busy\n", __func__, id);
+ spinlock_unlock_irqrestore(&tipc_lock, flags);
+ return T_BUSY;
+ }
+ }
+
+ //PRINTF_I("%s %d\n", __func__, __LINE__);
+ writel((void *)(TIPC_SEND_BUFF ), id);
+ writel((void *)(TIPC_SEND_BUFF + 4), len);
+ memcpy((void *)(TIPC_SEND_BUFF + 8), buf, len);
+
+ //writel(SCP2APMCU_IPC_SET, SCP2APMCU_BIT0);
+ writel(MBOX1_OUT_IRQ_SET, SCP2APMCU_BIT0);
+
+ spinlock_unlock_irqrestore(&tipc_lock, flags);
+
+ if (wait)
+ //while ((readl(SCP2APMCU_IPC_SET) & SCP2APMCU_BIT0));
+ while ((readl(MBOX1_OUT_IRQ_SET) & SCP2APMCU_BIT0));
+
+ return T_DONE;
+}
+
+#ifdef CFG_COMMON_WAKELOCK_SUPPORT
+static void tiny_ipc_wakeup_isr(void)
+{
+ unsigned int reg_val;
+
+ reg_val = readl(MBOX2_IN_IRQ_SET) & 0xf;
+ PRINTF_D("%s reg=%d\n", __func__, reg_val);
+
+ /* clr interrupt as early as possible to let AP leave busy waiting */
+ writel(MBOX2_IN_IRQ_CLR, reg_val);
+
+ if (reg_val & (1 << AP_AWAKE_LOCK))
+ wake_lock_FromISR(&ap_wakelock);
+
+ if (reg_val & (1 << AP_AWAKE_UNLOCK))
+ wake_unlock_FromISR(&ap_wakelock);
+
+}
+
+static void tiny_ipc_awake_init(void)
+{
+ wake_lock_init(&ap_wakelock, "AP_W");
+ if (intc_irq_request(&INTC_IRQ_MBOX[2], (void *)tiny_ipc_wakeup_isr, NULL))
+ PRINTF_E("wakeup irq request failed\n");
+ intc_irq_wakeup_set(&INTC_IRQ_MBOX[2], 1);
+}
+#endif
+
+void tiny_ipc_isr(void)
+{
+ int id = 0, size = 0;
+ id = readl((void *)TIPC_RECEIVE_BUFF);
+ size = readl((void *)(TIPC_RECEIVE_BUFF + 4));
+ if (tipc_desc[id].name != NULL){
+ PRINTF_D("%s %d\n", __func__, id);
+ tipc_desc[id].handler(id, (void*)(TIPC_RECEIVE_BUFF + 8), size);
+ }
+ /* clear INT */
+ //writel(GIPC_IN_CLR, readl(GIPC_IN_SET));
+ writel(MBOX1_IN_IRQ_CLR, SCP2APMCU_BIT0);
+}
+
+void tiny_ipc_init(void)
+{
+ //intc_irq_request(&INTC_IRQ_GIPC0, (void *) tiny_ipc_isr, NULL);
+ //intc_irq_wakeup_set(&INTC_IRQ_GIPC0, 1);
+ intc_irq_request(&INTC_IRQ_MBOX[1], (void *) tiny_ipc_isr, NULL);
+ intc_irq_wakeup_set(&INTC_IRQ_MBOX[1], 1);
+#ifdef CFG_COMMON_WAKELOCK_SUPPORT
+ tiny_ipc_awake_init();
+#endif
+}
diff --git a/src/tinysys/medmcu/drivers/common/wdt/inc/wdt.h b/src/tinysys/medmcu/drivers/common/wdt/inc/wdt.h
new file mode 100644
index 0000000..9bb2bc7
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/wdt/inc/wdt.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2010. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek Software")
+ * have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+ * applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef _WDT_H_
+#define _WDT_H_
+
+#define WDT_IRQ_REG (CORE0_WDT_IRQ + mrv_read_csr(CSR_MHARTID)*0x10000)
+#define WDT_CFGREG (CORE0_WDT_CFG + mrv_read_csr(CSR_MHARTID)*0x10000)
+#define WDT_KICKREG (CORE0_WDT_KICK + mrv_read_csr(CSR_MHARTID)*0x10000)
+#define WDT_CUR_VAL_REG (CORE0_WDT_CUR_VAL + mrv_read_csr(CSR_MHARTID)*0x10000)
+
+#define START_WDT 0x800FFFFF //enable wdt, timeout in 31 sec
+#define KICK_WDT 0x1
+#define DISABLE_WDT 0x000FFFFF
+#define WDT_EN 0x1F
+#define WDT_INSTANT_TRIGGER 0x0
+
+#define SCP_GPR_REBOOT_FLAG (SCP_GPR_CORE0_REBOOT + mrv_read_csr(CSR_MHARTID)*0x10000)
+
+void mtk_wdt_disable(void);
+void mtk_wdt_enable(void);
+void mtk_wdt_restart(void);
+void mtk_wdt_irq_clear(void);
+int mtk_wdt_set_time_out_value(unsigned int value);
+void mtk_wdt_isr(void);
+void mtk_wdt_init(void);
+void scp_ready_to_reboot(void);
+void scp_halt_isr(void);
+void mtk_halt_isr_init(void);
+void scp_endless_loop(void);
+
+#endif /* _WDT_H_ */
+
diff --git a/src/tinysys/medmcu/drivers/common/wdt/wdt.c b/src/tinysys/medmcu/drivers/common/wdt/wdt.c
new file mode 100644
index 0000000..029a576
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/wdt/wdt.c
@@ -0,0 +1,138 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ */
+/* MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
+ * ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
+ * THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
+ * SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
+ * RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
+ * FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
+ * WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
+ * AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
+ * RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation
+ * ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
+ * subject to any receiver\'s applicable license agreements with MediaTek Inc.
+ */
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include <tinysys_reg.h>
+#include <driver_api.h>
+#include <mt_printf.h>
+#include <irq.h>
+#include <intc.h>
+#include <encoding.h>
+#include <wdt.h>
+#ifdef CFG_XGPT_SUPPORT
+#include <xgpt.h>
+#endif
+#include <peripheral.h>
+
+void mtk_wdt_disable(void)
+{
+ DRV_WriteReg32(WDT_CFGREG, DISABLE_WDT);
+}
+void mtk_wdt_enable(void)
+{
+ DRV_WriteReg32(WDT_CFGREG, START_WDT);
+}
+void mtk_wdt_irq_clear(void)
+{
+ DRV_WriteReg32(WDT_IRQ_REG, 0x1);
+}
+void mtk_wdt_restart(void)
+{
+ DRV_WriteReg32(WDT_KICKREG, KICK_WDT);
+}
+
+int mtk_wdt_set_time_out_value(unsigned int value)
+{
+ if (value > 0xFFFFF) {
+ PRINTF_D("SCP WDT Timeout value overflow\n");
+ return -1;
+ }
+ mtk_wdt_disable();
+ DRV_WriteReg32(WDT_CFGREG, 1 << WDT_EN | value);
+ return 0;
+}
+
+void scp_endless_loop(void)
+{
+ taskDISABLE_INTERRUPTS();
+ /* cleanup gvic setting for avoiding interrupt or wakeup triggered */
+ vic_set_mask(0, 0x0);
+ vic_set_wakeup_mask(0, 0x0);
+ /* Halt CPU */
+ while(1)
+ __asm volatile ("wfi");
+}
+
+void scp_ready_to_reboot(void)
+{
+ /* set reboot flag to let AP know we are ready to reboot*/
+ *(volatile unsigned int *)SCP_GPR_REBOOT_FLAG = CORE_RDY_TO_REBOOT;
+
+}
+void mtk_wdt_isr(void)
+{
+ PRINTF_D("%s core%lu\n", __func__, mrv_read_csr(CSR_MHARTID));
+ /* notify another core */
+ DRV_WriteReg32(GIPC_IN_SET, GIPC4_SETCLR_BIT_0);
+ scp_ready_to_reboot();
+ scp_endless_loop();
+}
+
+void scp_halt_isr(void)
+{
+ PRINTF_D("%s core%lu\n", __func__, mrv_read_csr(CSR_MHARTID));
+ scp_ready_to_reboot();
+ scp_endless_loop();
+}
+
+void mtk_wdt_init(void)
+{
+ mtk_wdt_disable();
+#ifdef CFG_XGPT_SUPPORT
+ /* needs 70us to reload counter value */
+ udelay(70);
+#endif
+ mtk_wdt_irq_clear();
+ intc_irq_request(&INTC_IRQ_WDT, (void *) mtk_wdt_isr, NULL);
+ intc_irq_wakeup_set(&INTC_IRQ_WDT, 1);
+ mtk_halt_isr_init();
+ mtk_wdt_enable();
+ mtk_wdt_restart(); /* restart wdt after wdt reset */
+ PRINTF_D("SCP mtk_wdt_init: WDT_CFGREG=0x%x!!\n", DRV_Reg32(WDT_CFGREG));
+}
+
+
+void mtk_halt_isr_init(void)
+{
+ /* clear ipc first */
+ DRV_WriteReg32(GIPC_IN_CLR, GIPC4_SETCLR_BIT_0);
+ intc_irq_request(&INTC_IRQ_HALT, (void *) scp_halt_isr, NULL);
+ intc_irq_wakeup_set(&INTC_IRQ_HALT, 1);
+}
+
+
diff --git a/src/tinysys/medmcu/drivers/common/xgpt/inc/mt_gpt.h b/src/tinysys/medmcu/drivers/common/xgpt/inc/mt_gpt.h
new file mode 100644
index 0000000..af20573
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/xgpt/inc/mt_gpt.h
@@ -0,0 +1,37 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2015. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ */
+
+#ifndef __MT_GPT_H__
+#define __MT_GPT_H__
+
+#include "xgpt.h"
+
+#endif
diff --git a/src/tinysys/medmcu/drivers/common/xgpt/inc/xgpt.h b/src/tinysys/medmcu/drivers/common/xgpt/inc/xgpt.h
new file mode 100644
index 0000000..a6502aa
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/xgpt/inc/xgpt.h
@@ -0,0 +1,221 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2015. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ */
+
+#ifndef __XGPT_H__
+#define __XGPT_H__
+
+#include <stdio.h>
+#include <stdint.h>
+#include <encoding.h>
+#include <irq.h>
+
+#define TIMER_IN_CLK (CLK_CTRL_BASE + 0x30)
+#define TMR_MCLK_CG (1 << 0)
+#define TMR_BCLK_CG (1 << 1)
+
+#define XGPT_BASE_REG (SCP_TIMER_CORE0_BASE + mrv_read_csr(CSR_MHARTID)*0x10000)
+#define GENERAL_CTRL (CORE0_GENERAL_CTRL + mrv_read_csr(CSR_MHARTID)*0x10000)
+
+#define SCP_TIMER_BASE g_timer_base
+
+#define TMR0 0x0
+#define TMR1 0x1
+#define TMR2 0x2
+#define TMR3 0x3
+#define TMR4 0x4
+#define TMR5 0x5
+#define NR_TMRS 0x6
+
+#define TIMER_CPU_TICK_EN (SCP_TIMER_BASE + 0x68)
+#define TIMER_CPU_TICK_RST_VAL (SCP_TIMER_BASE + 0x6c)
+#define TIMER_CPU_TICK_CUR_VAL (SCP_TIMER_BASE + 0x70)
+#define TIMER_CPU_TICK_IRQ_CTRL (SCP_TIMER_BASE + 0x74)
+#define TIMERCPU_TICK_IRQ_CLR (1 << 5)
+#define TIMER_CPU_TICK_IRQ_STATUS (1 << 4)
+#define TIMER_CPU_TICK_IRQ_EN (1 << 0)
+
+#define OSTIMER_CON (SCP_TIMER_BASE + 0x80)
+#define OSTIMER_INIT_L (SCP_TIMER_BASE + 0x84)
+#define OSTIMER_INIT_H (SCP_TIMER_BASE + 0x88)
+#define OSTIMER_CUR_L 0x60017008 /*(SCP_TIMER_BASE + 0x8C)*/
+#define OSTIMER_CUR_H 0x6001700C /*(SCP_TIMER_BASE + 0x90)*/
+#define OSTIMER_TVAL (SCP_TIMER_BASE + 0x94)
+#define OSTIMER_IRQ_ACK (SCP_TIMER_BASE + 0x98)
+#define OSTIMER_TICK_IRQ_CLR (1 << 5)
+#define OSTIMER_TICK_IRQ_STATUS (1 << 4)
+#define OSTIMER_TICK_IRQ_EN (1 << 0)
+
+#define OS_TIMER_LATCH_CTRL (SCP_TIMER_BASE + 0xA0)
+#define OS_TIMER_LATCH_VALUE_0 (SCP_TIMER_BASE + 0xA4)
+#define OS_TIMER_LATCH_VALUE_0_MSB (SCP_TIMER_BASE + 0xA8)
+#define OS_TIMER_LATCH_VALUE_1 (SCP_TIMER_BASE + 0xAC)
+#define OS_TIMER_LATCH_VALUE_1_MSB (SCP_TIMER_BASE + 0xB0)
+#define OS_TIMER_LATCH_VALUE_2 (SCP_TIMER_BASE + 0xB4)
+#define OS_TIMER_LATCH_VALUE_2_MSB (SCP_TIMER_BASE + 0xB8)
+
+/* AP side system counter frequence is 13MHz*/
+#ifdef CFG_FPGA
+#define AP_NS_PER_CNT (1000000000UL)/(6000000UL)
+#else
+#define AP_NS_PER_CNT (1000000000UL)/(13000000UL)
+#endif
+
+#define TIMER_EN (0x00)
+#define TIMER_CLK_SRC (0x00)
+#define TIMER_RST_VAL (0x04)
+#define TIMER_CUR_VAL_REG (0x08)
+#define TIMER_IRQ_CTRL_REG (0x0C)
+
+#define TIMER_CLK_SEL_REG (SCP_TIMER_BASE+0x40)
+
+//#define portNVIC_MTK_XGPT_REG (TIMER_BASE + 0x18)
+
+#define TIMER_ENABLE 1
+#define TIMER_DISABLE 0
+
+#define TIMER_IRQ_ENABLE 1
+#define TIMER_IRQ_DISABLE 0
+
+#define TIMER_IRQ_STA (0x1 << 4)
+#define TIMER_IRQ_CLEAR (0x1 << 5)
+
+/* TODO: Check this setting */
+#define TIMER_CLK_SRC_CLK_32K (0x00)
+#define TIMER_CLK_SRC_CLK_26M (0x01)
+#define TIMER_CLK_SRC_BCLK (0x02)
+#define TIMER_CLK_SRC_PCLK (0x03)
+
+#define TIMER_CLK_SRC_MASK 0x3
+#define TIMER_CLK_SRC_SHIFT 4
+
+#define DELAY_TIMER_1US_TICK ((unsigned int)1) //(32KHz)
+#ifdef CFG_FPGA
+#define DELAY_TIMER_1MS_TICK ((unsigned int)34) //(33.3KHz)
+#else
+#define DELAY_TIMER_1MS_TICK ((unsigned int)33) //(32KHz)
+#endif
+
+// 32KHz: 31us = 1 counter
+#define TIME_TO_TICK_US(us) ((us)*DELAY_TIMER_1US_TICK)
+// 32KHz: 1ms = 33 counter
+#define TIME_TO_TICK_MS(ms) ((ms)*DELAY_TIMER_1MS_TICK)
+
+#ifdef CFG_FPGA
+#define COUNT_TO_TICK(x) ((x)/20) //20KHz, 1 tick is 20 counters
+#else
+#define COUNT_TO_TICK(x) ((x)/32) //32KHz, 1 tick is 32 counters
+#endif
+
+#define US_LIMIT 31 /* udelay's parameter limit */
+#define MAX_RG_BIT 0xffffffff
+
+#define RT_TIMER TMR0
+#define RT_TIMER_RSTVAL MAX_RG_BIT
+#define TICK_TIMER TMR1
+#define TICK_TIMER_RSTVAL MAX_RG_BIT
+#define DELAY_TIMER TMR2
+#define DELAY_TIMER_RSTVAL MAX_RG_BIT
+#define DMGR_TIMER TMR3
+#define DMGR_TIMER_RSTVAL TIME_TO_TICK_MS(1)
+#define CHRE_TIMER TMR4
+#define CHRE_TIMER_RSTVAL MAX_RG_BIT
+#define UNUSE2_TIMER TMR5
+#define UNUSE2_TIMER_RSTVAL MAX_RG_BIT
+
+typedef unsigned long long mt_time_t;
+typedef void (*platform_timer_callback) (void *arg);
+
+struct timer_device {
+ unsigned int id;
+ unsigned int base_addr;
+ struct INTC_IRQ irq;
+};
+
+/*************************End*****************************************/
+#if defined(CFG_MED_MCU_DVT)
+struct timer_device *get_dev_by_id(unsigned int id);
+void timer_enable_set(struct timer_device *dev);
+void timer_enable_irq(struct timer_device *dev);
+void timer_disable_set(struct timer_device *dev);
+void timer_set_clk(struct timer_device *dev, unsigned int clksrc);
+void timer_set_rstval(struct timer_device *dev, unsigned int val);
+unsigned long timer_get_curval(struct timer_device *dev);
+#endif
+void mdelay(unsigned long msec);
+void udelay(unsigned long usec);
+void mt_platform_timer_init(void);
+int platform_set_periodic_timer(platform_timer_callback callback, void *arg,
+ mt_time_t interval);
+unsigned long long read_xgpt_stamp_ns(void);
+unsigned long long timer_get_global_timer_tick(void);
+unsigned long long get_boot_time_ns(void);
+struct timer_device *id_to_dev(unsigned int id);
+
+void platform_set_cpu_tick(int interval);
+void timer_cpu_tick_irq_ack(void);
+void platform_cpu_tick_disable(void);
+void platform_cpu_tick_enable(void);
+
+#define OSTIMER_LATCH_TIME_SUPPORT
+
+#ifdef OSTIMER_LATCH_TIME_SUPPORT
+int alloc_latch_time(void);
+void free_latch_time(int id);
+void enable_latch_time(int id, int irq);
+void disable_latch_time(int id);
+uint64_t get_latch_time_timestamp(int id);
+#else
+static inline int alloc_latch_time(void)
+{
+ return -1;
+}
+
+static inline void free_latch_time(int id)
+{
+}
+
+static inline void enable_latch_time(int id, int irq)
+{
+}
+
+static inline void disable_latch_time(int id)
+{
+}
+
+static inline uint64_t get_latch_time_timestamp(int id)
+{
+ return 0;
+}
+#endif
+
+unsigned int program_hwtimer(void (*callback)(void), uint64_t diffTime);
+
+#endif /* !__XGPT_H__ */
diff --git a/src/tinysys/medmcu/drivers/common/xgpt/xgpt.c b/src/tinysys/medmcu/drivers/common/xgpt/xgpt.c
new file mode 100644
index 0000000..dd5d66c
--- /dev/null
+++ b/src/tinysys/medmcu/drivers/common/xgpt/xgpt.c
@@ -0,0 +1,790 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2015. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ */
+
+#include <driver_api.h>
+#include <tinysys_reg.h>
+#include <interrupt.h>
+#include <xgpt.h>
+#include <FreeRTOS.h>
+#include <semphr.h>
+#include <FreeRTOSConfig.h>
+
+#include <task.h>
+
+#ifdef CFG_VCORE_DVFS_SUPPORT
+#include <dvfs.h>
+#include <sleep.h>
+#endif
+#include <stdlib.h>
+#include <string.h>
+
+#include "mtk_atomic.h"
+#include "encoding.h"
+
+unsigned int g_timer_base;
+static struct timer_device scp_timer[NR_TMRS];
+static platform_timer_callback tick_timer_callback;
+static void *tick_timer_callback_arg;
+
+#ifdef CFG_CHRE_SUPPORT
+static platform_timer_callback chre_timer_callback;
+static void *chre_timer_callback_arg;
+#endif
+
+#define UNUSED(x) (void)(x)
+
+// 200MHz setting
+#define MCLK_RATE 200*1024*1024 //200M
+#define MCLK_1TICK_NS 5 // 1/(200M) = 5nsec
+
+#define SEC_TO_NSEC (1000 * 1000 * 1000)
+
+#ifdef CFG_FPGA
+#define TIMER_TICK_RATE 20480
+#else
+#define TIMER_TICK_RATE 32768
+#endif
+
+/* multiplier and shifter for 13MHz global timer */
+#ifdef CFG_FPGA
+#define OSTIMER_TIMER_MULT (419430400) /* 5M clk, 1000000000/(5*1000*1000) <<OSTIMER_TIMER_SHIFT */
+#else
+#define OSTIMER_TIMER_MULT (161319385)
+#endif
+#define OSTIMER_TIMER_SHIFT (21)
+
+#ifdef OSTIMER_LATCH_TIME_SUPPORT
+void init_latch_time(void);
+#else
+void init_latch_time(void)
+{
+}
+#endif
+
+struct timer_device *id_to_dev(unsigned int id)
+{
+ return id < NR_TMRS ? scp_timer + id : 0;
+}
+
+static void __timer_enable_irq(struct timer_device *dev)
+{
+ DRV_SetReg32(dev->base_addr + TIMER_IRQ_CTRL_REG, 0x1);
+}
+
+static void __timer_disable_irq(struct timer_device *dev)
+{
+ DRV_ClrReg32(dev->base_addr + TIMER_IRQ_CTRL_REG, 0x1);
+}
+
+static void __timer_ack_irq(struct timer_device *dev)
+{
+ DRV_SetReg32(dev->base_addr + TIMER_IRQ_CTRL_REG, TIMER_IRQ_CLEAR);
+}
+
+static void __timer_enable(struct timer_device *dev)
+{
+ DRV_SetReg32(dev->base_addr + TIMER_EN, 0x1);
+}
+
+static void __timer_disable(struct timer_device *dev)
+{
+ DRV_ClrReg32(dev->base_addr + TIMER_EN, 0x1);
+}
+
+static void __timer_set_clk(struct timer_device *dev, unsigned int clksrc)
+{
+ DRV_ClrReg32(dev->base_addr + TIMER_CLK_SRC,
+ TIMER_CLK_SRC_MASK << TIMER_CLK_SRC_SHIFT);
+ DRV_SetReg32(dev->base_addr + TIMER_CLK_SRC,
+ clksrc << TIMER_CLK_SRC_SHIFT);
+}
+
+static void __timer_set_rstval(struct timer_device *dev, unsigned int val)
+{
+ DRV_WriteReg32(dev->base_addr + TIMER_RST_VAL, val);
+}
+
+static void __timer_get_curval(struct timer_device *dev, unsigned long *ptr)
+{
+ *ptr = DRV_Reg32(dev->base_addr + TIMER_CUR_VAL_REG);
+}
+
+static void __timer_reset(struct timer_device *dev)
+{
+ __timer_disable(dev);
+ __timer_disable_irq(dev);
+ __timer_ack_irq(dev);
+ __timer_set_rstval(dev, 0);
+ __timer_set_clk(dev, TIMER_CLK_SRC_CLK_32K);
+}
+
+#if defined(CFG_MED_MCU_DVT)
+struct timer_device *get_dev_by_id(unsigned int id)
+{
+ return id_to_dev(id);
+}
+
+void timer_enable_irq(struct timer_device *dev)
+{
+ __timer_enable_irq(dev);
+}
+
+void timer_enable_set(struct timer_device *dev)
+{
+ __timer_enable(dev);
+}
+
+void timer_disable_set(struct timer_device *dev)
+{
+ __timer_disable(dev);
+}
+
+void timer_set_clk(struct timer_device *dev, unsigned int clksrc)
+{
+ __timer_set_clk(dev, clksrc);
+}
+
+void timer_set_rstval(struct timer_device *dev, unsigned int val)
+{
+ __timer_set_rstval(dev, val);
+}
+
+unsigned long timer_get_curval(struct timer_device *dev)
+{
+ unsigned long val;
+
+ __timer_get_curval(dev, &val);
+
+ return val;
+}
+#endif
+
+/* get ostimer counter */
+unsigned long long timer_get_global_timer_tick(void)
+{
+ unsigned long long val = 0;
+ unsigned long high = 0, low = 0;
+ unsigned long long new_high = 0, new_low = 0;
+
+ if (!is_in_isr())
+ taskENTER_CRITICAL();
+
+ low = DRV_Reg32(OSTIMER_CUR_L);
+ high = DRV_Reg32(OSTIMER_CUR_H);
+
+ if (!is_in_isr())
+ taskEXIT_CRITICAL();
+
+ new_high = high;
+ new_low = low;
+ val =
+ ((new_high << 32) & 0xFFFFFFFF00000000ULL) | (new_low &
+ 0x00000000FFFFFFFFULL);
+
+ return val;
+}
+
+static SYNC_SECTION unsigned long long ostimer_init_cycle;
+static unsigned long long ostimer_last_cycle;
+static unsigned int delay_get_current_tick(void);
+
+/* get ostimer timestamp */
+unsigned long long get_boot_time_ns(void)
+{
+ unsigned long long high = 0, low = 0;
+ unsigned long long cycle = 0;
+ unsigned long long timestamp = 0;
+
+ if (!is_in_isr())
+ taskENTER_CRITICAL();
+
+#ifdef CFG_USE_32K_HW_TIMER
+ low = DELAY_TIMER_RSTVAL - delay_get_current_tick();
+#else
+ low = DRV_Reg32(OSTIMER_CUR_L);
+ high = DRV_Reg32(OSTIMER_CUR_H);
+#endif
+
+ cycle = ((high << 32) & 0xFFFFFFFF00000000ULL) |
+ (low & 0x00000000FFFFFFFFULL);
+
+#ifndef CFG_USE_32K_HW_TIMER
+ if (cycle < ostimer_last_cycle)
+ cycle = ostimer_last_cycle + 1;
+#endif
+ ostimer_last_cycle = cycle;
+
+ if (!is_in_isr())
+ taskEXIT_CRITICAL();
+
+#ifndef CFG_USE_32K_HW_TIMER
+ cycle = cycle - ostimer_init_cycle;
+ high = (cycle >> 32) & 0x00000000FFFFFFFFULL;
+#endif
+ low = cycle & 0x00000000FFFFFFFFULL;
+
+#ifdef CFG_USE_32K_HW_TIMER
+ timestamp = (cycle * 1000000000) >> 15;
+#else
+ timestamp =
+ (((unsigned long long) high * OSTIMER_TIMER_MULT) << 11) +
+ (((unsigned long long) low *
+ OSTIMER_TIMER_MULT) >> OSTIMER_TIMER_SHIFT);
+#endif
+
+ return timestamp;
+}
+
+unsigned long long read_xgpt_stamp_ns(void)
+{
+ return get_boot_time_ns();
+}
+
+static void tick_timer_irq_handle(void);
+static void __clr_all_tmr_irq_ack(void);
+void mt_platform_timer_init(void)
+{
+ int i;
+ struct timer_device *dev;
+ g_timer_base = XGPT_BASE_REG;
+ /* enable clock */
+ DRV_SetReg32(TIMER_IN_CLK, (TMR_MCLK_CG | TMR_BCLK_CG));
+
+ for (i = 0; i < NR_TMRS; i++) {
+ scp_timer[i].id = i;
+ scp_timer[i].base_addr = SCP_TIMER_BASE + 0x10 * i;
+ }
+
+ scp_timer[0].irq = INTC_IRQ_XGPT0;
+ scp_timer[1].irq = INTC_IRQ_XGPT1;
+ scp_timer[2].irq = INTC_IRQ_XGPT2;
+ scp_timer[3].irq = INTC_IRQ_XGPT3;
+ scp_timer[4].irq = INTC_IRQ_XGPT4;
+ scp_timer[5].irq = INTC_IRQ_XGPT5;
+
+ __clr_all_tmr_irq_ack();
+
+ // reset timer
+ for (i = 0; i < NR_TMRS; i++) {
+ __timer_reset(&scp_timer[i]);
+ }
+
+ /* Setup timer to wakeup source for tickless mode to wakeup device. */
+ for (i = 0; i < NR_TMRS; i++) {
+ intc_irq_wakeup_set(&scp_timer[i].irq, 0x1);
+ }
+
+ /* enable delay GPT */
+ dev = id_to_dev(DELAY_TIMER);
+ __timer_set_rstval(dev, DELAY_TIMER_RSTVAL);
+ __timer_enable(dev);
+
+ mdelay(1);
+
+ dev = id_to_dev(TICK_TIMER);
+ intc_irq_request(&dev->irq, (void *) tick_timer_irq_handle, (void *) 0);
+
+ if (mrv_read_csr(CSR_MHARTID) == 0) {
+ ostimer_init_cycle = timer_get_global_timer_tick();
+ printf("[ostimer] ostimer_init_cycle = %llu cycles\n",
+ ostimer_init_cycle);
+ }
+ init_latch_time();
+}
+
+static void tick_timer_irq(void *arg)
+{
+ UNUSED(arg);
+
+ /*diff with before */
+ if (tick_timer_callback != NULL)
+ return tick_timer_callback(tick_timer_callback_arg);
+}
+
+static void tick_timer_irq_handle(void)
+{
+ struct timer_device *dev = id_to_dev(TICK_TIMER);
+
+ __timer_disable(dev);
+ __timer_disable_irq(dev);
+ __timer_ack_irq(dev);
+ tick_timer_irq(0);
+
+ return;
+}
+
+int platform_set_periodic_timer(platform_timer_callback callback, void *arg,
+ mt_time_t interval)
+{
+ struct timer_device *dev;
+ unsigned long long tmp_64 = 0;
+ unsigned long long interval_tmp = (unsigned long long) interval;
+
+ tick_timer_callback = callback;
+ tick_timer_callback_arg = arg;
+
+ tmp_64 = (unsigned long long) TIMER_TICK_RATE *interval_tmp;
+ tmp_64 = (tmp_64 / 1000ULL - 32);
+ dev = id_to_dev(TICK_TIMER);
+ __timer_disable(dev);
+
+ if (interval >= 1)
+ __timer_set_rstval(dev, (unsigned int) tmp_64); //0.3ms(sw)+0.7ms(hw wake)
+ else
+ __timer_set_rstval(dev, 1);
+ __timer_enable_irq(dev);
+
+ __timer_enable(dev);
+
+ return 0;
+}
+
+#ifdef CFG_CHRE_SUPPORT
+static void chre_timer_stop(void)
+{
+ struct timer_device *dev = id_to_dev(CHRE_TIMER);
+
+ __timer_disable(dev);
+}
+
+static void chre_timer_irq(void *arg)
+{
+ (void)*arg;
+ if (chre_timer_callback != NULL)
+ return chre_timer_callback(chre_timer_callback_arg);
+}
+
+static unsigned int chre_timer_irq_handle(void *arg)
+{
+ struct timer_device *dev = id_to_dev(CHRE_TIMER);
+ __timer_disable(dev);
+ __timer_disable_irq(dev);
+ __timer_ack_irq(dev);
+ chre_timer_irq(0);
+
+ return 0;
+}
+
+static int platform_set_periodic_timer_chre(platform_timer_callback callback,
+ void *arg, mt_time_t interval_ns)
+{
+ struct timer_device *dev;
+ unsigned long long interval_tick = 0;
+
+ chre_timer_callback = callback;
+ chre_timer_callback_arg = arg;
+
+ /* calculate how many ticks shall we wait */
+ interval_tick =
+ (interval_ns / 1000) * (unsigned long long) TIMER_TICK_RATE /
+ 1000000ULL;
+
+ dev = id_to_dev(CHRE_TIMER);
+
+ /* setup 1-tick timer if required tick is < 1 */
+ if (interval_tick >= 1)
+ __timer_set_rstval(dev, (unsigned int) interval_tick);
+ else
+ __timer_set_rstval(dev, 1);
+
+ __timer_enable_irq(dev);
+
+ intc_irq_request(&dev->irq, chre_timer_irq_handle, (void *)0);
+
+ __timer_enable(dev);
+
+ return 0;
+}
+#endif
+#if 1 // (RV only)
+void timer_cpu_tick_irq_ack(void)
+{
+ DRV_WriteReg32(TIMER_CPU_TICK_IRQ_CTRL, TIMERCPU_TICK_IRQ_CLR);
+}
+
+void platform_cpu_tick_disable(void)
+{
+ DRV_ClrReg32(GENERAL_CTRL, B_CPU_TIMER_INT_EN);
+}
+
+void platform_cpu_tick_enable(void)
+{
+ DRV_SetReg32(GENERAL_CTRL, B_CPU_TIMER_INT_EN);
+}
+
+/* interval: timer for systick clock */
+void platform_set_cpu_tick(int interval)
+{
+ DRV_WriteReg32(TIMER_CPU_TICK_RST_VAL, interval);
+ DRV_WriteReg32(TIMER_CPU_TICK_IRQ_CTRL,
+ TIMERCPU_TICK_IRQ_CLR | TIMER_CPU_TICK_IRQ_EN);
+ DRV_WriteReg32(TIMER_CPU_TICK_EN, 1);
+}
+
+static void __clr_all_tmr_irq_ack(void)
+{
+ /* clr tmr0~5 */
+ __timer_ack_irq(id_to_dev(TMR0));
+ __timer_ack_irq(id_to_dev(TMR1));
+ __timer_ack_irq(id_to_dev(TMR2));
+ __timer_ack_irq(id_to_dev(TMR3));
+ __timer_ack_irq(id_to_dev(TMR4));
+ __timer_ack_irq(id_to_dev(TMR5));
+ /* clr cpu tick */
+ timer_cpu_tick_irq_ack();
+ /* clr os timer */
+ DRV_WriteReg32(OSTIMER_IRQ_ACK, OSTIMER_TICK_IRQ_CLR);
+}
+#endif
+
+static unsigned int delay_get_current_tick(void)
+{
+ unsigned long current_count;
+ struct timer_device *dev = id_to_dev(DELAY_TIMER);
+
+ __timer_get_curval(dev, ¤t_count);
+ return current_count;
+}
+
+static int check_timeout_tick(unsigned int start_tick,
+ unsigned int timeout_tick)
+{
+ //register unsigned int cur_tick;
+ //register unsigned int elapse_tick;
+ unsigned int cur_tick;
+ unsigned int elapse_tick;
+ // get current tick
+ cur_tick = delay_get_current_tick();
+
+ // check elapse time, down counter
+ if (start_tick >= cur_tick) {
+ elapse_tick = start_tick - cur_tick;
+ } else {
+ elapse_tick = (DELAY_TIMER_RSTVAL - cur_tick) + start_tick;
+ }
+ // check if timeout
+ if (timeout_tick <= elapse_tick) {
+ // timeout
+ return 1;
+ }
+
+ return 0;
+}
+
+static unsigned int time2tick_us(unsigned int time_us)
+{
+ return TIME_TO_TICK_US(time_us);
+}
+
+static unsigned int time2tick_ms(unsigned int time_ms)
+{
+ return TIME_TO_TICK_MS(time_ms);
+}
+
+//===========================================================================
+// busy wait
+//===========================================================================
+static void busy_wait_us(unsigned int timeout_us)
+{
+ unsigned int start_tick, timeout_tick;
+
+ // get timeout tick
+ timeout_tick = time2tick_us(timeout_us);
+ start_tick = delay_get_current_tick();
+
+ // wait for timeout
+ while (!check_timeout_tick(start_tick, timeout_tick)) ;
+}
+
+static void busy_wait_ms(unsigned int timeout_ms)
+{
+ unsigned int start_tick, timeout_tick;
+
+ // get timeout tick
+ timeout_tick = time2tick_ms(timeout_ms);
+ start_tick = delay_get_current_tick();
+
+ // wait for timeout
+ while (!check_timeout_tick(start_tick, timeout_tick)) ;
+}
+
+/* delay msec mseconds */
+void mdelay(unsigned long msec)
+{
+ busy_wait_ms(msec);
+}
+
+/* delay usec useconds */
+void udelay(unsigned long usec)
+{
+ unsigned long usec_t;
+ if (usec < US_LIMIT) {
+ //PRINTF_D("usec < 31us, error parameter\n");
+ busy_wait_us(1);
+ } else {
+ usec_t = usec / 31 + 1;
+ busy_wait_us(usec_t);
+ }
+}
+
+#ifdef CFG_CHRE_SUPPORT
+//===========================================================================
+// chre feature
+//===========================================================================
+extern uint64_t cpuIntsOff(void);
+extern void cpuIntsRestore(uint64_t state);
+extern TaskHandle_t CHRE_TaskHandle;
+
+bool platSleepClockRequest(uint64_t wakeupTime, uint32_t maxJitterPpm,
+ uint32_t maxDriftPpm, uint32_t maxErrTotalPpm);
+static void chre_timer_wakeup(void *arg)
+{
+ extern int timIntHandler(void);
+ timIntHandler();
+ if (xTaskResumeFromISR(CHRE_TaskHandle) == pdTRUE)
+ portYIELD_WITHIN_API();
+}
+
+bool platSleepClockRequest(uint64_t wakeupTime, uint32_t maxJitterPpm,
+ uint32_t maxDriftPpm, uint32_t maxErrTotalPpm)
+{
+ (void)maxJitterPpm;
+ (void)maxDriftPpm;
+ (void)maxErrTotalPpm;
+ // uint64_t intState, curTime;
+ uint64_t curTime;
+ unsigned long long diff_time;
+ chre_timer_stop();
+ if (wakeupTime == 0) {
+ return 1;
+ }
+ curTime = (uint64_t) read_xgpt_stamp_ns();
+
+ if (wakeupTime && curTime >= wakeupTime)
+ return 0;
+
+ /* diff_time unit: ns */
+ diff_time = wakeupTime - curTime;
+
+ // intState = cpuIntsOff();
+ // TODO: set an actual alarm here so that if we keep running and do not sleep till this is due,
+ // we still fire an interrupt for it!
+ platform_set_periodic_timer_chre(chre_timer_wakeup, NULL, diff_time);
+ // cpuIntsRestore(intState);
+ return 1;
+}
+#endif
+
+void (*rttimercbk)(void);
+
+static unsigned int rt_timer_irq_handler(void *arg)
+{
+ struct timer_device *dev = id_to_dev(RT_TIMER);
+ __timer_disable(dev);
+ __timer_disable_irq(dev);
+ __timer_ack_irq(dev);
+ if (rttimercbk != NULL)
+ rttimercbk();
+ return 0;
+}
+
+unsigned int program_hwtimer(void (*callback)(void), uint64_t diff_time)
+{
+ struct timer_device *dev = id_to_dev(RT_TIMER);
+ unsigned long long interval_tick = 0;
+
+ __timer_disable(dev);
+
+ if (diff_time == 0) {
+ return 1;
+ }
+ /* calculate how many ticks shall we wait */
+ interval_tick =
+ (diff_time / 1000) * (unsigned long long)TIMER_TICK_RATE /
+ 1000000ULL;
+
+ /* setup 1-tick timer if required tick is < 1 */
+ if (interval_tick >= 1)
+ __timer_set_rstval(dev, (unsigned int)interval_tick);
+ else
+ __timer_set_rstval(dev, 1);
+
+ __timer_enable_irq(dev);
+
+ rttimercbk = callback;
+
+ intc_irq_request(&dev->irq, rt_timer_irq_handler, (void *)0);
+
+ __timer_enable(dev);
+
+ return 1;
+}
+
+#ifdef OSTIMER_LATCH_TIME_SUPPORT
+#define MAX_LATCH_TIMER 3
+#define CRTL_BIT_SHIFT 8
+#define IRQ_BIT_SHIFT 0
+#define ENABLE_BIT_SHIFT 5
+#define CYC_BASE_SHIFT 8
+struct latch_time_struct {
+ unsigned int ctrl_base;
+ unsigned int enable_offset;
+ unsigned int irq_offset;
+ unsigned int cyc_low_base;
+ unsigned int cyc_high_base;
+};
+static struct latch_time_struct latch_time[MAX_LATCH_TIMER];
+static unsigned int latch_time_used[MAX_LATCH_TIMER];
+void init_latch_time(void)
+{
+ int i = 0;
+ for (i = 0; i < MAX_LATCH_TIMER; ++i) {
+ latch_time[i].ctrl_base = OS_TIMER_LATCH_CTRL;
+ latch_time[i].enable_offset =
+ i * CRTL_BIT_SHIFT + ENABLE_BIT_SHIFT;
+ latch_time[i].irq_offset = i * CRTL_BIT_SHIFT + IRQ_BIT_SHIFT;
+ latch_time[i].cyc_low_base =
+ OS_TIMER_LATCH_VALUE_0 + i * CYC_BASE_SHIFT;
+ latch_time[i].cyc_high_base = latch_time[i].cyc_low_base + 4;
+
+ latch_time_used[i] = 0;
+ }
+ DRV_WriteReg32(OS_TIMER_LATCH_CTRL, 0);
+}
+
+void enable_latch_time(int id, int irq)
+{
+ unsigned int base = 0, control = 0;
+
+ if (id < 0 || id >= MAX_LATCH_TIMER)
+ return;
+ if (irq > 0x1f)
+ return;
+ base = latch_time[id].ctrl_base;
+ control = ((1 << latch_time[id].enable_offset) |
+ (irq << latch_time[id].irq_offset));
+ if (!is_in_isr())
+ taskENTER_CRITICAL();
+ DRV_SetReg32(base, control);
+ if (!is_in_isr())
+ taskEXIT_CRITICAL();
+}
+
+void disable_latch_time(int id)
+{
+ unsigned int base = 0, control = 0;
+
+ if (id < 0 || id >= MAX_LATCH_TIMER)
+ return;
+ base = latch_time[id].ctrl_base;
+ control = ((0 << latch_time[id].enable_offset) |
+ (0 << latch_time[id].irq_offset));
+ if (!is_in_isr())
+ taskENTER_CRITICAL();
+ DRV_SetReg32(base, control);
+ if (!is_in_isr())
+ taskEXIT_CRITICAL();
+}
+
+int alloc_latch_time(void)
+{
+ int i = 0, id = -1;
+ if (!is_in_isr())
+ taskENTER_CRITICAL();
+ for (i = 0; i < MAX_LATCH_TIMER; ++i) {
+ if (latch_time_used[i] == 0) {
+ latch_time_used[i] = 1;
+ id = i;
+ break;
+ }
+ }
+ if (!is_in_isr())
+ taskEXIT_CRITICAL();
+ return id;
+}
+
+void free_latch_time(int id)
+{
+ if (id < 0 || id >= MAX_LATCH_TIMER)
+ return;
+ if (!is_in_isr())
+ taskENTER_CRITICAL();
+ latch_time_used[id] = 0;
+ if (!is_in_isr())
+ taskEXIT_CRITICAL();
+}
+
+static unsigned long long get_latch_time_counter(struct latch_time_struct *base)
+{
+ unsigned long long val;
+ unsigned long high_1, high_2, low_1, low_2;
+
+ if (!is_in_isr())
+ taskENTER_CRITICAL();
+
+ low_1 = DRV_Reg32(base->cyc_low_base);
+ high_1 = DRV_Reg32(base->cyc_high_base);
+ low_2 = DRV_Reg32(base->cyc_low_base);
+ high_2 = DRV_Reg32(base->cyc_high_base);
+
+ if (low_2 < low_1) {
+ high_1 = high_2;
+ low_1 = low_2;
+ }
+
+ val = (((unsigned long long) high_1 << 32) & 0xFFFFFFFF00000000) |
+ ((unsigned long long) low_1 & 0x00000000FFFFFFFF);
+
+ if (!is_in_isr())
+ taskEXIT_CRITICAL();
+
+ return val;
+}
+
+uint64_t get_latch_time_timestamp(int id)
+{
+ unsigned long long cycle = 0;
+ unsigned long long high = 0, low = 0;
+ uint64_t timestamp = 0;
+
+ if (id < 0 || id >= MAX_LATCH_TIMER)
+ return 0;
+ cycle = get_latch_time_counter(&latch_time[id]);
+
+ cycle = cycle - ostimer_init_cycle;
+ high = (cycle >> 32) & 0x00000000FFFFFFFFULL;
+ low = cycle & 0x00000000FFFFFFFFULL;
+ timestamp = (((unsigned long long) high * OSTIMER_TIMER_MULT) << 11) +
+ (((unsigned long long) low *
+ OSTIMER_TIMER_MULT) >> OSTIMER_TIMER_SHIFT);
+ return timestamp;
+}
+#endif
diff --git a/src/tinysys/medmcu/middleware/logger/inc/mt_logger.h b/src/tinysys/medmcu/middleware/logger/inc/mt_logger.h
new file mode 100644
index 0000000..c33fcaf
--- /dev/null
+++ b/src/tinysys/medmcu/middleware/logger/inc/mt_logger.h
@@ -0,0 +1,53 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
+ * ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
+ * THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
+ * SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
+ * RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
+ * FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
+ * WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
+ * AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
+ * RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation
+ * ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
+ * subject to any receiver\'s applicable license agreements with MediaTek Inc.
+ */
+#ifndef _MT_LOGGER_H_
+#define _MT_LOGGER_H_
+
+#define LOGGER_BUFFERABLE 1 /* log buffer at SRAM */
+#define LOGGER_BOOTLOG_SUPPORT 1 /* bootlog enabled */
+#define LOGGER_MAX_QUEUE 2 /* maximum timer queue number */
+
+#if LOGGER_BUFFERABLE
+#define BUF_LEN 3072 /* 3KB */
+#endif
+
+/* .share section should be zero filled */
+#define PLATSEC __attribute__ ((section (".sync")))
+
+void logger_init_handler(unsigned int id, void *prdata, void *data);
+
+#endif
diff --git a/src/tinysys/medmcu/middleware/logger/mt_logger.c b/src/tinysys/medmcu/middleware/logger/mt_logger.c
new file mode 100644
index 0000000..655389f
--- /dev/null
+++ b/src/tinysys/medmcu/middleware/logger/mt_logger.c
@@ -0,0 +1,243 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
+ * ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
+ * THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
+ * SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
+ * RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
+ * FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
+ * WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
+ * AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
+ * RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation
+ * ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
+ * subject to any receiver\'s applicable license agreements with MediaTek Inc.
+ */
+
+#include "encoding.h"
+#include "stdint.h"
+#include "logger.h"
+#include "mt_printf.h"
+
+#ifdef CFG_VCORE_DVFS_SUPPORT
+#include <dvfs.h>
+#endif
+
+#ifdef CFG_DMA_SUPPORT
+#include "dma_api.h"
+#endif
+
+#ifdef CFG_COMMON_IPI_SUPPORT
+#include <ipi.h>
+#include "ipi_id.h"
+#endif
+
+#define LOGGER_WAIT_DRAM 3
+
+
+extern unsigned int logger_update_dram_ready_time(void);
+extern void logger_update_post_process(void);
+extern unsigned int logger_addr_remap(unsigned int addr);
+extern void logger_addr_unremap(unsigned int addr);
+extern int logger_update_notify_ap(void);
+extern void logger_wake_unlock(void);
+extern void logger_ipi_registration(LAST_LOG_INFO logger_info);
+extern void logger_enter_critical(void);
+extern void logger_exit_critical(void);
+extern void logger_wake_lock(void);
+extern void logger_dcache_flush(void *addr, uint32_t size);
+extern void logger_dcache_invalidate(void *addr, uint32_t size);
+extern unsigned int logger_update_dma(unsigned int src_buf,
+ unsigned int src_r_pos,
+ unsigned int dst_buf,
+ unsigned int dst_w_pos,
+ unsigned int src_len,
+ unsigned int dst_len);
+
+extern uint32_t ap_to_scp(uint32_t ap_addr);
+
+struct logger_init_msg {
+ unsigned int addr;
+ unsigned int size;
+} msg_logger_init;
+
+void *msg_logger_en, *msg_logger_wk;
+
+#ifdef CFG_WAKELOCK_SUPPORT
+wakelock_t scp_logger_wakelock;
+#endif
+
+void logger_dcache_flush(void *addr, uint32_t size) {}
+void logger_dcache_invalidate(void *addr, uint32_t size) {}
+void logger_addr_unremap(unsigned int addr) {}
+
+#ifdef CFG_COMMON_IPI_SUPPORT
+static void logger_wakeup_handler(unsigned int id, void *prdata, void *data)
+{
+ unsigned int wakeup;
+
+ wakeup = *(unsigned int *)data;
+ logger_update_wakeup_ap(wakeup);
+}
+
+static void logger_enable_handler(unsigned int id, void *prdata, void *data)
+{
+ unsigned int enable;
+
+ enable = *(unsigned int *)data;
+ logger_update_enable(enable);
+}
+
+void logger_init_handler(unsigned int id, void *prdata, void *data)
+{
+ unsigned int ret;
+ struct logger_init_msg msg = *(struct logger_init_msg *)data;
+
+ ret = logger_dram_register(msg.addr, msg.size);
+ if (ret == 0) {
+ configASSERT(0);
+ return;
+ }
+}
+#endif
+
+unsigned int logger_addr_remap(unsigned int addr)
+{
+#ifdef CFG_DMA_SUPPORT
+ return ap_to_scp(addr);
+#endif
+}
+
+unsigned int logger_update_dram_ready_time(void)
+{
+ unsigned int ret = 0;
+
+#ifdef CFG_VCORE_DVFS_SUPPORT
+ /* 0 go for rest of update, 1 go for postponding to next tick */
+ ret = dvfs_enable_DRAM_no_wait_for_logger(SCP_A_LOGGER_MEM_ID);
+#endif
+ return (ret ? LOGGER_WAIT_DRAM : 0);
+}
+
+void logger_update_post_process(void)
+{
+#ifdef CFG_VCORE_DVFS_SUPPORT
+ dvfs_disable_DRAM_no_wait_for_logger(SCP_A_LOGGER_MEM_ID);
+#endif
+}
+
+unsigned int logger_update_dma(unsigned int src_buf, unsigned int src_r_pos,
+ unsigned int dst_buf, unsigned int dst_w_pos,
+ unsigned int src_len, unsigned int dst_len)
+{
+#ifdef CFG_DMA_SUPPORT
+ DMA_RESULT ret = 0;
+
+ ret =
+ scp_dma_transaction(dst_buf + dst_w_pos, src_buf + src_r_pos,
+ src_len, LOGGER_DMA_ID, NO_RESERVED);
+
+ if (ret != DMA_RESULT_DONE) {
+ PRINTF_E("log dma trans fail%u\n", ret);
+ return 0;
+ }
+
+ return src_len;
+#endif
+}
+
+int logger_update_notify_ap(void)
+{
+#ifdef CFG_COMMON_IPI_SUPPORT
+ unsigned int magic = 0x5A5A5A5A;
+
+ if (!ipi_send(IPI_OUT_LOGGER_WAKEUP_1, &magic, sizeof(magic)/4, 0))
+ return 1;
+#endif
+ return 0;
+}
+
+void logger_ipi_registration(LAST_LOG_INFO logger_info)
+{
+#ifdef CFG_COMMON_IPI_SUPPORT
+ int ret;
+
+#ifdef CFG_LOG_FILTER
+ extern void set_log_filter(void);
+ struct mtk_mbox_queue_t msg_logger_flt;
+ ret = ipi_register(
+ IPI_IN_SCP_LOG_FILTER_1, set_log_filter, 0, &msg_logger_flt);
+ if (ret != IPI_ACTION_DONE)
+ PRINTF_E("register log filter ipi failed, %d\n", ret);
+#endif // CFG_LOG_FILTER
+
+ ret = ipi_register(
+ IPI_IN_LOGGER_INIT_1, logger_init_handler, 0, &msg_logger_init);
+ if (ret != IPI_ACTION_DONE)
+ PRINTF_E("register log init ipi failed, %d\n", ret);
+
+ /* cmd for disable/enable log and wakeup flag */
+ ret = ipi_register(
+ IPI_IN_LOGGER_ENABLE_1, logger_enable_handler, 0, &msg_logger_en);
+ if (ret != IPI_ACTION_DONE)
+ PRINTF_E("register log enable ipi failed, %d\n", ret);
+
+ ret = ipi_register(
+ IPI_IN_LOGGER_WAKEUP_1, logger_wakeup_handler, 0, &msg_logger_wk);
+ if (ret != IPI_ACTION_DONE)
+ PRINTF_E("register log wakeup ipi failed, %d\n", ret);
+
+ /*send ipi */
+ while (ipi_send(IPI_OUT_LOGGER_INIT_1, &logger_info, sizeof(logger_info)/4, 0))
+ ;
+
+#endif
+}
+
+void logger_wake_unlock(void)
+{
+#ifdef CFG_WAKELOCK_SUPPORT
+ wake_unlock_FromISR(&scp_logger_wakelock);
+#endif
+}
+
+void logger_wake_lock(void)
+{
+#ifdef CFG_WAKELOCK_SUPPORT
+ /*wakelock init */
+ wake_lock_init(&logger_wakelock, "logwk");
+ /*logger wake lock until receive AP side DRAM info. */
+ wake_lock(&logger_wakelock);
+#endif
+}
+
+void logger_enter_critical(void)
+{
+ taskENTER_CRITICAL();
+}
+
+void logger_exit_critical(void)
+{
+ taskEXIT_CRITICAL();
+}
diff --git a/src/tinysys/medmcu/middleware/pbfr/inc/mt_pbfr.h b/src/tinysys/medmcu/middleware/pbfr/inc/mt_pbfr.h
new file mode 100644
index 0000000..ea823ea
--- /dev/null
+++ b/src/tinysys/medmcu/middleware/pbfr/inc/mt_pbfr.h
@@ -0,0 +1,85 @@
+/* Copyright Statement:
+ *
+ * @2015 MediaTek Inc. All rights reserved.
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek Inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE.
+ */
+#ifndef _MT_PBFR_H_
+#define _MT_PBFR_H_
+
+#include "encoding.h"
+
+#define PBFR_STOP 0
+#define PBFR_START 1
+#define PBFR_REPORT 2
+
+#if defined(P_MODE_0) // task/RTOS in machine mode
+#define read_mcause() mrv_read_csr(CSR_MCAUSE)
+#ifdef MRV55
+#define read_micause() mrv_read_csr(MRV_VIC_MICAUSE_G)
+#else
+#define read_micause() mrv_read_csr(MRV_VIC_MICAUSE)
+#endif
+#elif defined(P_MODE_1) // task/RTOS in user mode
+#define read_mcause() (unsigned long)syscall(SYS_get_csr, CSR_MCAUSE, 0, 0)
+#ifdef MRV55
+#define read_micause() (unsigned long)syscall(SYS_get_csr, MRV_VIC_MICAUSE_G, 0, 0)
+#else
+#define read_micause() (unsigned long)syscall(SYS_get_csr, MRV_VIC_MICAUSE, 0, 0)
+#endif
+#endif /* P_MODE_0 */
+
+/* VIC_VEC indicates the last taken interrupt vector */
+#define read_taken_INT() ({ unsigned long __tmp_mc, __tmp_mic; \
+ __tmp_mc = read_mcause(); \
+ if(__tmp_mc == IRQ_M_EXT) { \
+ __tmp_mic = read_micause(); \
+ __tmp_mc |= (__tmp_mic << 16); \
+ } \
+ __tmp_mc;})
+
+unsigned long long pbfr_get_timestamp(int isr_ctx);
+
+#ifdef PBFR_SUPPORT_CACHE_COUNT
+unsigned long long pbfr_get_timestamp(int isr_ctx);
+void vPortEnableCacheCount(void);
+void vPortDisableCacheCount(void);
+unsigned long long vPortGetICacheAccessCount(void);
+unsigned long long vPortGetICacheMissCount(void);
+unsigned long long vPortGetDCacheAccessCount(void);
+unsigned long long vPortGetDCacheMissCount(void);
+void vPortHaltCacheCount(void);
+void vPortResumeCacheCount(void);
+#endif
+
+#ifdef PBFR_SUPPORT_IOSTALL
+void vPortEnableIOStallRate(void);
+void vPortDisableIOStallRate(void);
+int vPortGetIOStallRate(void);
+#endif
+
+#endif
diff --git a/src/tinysys/medmcu/middleware/pbfr/mt_pbfr.c b/src/tinysys/medmcu/middleware/pbfr/mt_pbfr.c
new file mode 100644
index 0000000..2b9fd2c
--- /dev/null
+++ b/src/tinysys/medmcu/middleware/pbfr/mt_pbfr.c
@@ -0,0 +1,70 @@
+/* Copyright Statement:
+ *
+ * @2015 MediaTek Inc. All rights reserved.
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek Inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE.
+ */
+
+#include "mt_pbfr.h"
+#include "xgpt.h"
+#include "encoding.h"
+
+#ifdef CFG_PBFR_SUPPORT
+# define CFG_PBFR_SUPPORT_TESTING
+#endif /* CFG_PBFR_SUPPORT */
+
+/* temporarily use OS tick timer as wall timer */
+#if defined(CFG_PBFR_SUPPORT_TESTING) && (configUSE_TICK_HOOK == 0)
+# error "Need configUSE_TICK_HOOK = 1 for PBFR testing"
+#endif /* CFG_PBFR_SUPPORT */
+
+unsigned long long pbfr_get_timestamp(int isr_ctx)
+{
+ unsigned long long ret;
+
+ (void) isr_ctx;
+ ret = read_xgpt_stamp_ns();
+ return ret;
+}
+
+#ifdef PBFR_SUPPORT_CACHE_COUNT
+unsigned long long pbfr_get_timestamp(int isr_ctx) { return 0; }
+void vPortEnableCacheCount(void) {}
+void vPortDisableCacheCount(void) {}
+unsigned long long vPortGetICacheAccessCount(void) { return 0; }
+unsigned long long vPortGetICacheMissCount(void){ return 0; }
+unsigned long long vPortGetDCacheAccessCount(void) { return 0; }
+unsigned long long vPortGetDCacheMissCount(void) { return 0; }
+void vPortHaltCacheCount(void) {}
+void vPortResumeCacheCount(void) {}
+#endif
+
+#ifdef PBFR_SUPPORT_IOSTALL
+void vPortEnableIOStallRate(void) {}
+void vPortDisableIOStallRate(void) {}
+int vPortGetIOStallRate(void) { return 0; }
+#endif
diff --git a/src/tinysys/medmcu/project/RV33_A/common/platform/inc/mt_driver_api.h b/src/tinysys/medmcu/project/RV33_A/common/platform/inc/mt_driver_api.h
new file mode 100644
index 0000000..27fca43
--- /dev/null
+++ b/src/tinysys/medmcu/project/RV33_A/common/platform/inc/mt_driver_api.h
@@ -0,0 +1,67 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2010. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek Software")
+ * have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+ * applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef _MT_DRIVER_API_H_
+#define _MT_DRIVER_API_H_
+
+#include "mt_riscvintrin.h"
+
+/* Wrap for chip supported operator */
+#define clz(val) mrv_clz(val)
+
+/* data only used by 1 core, so no need to duplicate data */
+#define CORE0_DATA __attribute__ ((section(".core0_only_data")))
+#define CORE1_DATA __attribute__ ((section(".core1_only_data")))
+
+
+#ifdef CFG_MRV_PATCH1
+static inline unsigned int _lr_read32_(unsigned int addr)
+{
+ unsigned int __tmp;
+ __asm volatile ("lr.w %0, (%1)\n"
+ : "=r"(__tmp)
+ : "r" (addr)
+ : "memory");
+ return __tmp;
+}
+
+#define readl(addr) _lr_read32_((unsigned int)addr)
+#define INREG32(addr) _lr_read32_((unsigned int)addr)
+#define DRV_Reg32(addr) _lr_read32_((unsigned int)addr)
+#define inreg32(addr) _lr_read32_((unsigned int)addr)
+#define drv_reg32(addr) _lr_read32_((unsigned int)addr)
+
+#endif
+#endif /* _MT_DRIVER_API_H_*/
diff --git a/src/tinysys/medmcu/project/RV33_A/common/platform/inc/mt_riscvintrin.h b/src/tinysys/medmcu/project/RV33_A/common/platform/inc/mt_riscvintrin.h
new file mode 100644
index 0000000..f15b763
--- /dev/null
+++ b/src/tinysys/medmcu/project/RV33_A/common/platform/inc/mt_riscvintrin.h
@@ -0,0 +1,47 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2010. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek Software")
+ * have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+ * applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef _MT_RISCVINTRIN_H_
+#define _MT_RISCVINTRIN_H_
+
+#ifdef __COVERITY__
+#define __int128_t int
+#endif
+
+#ifdef LLVM
+#include <riscvintrin.h>
+#endif
+
+#endif
diff --git a/src/tinysys/medmcu/project/RV33_A/common/platform/inc/scp_it.h b/src/tinysys/medmcu/project/RV33_A/common/platform/inc/scp_it.h
new file mode 100644
index 0000000..a2f5512
--- /dev/null
+++ b/src/tinysys/medmcu/project/RV33_A/common/platform/inc/scp_it.h
@@ -0,0 +1,390 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
+ * ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
+ * THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
+ * SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
+ * RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
+ * FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
+ * WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
+ * AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
+ * RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation
+ * ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
+ * subject to any receiver\'s applicable license agreements with MediaTek Inc.
+ */
+
+#ifdef configExtension_F
+#define DUMP_REG_FPU 0//1
+#else
+#define DUMP_REG_FPU 0
+#endif
+
+#ifdef configExtension_ACC
+#define DUMP_REG_ACC 0//1
+#else
+#define DUMP_REG_ACC 0
+#endif
+
+#ifdef configExtension_UAM
+#define DUMP_REG_UAM 0//1
+#else
+#define DUMP_REG_UAM 0
+#endif
+
+#define DUMP_MAGIC 0xca
+#define DUMP_REG_MREG 1
+#define DUMP_REG_COP 0
+#define DUMP_REG_DBG 0
+
+#define DUMP_VERSION ((DUMP_MAGIC << 24) | (DUMP_REG_FPU << 23)\
+ | (DUMP_REG_ACC << 22) | (DUMP_REG_UAM << 21)\
+ | (DUMP_REG_MREG << 19) | (DUMP_REG_COP << 18)\
+ | (DUMP_REG_DBG << 1)) | sizeof(struct TaskContextType)
+
+enum mrv_stack {
+ e_pc,
+ e_x1,
+ e_x2,
+ e_x3,
+ e_x4,
+ e_x5,
+ e_x6,
+ e_x7,
+ e_x8,
+ e_x9,
+ e_x10,
+ e_x11,
+ e_x12,
+ e_x13,
+ e_x14,
+ e_x15,
+ e_x16,
+ e_x17,
+ e_x18,
+ e_x19,
+ e_x20,
+ e_x21,
+ e_x22,
+ e_x23,
+ e_x24,
+ e_x25,
+ e_x26,
+ e_x27,
+ e_x28,
+ e_x29,
+ e_x30,
+ e_x31,
+ e_mstatus,
+#if DUMP_REG_UAM
+ e_uab0,
+ e_uas0,
+ e_uam0,
+ e_uab1,
+ e_uas1,
+ e_uam1,
+ e_uab2,
+ e_uas2,
+ e_uam2,
+ e_uab3,
+ e_uas3,
+ e_uam3,
+#endif
+#if DUMP_REG_ACC
+ e_acc0l,
+ e_acc0h,
+ e_acc0g,
+ e_acc1l,
+ e_acc1h,
+ e_acc1g,
+ e_acc2l,
+ e_acc2h,
+ e_acc2g,
+ e_acc3l,
+ e_acc3h,
+ e_acc3g,
+#endif
+#if DUMP_REG_FPU
+ e_f0,
+ e_f1,
+ e_f2,
+ e_f3,
+ e_f4,
+ e_f5,
+ e_f6,
+ e_f7,
+ e_f8,
+ e_f9,
+ e_f10,
+ e_f11,
+ e_f12,
+ e_f13,
+ e_f14,
+ e_f15,
+ e_f16,
+ e_f17,
+ e_f18,
+ e_f19,
+ e_f20,
+ e_f21,
+ e_f22,
+ e_f23,
+ e_f24,
+ e_f25,
+ e_f26,
+ e_f27,
+ e_f28,
+ e_f29,
+ e_f30,
+ e_f31,
+ e_fcsr,
+#endif
+
+};
+
+typedef struct TaskContextType {
+ long x0;
+ long x1;
+ long x2;
+ long x3; /* 0x10*/
+ long x4;
+ long x5;
+ long x6;
+ long x7; /* 0x20*/
+ long x8;
+ long x9;
+ long x10;
+ long x11; /* 0x30*/
+ long x12;
+ long x13;
+ long x14;
+ long x15; /* 0x40*/
+ long x16;
+ long x17;
+ long x18;
+ long x19; /* 0x50*/
+ long x20;
+ long x21;
+ long x22;
+ long x23; /* 0x60*/
+ long x24;
+ long x25;
+ long x26;
+ long x27; /* 0x70*/
+ long x28;
+ long x29;
+ long x30;
+ long x31; /* 0x80*/
+ long pc;
+ long mstatus;
+ long mepc;
+#if DUMP_REG_UAM
+ long uab0;
+ long uas0;
+ long uam0; /* 0x90*/
+ long uab1;
+ long uas1;
+ long uam1;
+ long uab2; /* 0xa0*/
+ long uas2;
+ long uam2;
+ long uab3;
+ long uas3; /* 0xb0*/
+ long uam3;
+#endif
+#if DUMP_REG_ACC
+ long acc0l;
+ long acc0h;
+ long acc0g; /* 0xc0*/
+ long acc1l;
+ long acc1h;
+ long acc1g;
+ long acc2l; /* 0xd0*/
+ long acc2h;
+ long acc2g;
+ long acc3l;
+ long acc3h; /* 0xe0*/
+ long acc3g;
+#endif
+#if DUMP_REG_FPU
+ long f0;
+ long f1;
+ long f2; /* 0xf0*/
+ long f3;
+ long f4;
+ long f5;
+ long f6; /* 0x100*/
+ long f7;
+ long f8;
+ long f9;
+ long f10; /* 0x110*/
+ long f11;
+ long f12;
+ long f13;
+ long f14; /* 0x120*/
+ long f15;
+ long f16;
+ long f17;
+ long f18; /* 0x130*/
+ long f19;
+ long f20;
+ long f21;
+ long f22; /* 0x140*/
+ long f23;
+ long f24;
+ long f25;
+ long f26; /* 0x150*/
+ long f27;
+ long f28;
+ long f29;
+ long f30; /* 0x160*/
+ long f31;
+ long fcsr;
+#endif
+#if DUMP_REG_MREG
+ long fflags; /* 0x170*/
+ long frm;
+ long misa;
+ long mtvec;
+ long mctren;
+ long mflag;
+ long mcycle;
+ long mtime; /* 0x190*/
+ long minstret;
+ long mcycleh;
+ long mtimeh;
+ long minstreth; /* 0x1a0*/
+ long mpmuctr;
+ long mtbufctr;
+ long mvendorid;
+ long marchid; /* 0x1b0*/
+ long mimpid;
+ long mhartid;
+ long mnpc; /* 0x1c0*/
+ long mverid0;
+ long mverid1;
+ long mverid2;
+ long micause; /* 0x1d0*/
+ long midbgmask;
+ long midbgwakeup;
+ long mipend_g0;
+ long mimask_g0; /* 0x1e0*/
+ long miwakeup_g0;
+ long milsel_g0;
+ long miemask_g0;
+ long medeleg; /* 0x1f0*/
+ long mideleg;
+ long mie;
+ long mip; /* 0x200*/
+ long mpu_en;
+ long mpu_litcm;
+ long mpu_ldtcm;
+ long mpu_hitcm; /* 0x210*/
+ long mpu_hdtcm;
+ long mpu_l00;
+ long mpu_l01;
+ long mpu_l02; /* 0x220*/
+ long mpu_l03;
+ long mpu_l04;
+ long mpu_l05;
+ long mpu_l06; /* 0x230*/
+ long mpu_l07;
+ long mpu_l08;
+ long mpu_l09;
+ long mpu_l10; /* 0x240*/
+ long mpu_l11;
+ long mpu_l12;
+ long mpu_l13;
+ long mpu_l14; /* 0x250*/
+ long mpu_l15;
+ long mpu_h00;
+ long mpu_h01;
+ long mpu_h02; /* 0x260*/
+ long mpu_h03;
+ long mpu_h04;
+ long mpu_h05;
+ long mpu_h06;
+ long mpu_h07;
+ long mpu_h08;
+ long mpu_h09;
+ long mpu_h10;
+ long mpu_h11;
+ long mpu_h12;
+ long mpu_h13;
+ long mpu_h14;
+ long mpu_h15;
+ long mdbgbp0;
+ long mdbgbp1;
+ long mdbgbp2;
+ long mdbgbp3;
+ long mdbgbpc;
+ long mdbgwpm0;
+ long mdbgwpm1;
+ long mdbgwpm2;
+ long mdbgwpm3;
+ long dscratch;
+ long mscratch;
+ long mcause;
+ long mtval;
+ long mimabtcau;
+ long mimabtaddr;
+#endif
+#if DUMP_REG_COP
+ long dcache_con;
+ long dcache_membar;
+ long dcache_rulechk;
+ long dcache_rlcwmode;
+ long dcache_pmask;
+ long dcache_status;
+ long dcache_op;
+ long dcache_rlcwid;
+ long core_pf_ctrl_0;
+ long icache_con;
+ long icache_op;
+ long icache_status;
+ long icache_membar;
+#endif
+#if DUMP_REG_DBG
+ long thread_mode_ctrl_0;
+ long btb_con;
+ long icache_pmask;
+ long tbufctr;
+ long tbufclr;
+ long tbufstr;
+ long tbufrcmd;
+ long tbufrdata;
+ long mtmrctr;
+ long mtmrstatus;
+ long mtmrcvr;
+ long mtmrrvr;
+ long mtmrdvr;
+#endif
+} TaskContext;
+
+
+void mt_ram_dump_init(void);
+void stackDump(long epc, long stack[], long re_pc, long re_sp, long re_ra);
+//void wdt_isr_save_context(long stack[]);
+
+
diff --git a/src/tinysys/medmcu/project/RV33_A/common/platform/src/scp_it.c b/src/tinysys/medmcu/project/RV33_A/common/platform/src/scp_it.c
new file mode 100644
index 0000000..dcb8f70
--- /dev/null
+++ b/src/tinysys/medmcu/project/RV33_A/common/platform/src/scp_it.c
@@ -0,0 +1,440 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
+ * ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
+ * THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
+ * SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
+ * RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
+ * FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
+ * WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
+ * AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
+ * RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation
+ * ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
+ * subject to any receiver\'s applicable license agreements with MediaTek Inc.
+ */
+
+#include "encoding.h"
+#include <stdio.h>
+#include <string.h>
+#include <main.h>
+#include <scp_it.h>
+#include <mt_printf.h>
+#ifdef CFG_WDT_SUPPORT
+#include <wdt.h>
+#endif
+
+TaskContext taskCtxDump[2] __attribute__((section(".sync")));
+#ifdef CFG_CACHE_SUPPORT
+extern void *__dram_end;
+#endif
+
+void stackDump(long epc, long stack[], long re_pc, long re_sp, long re_ra)
+{
+ int i;
+ unsigned long tbuf_from, tbuf_to, tuf_wp;
+ TaskContext *ctx_ptr = &taskCtxDump[mrv_read_csr(CSR_MHARTID)];
+
+ ctx_ptr->x0 = DUMP_VERSION;
+ ctx_ptr->x1 = stack[e_x1];
+ ctx_ptr->x2 = stack[e_x2];
+ ctx_ptr->x3 = stack[e_x3];
+ ctx_ptr->x4 = stack[e_x4];
+ ctx_ptr->x5 = stack[e_x5];
+ ctx_ptr->x6 = stack[e_x6];
+ ctx_ptr->x7 = stack[e_x7];
+ ctx_ptr->x8 = stack[e_x8];
+ ctx_ptr->x9 = stack[e_x9];
+ ctx_ptr->x10 = stack[e_x10];
+ ctx_ptr->x11 = stack[e_x11];
+ ctx_ptr->x12 = stack[e_x12];
+ ctx_ptr->x13 = stack[e_x13];
+ ctx_ptr->x14 = stack[e_x14];
+ ctx_ptr->x15 = stack[e_x15];
+ ctx_ptr->x16 = stack[e_x16];
+ ctx_ptr->x17 = stack[e_x17];
+ ctx_ptr->x18 = stack[e_x18];
+ ctx_ptr->x19 = stack[e_x19];
+ ctx_ptr->x20 = stack[e_x20];
+ ctx_ptr->x21 = stack[e_x21];
+ ctx_ptr->x22 = stack[e_x22];
+ ctx_ptr->x23 = stack[e_x23];
+ ctx_ptr->x24 = stack[e_x24];
+ ctx_ptr->x25 = stack[e_x25];
+ ctx_ptr->x26 = stack[e_x26];
+ ctx_ptr->x27 = stack[e_x27];
+ ctx_ptr->x28 = stack[e_x28];
+ ctx_ptr->x29 = stack[e_x29];
+ ctx_ptr->x30 = stack[e_x30];
+ ctx_ptr->x31 = stack[e_x31];
+ ctx_ptr->pc = stack[e_pc];
+ ctx_ptr->mstatus = stack[e_mstatus];
+ ctx_ptr->mepc = epc;
+
+ PRINTF_E("Regs dump\n\r");
+ PRINTF_E("x0:0x%08x x1:0x%08x\n", (uint32_t)(ctx_ptr->x0),
+ (uint32_t)(ctx_ptr->x1));
+ PRINTF_E("x2:0x%08x x3:0x%08x\n", (uint32_t)(ctx_ptr->x2),
+ (uint32_t)(ctx_ptr->x3));
+ PRINTF_E("pc:0x%08x mstatus:0x%08x\n", (uint32_t)(ctx_ptr->pc),
+ (uint32_t)(ctx_ptr->mstatus));
+ PRINTF_E("mepc:0x%08x\n", (uint32_t)(ctx_ptr->mepc));
+
+ /* reset pc, sp, ra for mrv_coredump() */
+ ctx_ptr->pc = re_pc;
+ ctx_ptr->x2 = re_sp;
+ ctx_ptr->x1 = re_ra;
+#if DUMP_REG_UAM
+ ctx_ptr->uab0 = stack[e_uab0];
+ ctx_ptr->uas0 = stack[e_uas0];
+ ctx_ptr->uam0 = stack[e_uam0];
+ ctx_ptr->uab1 = stack[e_uab1];
+ ctx_ptr->uas1 = stack[e_uas1];
+ ctx_ptr->uam1 = stack[e_uam1];
+ ctx_ptr->uab2 = stack[e_uab2];
+ ctx_ptr->uas2 = stack[e_uas2];
+ ctx_ptr->uam2 = stack[e_uam2];
+ ctx_ptr->uab3 = stack[e_uab3];
+ ctx_ptr->uas3 = stack[e_uas3];
+ ctx_ptr->uam3 = stack[e_uam3];
+#endif
+#if DUMP_REG_ACC
+ ctx_ptr->acc0l = stack[e_acc0l];
+ ctx_ptr->acc0h = stack[e_acc0h];
+ ctx_ptr->acc0g = stack[e_acc0g];
+ ctx_ptr->acc1l = stack[e_acc1l];
+ ctx_ptr->acc1h = stack[e_acc1h];
+ ctx_ptr->acc1g = stack[e_acc1g];
+ ctx_ptr->acc2l = stack[e_acc2l];
+ ctx_ptr->acc2h = stack[e_acc2h];
+ ctx_ptr->acc2g = stack[e_acc2g];
+ ctx_ptr->acc3l = stack[e_acc3l];
+ ctx_ptr->acc3h = stack[e_acc3h];
+ ctx_ptr->acc3g = stack[e_acc3g];
+#endif
+#if DUMP_REG_FPU
+ ctx_ptr->f0 = stack[e_f0];
+ ctx_ptr->f1 = stack[e_f1];
+ ctx_ptr->f2 = stack[e_f2];
+ ctx_ptr->f3 = stack[e_f3];
+ ctx_ptr->f4 = stack[e_f4];
+ ctx_ptr->f5 = stack[e_f5];
+ ctx_ptr->f6 = stack[e_f6];
+ ctx_ptr->f7 = stack[e_f7];
+ ctx_ptr->f8 = stack[e_f8];
+ ctx_ptr->f9 = stack[e_f9];
+ ctx_ptr->f10 = stack[e_f10];
+ ctx_ptr->f11 = stack[e_f11];
+ ctx_ptr->f12 = stack[e_f12];
+ ctx_ptr->f13 = stack[e_f13];
+ ctx_ptr->f14 = stack[e_f14];
+ ctx_ptr->f15 = stack[e_f15];
+ ctx_ptr->f16 = stack[e_f16];
+ ctx_ptr->f17 = stack[e_f17];
+ ctx_ptr->f18 = stack[e_f18];
+ ctx_ptr->f19 = stack[e_f19];
+ ctx_ptr->f20 = stack[e_f20];
+ ctx_ptr->f21 = stack[e_f21];
+ ctx_ptr->f22 = stack[e_f22];
+ ctx_ptr->f23 = stack[e_f23];
+ ctx_ptr->f24 = stack[e_f24];
+ ctx_ptr->f25 = stack[e_f25];
+ ctx_ptr->f26 = stack[e_f26];
+ ctx_ptr->f27 = stack[e_f27];
+ ctx_ptr->f28 = stack[e_f28];
+ ctx_ptr->f29 = stack[e_f29];
+ ctx_ptr->f30 = stack[e_f30];
+ ctx_ptr->f31 = stack[e_f31];
+ ctx_ptr->fcsr = stack[e_fcsr];
+#endif
+#if DUMP_REG_MREG
+ ctx_ptr->fflags = mrv_read_csr(CSR_FFLAGS);
+ ctx_ptr->frm = mrv_read_csr(CSR_FRM);
+ ctx_ptr->misa = mrv_read_csr(CSR_MISA);
+ ctx_ptr->mtvec = mrv_read_csr(CSR_MTVEC);
+ ctx_ptr->mctren = mrv_read_csr(CSR_MCTREN);
+ ctx_ptr->mflag = 0x0;//mrv_read_csr(CSR_UFLAG);
+ ctx_ptr->mcycle = mrv_read_csr(CSR_MCYCLE);
+ ctx_ptr->mtime = mrv_read_csr(CSR_TIMER);
+ ctx_ptr->minstret = mrv_read_csr(CSR_MINSTRET);
+ ctx_ptr->mcycleh = mrv_read_csr(CSR_MCYCLEH);
+ ctx_ptr->mtimeh = mrv_read_csr(CSR_TIMERH);
+ ctx_ptr->minstreth = mrv_read_csr(CSR_MINSTRETH);
+ ctx_ptr->mpmuctr = mrv_read_csr(CSR_PMU_MPMUCTR);
+ ctx_ptr->mtbufctr = mrv_read_csr(CSR_TBUF_MTBUFCTR);
+ ctx_ptr->mvendorid = mrv_read_csr(CSR_MVENDORID);
+ ctx_ptr->marchid = mrv_read_csr(CSR_MARCHID);
+ ctx_ptr->mimpid = mrv_read_csr(CSR_MIMPID);
+ ctx_ptr->mhartid = mrv_read_csr(CSR_MHARTID);
+ ctx_ptr->mnpc = mrv_read_csr(CSR_MNPC);
+ ctx_ptr->mverid0 = mrv_read_csr(CSR_MVERID0);
+ ctx_ptr->mverid1 = mrv_read_csr(CSR_MVERID1);
+ ctx_ptr->mverid2 = mrv_read_csr(CSR_MVERID2);
+ ctx_ptr->micause = mrv_read_csr(CSR_VIC_MICAUSE);
+ ctx_ptr->midbgmask = 0x0;//mrv_read_csr(CSR_VIC_MIDBGMASK);
+ ctx_ptr->midbgwakeup = 0x0;//mrv_read_csr(CSR_VIC_MIDBGWAKEUP);
+ ctx_ptr->mipend_g0 = mrv_read_csr(CSR_VIC_MIPEND_G0);
+ ctx_ptr->mimask_g0 = mrv_read_csr(CSR_VIC_MIMASK_G0);
+ ctx_ptr->miwakeup_g0 = mrv_read_csr(CSR_VIC_MIWAKEUP_G0);
+ ctx_ptr->milsel_g0 = mrv_read_csr(CSR_VIC_MILSEL_G0);
+ ctx_ptr->miemask_g0 = 0x0;//mrv_read_csr(CSR_VIC_MIEMASK_G0);
+ ctx_ptr->medeleg = mrv_read_csr(CSR_MEDELEG);
+ ctx_ptr->mideleg = mrv_read_csr(CSR_MIDELEG);
+ ctx_ptr->mie = mrv_read_csr(CSR_MIE);
+ ctx_ptr->mip = mrv_read_csr(CSR_MIP);
+ ctx_ptr->mpu_en = mrv_read_csr(CSR_MPU_ENTRY_EN);
+ ctx_ptr->mpu_litcm = mrv_read_csr(CSR_MPU_LITCM);
+ ctx_ptr->mpu_ldtcm = mrv_read_csr(CSR_MPU_LDTCM);
+ ctx_ptr->mpu_hitcm = mrv_read_csr(CSR_MPU_HITCM);
+ ctx_ptr->mpu_hdtcm = mrv_read_csr(CSR_MPU_HDTCM);
+ ctx_ptr->mpu_l00 = mrv_read_csr(CSR_MPU_L00);
+ ctx_ptr->mpu_l01 = mrv_read_csr(CSR_MPU_L01);
+ ctx_ptr->mpu_l02 = mrv_read_csr(CSR_MPU_L02);
+ ctx_ptr->mpu_l03 = mrv_read_csr(CSR_MPU_L03);
+ ctx_ptr->mpu_l04 = mrv_read_csr(CSR_MPU_L04);
+ ctx_ptr->mpu_l05 = mrv_read_csr(CSR_MPU_L05);
+ ctx_ptr->mpu_l06 = mrv_read_csr(CSR_MPU_L06);
+ ctx_ptr->mpu_l07 = mrv_read_csr(CSR_MPU_L07);
+ ctx_ptr->mpu_l08 = mrv_read_csr(CSR_MPU_L08);
+ ctx_ptr->mpu_l09 = mrv_read_csr(CSR_MPU_L09);
+ ctx_ptr->mpu_l10 = mrv_read_csr(CSR_MPU_L10);
+ ctx_ptr->mpu_l11 = mrv_read_csr(CSR_MPU_L11);
+ ctx_ptr->mpu_l12 = mrv_read_csr(CSR_MPU_L12);
+ ctx_ptr->mpu_l13 = mrv_read_csr(CSR_MPU_L13);
+ ctx_ptr->mpu_l14 = mrv_read_csr(CSR_MPU_L14);
+ ctx_ptr->mpu_l15 = mrv_read_csr(CSR_MPU_L15);
+ ctx_ptr->mpu_h00 = mrv_read_csr(CSR_MPU_H00);
+ ctx_ptr->mpu_h01 = mrv_read_csr(CSR_MPU_H01);
+ ctx_ptr->mpu_h02 = mrv_read_csr(CSR_MPU_H02);
+ ctx_ptr->mpu_h03 = mrv_read_csr(CSR_MPU_H03);
+ ctx_ptr->mpu_h04 = mrv_read_csr(CSR_MPU_H04);
+ ctx_ptr->mpu_h05 = mrv_read_csr(CSR_MPU_H05);
+ ctx_ptr->mpu_h06 = mrv_read_csr(CSR_MPU_H06);
+ ctx_ptr->mpu_h07 = mrv_read_csr(CSR_MPU_H07);
+ ctx_ptr->mpu_h08 = mrv_read_csr(CSR_MPU_H08);
+ ctx_ptr->mpu_h09 = mrv_read_csr(CSR_MPU_H09);
+ ctx_ptr->mpu_h10 = mrv_read_csr(CSR_MPU_H10);
+ ctx_ptr->mpu_h11 = mrv_read_csr(CSR_MPU_H11);
+ ctx_ptr->mpu_h12 = mrv_read_csr(CSR_MPU_H12);
+ ctx_ptr->mpu_h13 = mrv_read_csr(CSR_MPU_H13);
+ ctx_ptr->mpu_h14 = mrv_read_csr(CSR_MPU_H14);
+ ctx_ptr->mpu_h15 = mrv_read_csr(CSR_MPU_H15);
+ ctx_ptr->mdbgbp0 = mrv_read_csr(CSR_MDBGBP0);
+ ctx_ptr->mdbgbp1 = mrv_read_csr(CSR_MDBGBP1);
+ ctx_ptr->mdbgbp2 = mrv_read_csr(CSR_MDBGBP2);
+ ctx_ptr->mdbgbp3 = mrv_read_csr(CSR_MDBGBP3);
+ ctx_ptr->mdbgbpc = mrv_read_csr(CSR_MDBGBPC);
+ ctx_ptr->mdbgwpm0 = mrv_read_csr(CSR_MDBGWPM0);
+ ctx_ptr->mdbgwpm1 = mrv_read_csr(CSR_MDBGWPM1);
+ ctx_ptr->mdbgwpm2 = mrv_read_csr(CSR_MDBGWPM2);
+ ctx_ptr->mdbgwpm3 = mrv_read_csr(CSR_MDBGWPM3);
+ ctx_ptr->dscratch = 0x0;//mrv_read_csr(CSR_DSCRATCH);
+ ctx_ptr->mscratch = mrv_read_csr(CSR_MSCRATCH);
+ ctx_ptr->mcause = mrv_read_csr(CSR_MCAUSE);
+ ctx_ptr->mtval = mrv_read_csr(CSR_MTVAL);
+ ctx_ptr->mimabtcau = mrv_read_csr(CSR_MIMABTCAU);
+ ctx_ptr->mimabtaddr = mrv_read_csr(CSR_MIMABTADDR);
+
+#endif
+
+#if DUMP_REG_COP
+ ctx_ptr->dcache_con = stack[e_dcache_con];
+ ctx_ptr->dcache_membar = stack[e_dcache_membar];
+ ctx_ptr->dcache_rulechk = stack[e_dcache_rulechk];
+ ctx_ptr->dcache_rlcwmode = stack[e_dcache_rlcwmode];
+ ctx_ptr->dcache_pmask = stack[e_dcache_pmask];
+ ctx_ptr->dcache_status = stack[e_dcache_status];
+ ctx_ptr->dcache_op = stack[e_dcache_op];
+ ctx_ptr->dcache_rlcwid = stack[e_dcache_rlcwid];
+ ctx_ptr->core_pf_ctrl_0 = stack[e_core_pf_ctrl_0];
+ ctx_ptr->icache_con = stack[e_icache_con];
+ ctx_ptr->icache_op = stack[e_icache_op];
+ ctx_ptr->icache_status = stack[e_icache_status];
+ ctx_ptr->icache_membar = stack[e_icache_membar];
+#endif
+#if DUMP_REG_DBG
+ ctx_ptr->thread_mode_ctrl_0 = stack[e_thread_mode_ctrl_0];
+ ctx_ptr->btb_con = stack[e_btb_con];
+ ctx_ptr->icache_pmask = stack[e_icache_pmask];
+ ctx_ptr->tbufctr = stack[e_tbufctr];
+ ctx_ptr->tbufclr = stack[e_tbufclr];
+ ctx_ptr->tbufstr = stack[e_tbufstr];
+ ctx_ptr->tbufrcmd = stack[e_tbufrcmd];
+ ctx_ptr->tbufrdata = stack[e_tbufrdata];
+ ctx_ptr->mtmrctr = stack[e_mtmrctr];
+ ctx_ptr->mtmrstatus = stack[e_mtmrstatus];
+ ctx_ptr->mtmrcvr = stack[e_mtmrcvr];
+ ctx_ptr->mtmrrvr = stack[e_mtmrrvr];
+ ctx_ptr->mtmrdvr = stack[e_mtmrdvr];
+#endif
+
+#if DUMP_REG_MREG
+#if 0 //not helpful
+ PRINTF_E("fflags: 0x%08x\n\r", (uint32_t)(ctx_ptr->fflags));
+ PRINTF_E("frm: 0x%08x\n\r", (uint32_t)(ctx_ptr->frm));
+ PRINTF_E("misa: 0x%08x\n\r", (uint32_t)(ctx_ptr->misa));
+ PRINTF_E("mtvec: 0x%08x\n\r", (uint32_t)(ctx_ptr->mtvec));
+#endif
+#if 0 //not helpful
+ PRINTF_E("mctren: 0x%08x\n\r", (uint32_t)(ctx_ptr->mctren));
+ PRINTF_E("mflag: 0x%08x\n\r", (uint32_t)(ctx_ptr->mflag));
+ PRINTF_E("mcycle: 0x%08x\n\r", (uint32_t)(ctx_ptr->mcycle));
+ PRINTF_E("mtime: 0x%08x\n\r", (uint32_t)(ctx_ptr->mtime));
+ PRINTF_E("minstret: 0x%08x\n\r", (uint32_t)(ctx_ptr->minstret));
+ PRINTF_E("mcycleh: 0x%08x\n\r", (uint32_t)(ctx_ptr->mcycleh));
+ PRINTF_E("mtimeh: 0x%08x\n\r", (uint32_t)(ctx_ptr->mtimeh));
+ PRINTF_E("minstreth: 0x%08x\n\r", (uint32_t)(ctx_ptr->minstreth));
+ PRINTF_E("mpmuctr: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpmuctr));
+ PRINTF_E("mtbufctr: 0x%08x\n\r", (uint32_t)(ctx_ptr->mtbufctr));
+ PRINTF_E("mvendorid: 0x%08x\n\r", (uint32_t)(ctx_ptr->mvendorid));
+ PRINTF_E("marchid: 0x%08x\n\r", (uint32_t)(ctx_ptr->marchid));
+ PRINTF_E("mimpid: 0x%08x\n\r", (uint32_t)(ctx_ptr->mimpid));
+ PRINTF_E("mhartid: 0x%08x\n\r", (uint32_t)(ctx_ptr->mhartid));
+ PRINTF_E("mnpc: 0x%08x\n\r", (uint32_t)(ctx_ptr->mnpc));
+ PRINTF_E("mverid0: 0x%08x\n\r", (uint32_t)(ctx_ptr->mverid0));
+ PRINTF_E("mverid1: 0x%08x\n\r", (uint32_t)(ctx_ptr->mverid1));
+ PRINTF_E("mverid2: 0x%08x\n\r", (uint32_t)(ctx_ptr->mverid2));
+ PRINTF_E("micause: 0x%08x\n\r", (uint32_t)(ctx_ptr->micause));
+ PRINTF_E("midbgmask: 0x%08x\n\r", (uint32_t)(ctx_ptr->midbgmask));
+ PRINTF_E("midbgwakeup: 0x%08x\n\r", (uint32_t)(ctx_ptr->midbgwakeup));
+ PRINTF_E("mipend_g0: 0x%08x\n\r", (uint32_t)(ctx_ptr->mipend_g0));
+ PRINTF_E("mimask_g0: 0x%08x\n\r", (uint32_t)(ctx_ptr->mimask_g0));
+ PRINTF_E("miwakeup_g0: 0x%08x\n\r", (uint32_t)(ctx_ptr->miwakeup_g0));
+ PRINTF_E("milsel_g0: 0x%08x\n\r", (uint32_t)(ctx_ptr->milsel_g0));
+ PRINTF_E("miemask_g0: 0x%08x\n\r", (uint32_t)(ctx_ptr->miemask_g0));
+ PRINTF_E("medeleg: 0x%08x\n\r", (uint32_t)(ctx_ptr->medeleg));
+ PRINTF_E("mideleg: 0x%08x\n\r", (uint32_t)(ctx_ptr->mideleg));
+ PRINTF_E("mie: 0x%08x\n\r", (uint32_t)(ctx_ptr->mie));
+ PRINTF_E("mip: 0x%08x\n\r", (uint32_t)(ctx_ptr->mip));
+ PRINTF_E("mpu_en: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_en));
+ PRINTF_E("mpu_litcm: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_litcm));
+ PRINTF_E("mpu_ldtcm: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_ldtcm));
+ PRINTF_E("mpu_hitcm: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_hitcm));
+ PRINTF_E("mpu_hdtcm: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_hdtcm));
+ PRINTF_E("mpu_l00: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_l00));
+ PRINTF_E("mpu_l01: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_l01));
+ PRINTF_E("mpu_l02: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_l02));
+ PRINTF_E("mpu_l03: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_l03));
+ PRINTF_E("mpu_l04: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_l04));
+ PRINTF_E("mpu_l05: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_l05));
+ PRINTF_E("mpu_l06: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_l06));
+ PRINTF_E("mpu_l07: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_l07));
+ PRINTF_E("mpu_l08: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_l08));
+ PRINTF_E("mpu_l09: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_l09));
+ PRINTF_E("mpu_l10: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_l10));
+ PRINTF_E("mpu_l11: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_l11));
+ PRINTF_E("mpu_l12: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_l12));
+ PRINTF_E("mpu_l13: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_l13));
+ PRINTF_E("mpu_l14: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_l14));
+ PRINTF_E("mpu_l15: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_l15));
+ PRINTF_E("mpu_h00: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_h00));
+ PRINTF_E("mpu_h01: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_h01));
+ PRINTF_E("mpu_h02: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_h02));
+ PRINTF_E("mpu_h03: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_h03));
+ PRINTF_E("mpu_h04: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_h04));
+ PRINTF_E("mpu_h05: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_h05));
+ PRINTF_E("mpu_h06: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_h06));
+ PRINTF_E("mpu_h07: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_h07));
+ PRINTF_E("mpu_h08: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_h08));
+ PRINTF_E("mpu_h09: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_h09));
+ PRINTF_E("mpu_h10: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_h10));
+ PRINTF_E("mpu_h11: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_h11));
+ PRINTF_E("mpu_h12: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_h12));
+ PRINTF_E("mpu_h13: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_h13));
+ PRINTF_E("mpu_h14: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_h14));
+ PRINTF_E("mpu_h15: 0x%08x\n\r", (uint32_t)(ctx_ptr->mpu_h15));
+ PRINTF_E("mdbgbp0: 0x%08x\n\r", (uint32_t)(ctx_ptr->mdbgbp0));
+ PRINTF_E("mdbgbp1: 0x%08x\n\r", (uint32_t)(ctx_ptr->mdbgbp1));
+ PRINTF_E("mdbgbp2: 0x%08x\n\r", (uint32_t)(ctx_ptr->mdbgbp2));
+ PRINTF_E("mdbgbp3: 0x%08x\n\r", (uint32_t)(ctx_ptr->mdbgbp3));
+ PRINTF_E("mdbgbpc: 0x%08x\n\r", (uint32_t)(ctx_ptr->mdbgbpc));
+ PRINTF_E("mdbgwpm0: 0x%08x\n\r", (uint32_t)(ctx_ptr->mdbgwpm0));
+ PRINTF_E("mdbgwpm1: 0x%08x\n\r", (uint32_t)(ctx_ptr->mdbgwpm1));
+ PRINTF_E("mdbgwpm2: 0x%08x\n\r", (uint32_t)(ctx_ptr->mdbgwpm2));
+ PRINTF_E("mdbgwpm3: 0x%08x\n\r", (uint32_t)(ctx_ptr->mdbgwpm3));
+ PRINTF_E("dscratch: 0x%08x\n\r", (uint32_t)(ctx_ptr->dscratch));
+
+ PRINTF_E("mscratch: 0x%08x\n\r", (uint32_t)(ctx_ptr->mscratch));
+#endif
+ PRINTF_E("mcause: 0x%08x\n\r", (uint32_t)(ctx_ptr->mcause));
+ PRINTF_E("mtval: 0x%08x\n\r", (uint32_t)(ctx_ptr->mtval));
+#if 0 //not helpful
+ PRINTF_E("mimabtcau: 0x%08x\n\r", (uint32_t)(ctx_ptr->mimabtcau));
+ PRINTF_E("mimabtaddr: 0x%08x\n\r", (uint32_t)(ctx_ptr->mimabtaddr));
+#endif
+#endif
+
+ PRINTF_E("T Buff(%x)\n",
+ (uint32_t)mrv_read_csr(CSR_TBUF_MTBUFCTR));
+ tuf_wp = (mrv_read_csr(CSR_TBUF_MTBUFSTR) >> 4);
+ //PRINTF_E("wp %x\n", (uint32_t)tuf_wp);
+ for(i = 0;i < 16; i++) {
+ tbuf_from = ((0x1 << CSR_TBUF_MTBUFRCMD_R)
+ | (((tuf_wp + i) & 0xf) << CSR_TBUF_MTBUFRCMD_RP)
+ | (0 << CSR_TBUF_MTBUFRCMD_LOG));
+ tbuf_to = ((0x1 << CSR_TBUF_MTBUFRCMD_R)
+ | (((tuf_wp + i) & 0xf) << CSR_TBUF_MTBUFRCMD_RP)
+ | (1 << CSR_TBUF_MTBUFRCMD_LOG));
+ mrv_set_csr(CSR_TBUF_MTBUFRCMD, tbuf_from);
+ tbuf_from = mrv_read_csr(CSR_TBUF_MTBUFRDATA);
+ mrv_set_csr(CSR_TBUF_MTBUFRCMD, tbuf_to);
+ tbuf_to = mrv_read_csr(CSR_TBUF_MTBUFRDATA);
+ PRINTF_E("%02d 0x%08x:0x%08x\n",i ,
+ (uint32_t)(tbuf_from), (uint32_t)(tbuf_to));
+ }
+#ifdef CFG_CACHE_SUPPORT
+ if ((epc & 0x2) || ( (uint32_t)epc >= ((uint32_t)(&__dram_end))))
+#else
+ if (epc & 0x2)
+#endif
+ return;
+
+ PRINTF_E("Code: %04x %04x %04x %04x <%04x> %04x %04x %04x %04x\n",
+ *(uint16_t *)(epc-8),*(uint16_t *)(epc-6),
+ *(uint16_t *)(epc-4), *(uint16_t *)(epc-2),
+ *(uint16_t *)(epc), *(uint16_t *)(epc+2),
+ *(uint16_t *)(epc+4), *(uint16_t *)(epc+6),
+ *(uint16_t *)(epc+8));
+
+}
+
+void mt_ram_dump_init(void)
+{
+ memset(&taskCtxDump, 0, sizeof(taskCtxDump));
+ PRINTF_E("ram dump: %p\n\r", &taskCtxDump);
+}
+
+#ifdef CFG_STACK_PROTECTOR
+void __stack_chk_fail(void);
+
+void __stack_chk_fail()
+{
+ printf("__stack_chk_fail() %p\n", __builtin_return_address(0));
+ while(1);
+}
+
+void *__stack_chk_guard = (void *)(0x99999999);
+
+#endif
+
diff --git a/src/tinysys/medmcu/tools/astyle b/src/tinysys/medmcu/tools/astyle
new file mode 100755
index 0000000..15751d3
--- /dev/null
+++ b/src/tinysys/medmcu/tools/astyle
Binary files differ
diff --git a/src/tinysys/medmcu/tools/build_tinysys.sh b/src/tinysys/medmcu/tools/build_tinysys.sh
new file mode 100755
index 0000000..d252e77
--- /dev/null
+++ b/src/tinysys/medmcu/tools/build_tinysys.sh
@@ -0,0 +1,109 @@
+#!/bin/bash
+###############################################################################
+# This script provides the customer a quick way to build Tiny System from
+# source.
+###############################################################################
+
+PROG=$(basename ${0})
+
+usage() {
+ cat >&2 <<- EOF
+USAGE
+ ${PROG} [-h] [...]
+
+ This script provides a quicker way to build tinysys.
+
+PREREQUISITE
+ The Android environment must be initialize.
+ That is, you need to run those steps at least once:
+ $ cd <ANDROID_ROOT_DIR>
+ $ . buid/envsetup.sh
+ $ lunch
+
+ This script must be executed in Android top directory.
+
+OPTIONS
+ -h Print this help message
+
+Other options for GNU make or build targets can be provided.
+For example:
+ clean Clean up all built directories and objects
+ configheader Generate C header that contains all config options
+ -jN Run N parallel build tasks
+EOF
+
+exit 1
+}
+
+info() {
+ echo "${PROG}: [INFO] ${*}"
+}
+
+error() {
+ echo "${PROG}: [ERROR] ${*}"
+ exit 1
+}
+
+check_Android_env() {
+ if [ -z "${ANDROID_PRODUCT_OUT}" ] || [ -z "${TARGET_PRODUCT}" ] ; then
+ cat >&2 <<- EOF
+[ERROR] Android environment is not ready yet.
+
+Please make sure build/envsetup.sh is sourced and lunch is executed.
+EOF
+ return 1
+ fi
+
+ return 0
+}
+
+run_build_cmd() {
+ echo "Build command: ${*}"
+ eval "${*}" || exit 1
+}
+
+#######################################
+# Main
+#######################################
+TINYSYS_ROOT='tinysys/medmcu'
+TINYSYS_TARGET='tinysys-medmcu'
+#ADSP_TARGET='tinysys-adsp'
+CLEAN_TINYSYS_TARGET="clean-${TINYSYS_TARGET}"
+#CLEAN_ADSP_TARGET="clean-${ADSP_TARGET}"
+TINYSYS_ANDROID_MK="${TINYSYS_ROOT}/Android.mk"
+CLEAN_TARGET=0
+
+# Categorize options
+for i in "${@}"; do
+ case "${i}" in
+ 'clean')
+ KEYWORDS="${KEYWORDS} ${i}"
+ CLEAN_TARGET=1
+ ;;
+ '-h')
+ usage
+ ;;
+ *) CMD_ARGS="${CMD_ARGS} ${i}"
+ esac
+done
+
+check_Android_env || exit 1
+
+# This script must be run in Android root directory
+[ -f 'build/envsetup.sh' ] || \
+ error "Please execute this command in Android top directory"
+
+#######################################
+# Here we build
+#######################################
+BUILD_CMD="ONE_SHOT_MAKEFILE=${TINYSYS_ANDROID_MK} make ${TINYSYS_TARGET} ${CMD_ARGS}"
+CLEAN_CMD="ONE_SHOT_MAKEFILE=${TINYSYS_ANDROID_MK} make ${CLEAN_TINYSYS_TARGET} ${CMD_ARGS}"
+
+
+if [ ${CLEAN_TARGET} -eq 1 ]; then
+ run_build_cmd "${CLEAN_CMD}"
+else
+ run_build_cmd "${BUILD_CMD}"
+fi
+
+exit ${?}
diff --git a/src/tinysys/medmcu/tools/codestyle b/src/tinysys/medmcu/tools/codestyle
new file mode 100755
index 0000000..cea8ed8
--- /dev/null
+++ b/src/tinysys/medmcu/tools/codestyle
@@ -0,0 +1,6 @@
+#!/bin/sh
+current_dir=$(pwd)
+script_dir=$(dirname $0)
+
+$current_dir/$script_dir/astyle --style=kr --indent=spaces=4 --indent-switches --max-code-length=120 --pad-header --pad-oper --convert-tabs --unpad-paren $@
+
diff --git a/src/tinysys/medmcu/tools/link_ld.py b/src/tinysys/medmcu/tools/link_ld.py
new file mode 100755
index 0000000..245a34d
--- /dev/null
+++ b/src/tinysys/medmcu/tools/link_ld.py
@@ -0,0 +1,76 @@
+#!/usr/bin/env python
+# coding: UTF-8
+
+import sys, getopt
+import string
+import struct
+import operator
+import re
+import os
+
+exclude_list = []
+exclude_files = ''
+link_ld_content = []
+def usage():
+ print 'link_ld.py -i <input> -o <output>'
+
+def exclude_list_search(inputfile):
+ global exclude_list
+ global exclude_files
+ global link_ld_content
+ fo = open(inputfile,'rb+')
+ line = "gaia"
+ while line:
+ line = fo.readline()
+ m0 = re.findall('\$(.+?\.o[bj]*)\$', line)
+ if m0:
+ exclude_list += m0
+ line = line.replace('$', '')
+ link_ld_content.append(line)
+ fo.close()
+ #print link_ld_content
+ exclude_list = list(dict.fromkeys(exclude_list))
+ #print exclude_list
+ exclude_files += " ".join(exclude_list)
+
+def regen_link_ld(outputfile):
+ global exclude_list
+ global link_ld_content
+ fo = open(outputfile,'w')
+
+ line=link_ld_content.pop(0)
+ while line:
+ m0 = re.match('[ \t]*@\*@\(', line)
+ if m0:
+ line = line.replace(m0.group(0), "*(EXCLUDE_FILE(" + exclude_files +")")
+ #print m0.group(0)
+ #print line
+ fo.write(line)
+ line=link_ld_content.pop(0)
+ fo.close()
+
+def main(argv):
+ inputfile = ''
+ outputfile = ''
+ try:
+ opts, args = getopt.getopt(argv,"hi:o:",["ifile=","ofile="])
+ except getopt.GetoptError:
+ usage()
+ sys.exit(2)
+ for opt, arg in opts:
+ if opt == '-h':
+ usage()
+ sys.exit()
+ elif opt in ("-i", "--ifile"):
+ inputfile = arg
+ elif opt in ("-o", "--ofile"):
+ outputfile = arg
+ print 'intput：', inputfile
+ print 'output：', outputfile
+ exclude_list_search(inputfile)
+ regen_link_ld(outputfile)
+
+if '__main__'==__name__:
+ ret = main(sys.argv[1:])
+ sys.exit(ret)
+