blob: c233f90b824c6b742ec51bef805b40b35e87cb67 [file] [log] [blame]
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
*/
/dts-v1/;
#include <generated/autoconf.h>
#include <dt-bindings/clock/mt6890-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt2735-pinfunc.h>
#include <dt-bindings/memory/mt6880-larb-port.h>
#include <dt-bindings/power/mt6890-power.h>
#include <dt-bindings/reset/ti-syscon.h>
#include <dt-bindings/soc/mediatek,boot-mode.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/interconnect/mtk,mt6873-emi.h>
#include <dt-bindings/iio/mt635x-auxadc.h>
#include <dt-bindings/gce/mt6890-gce.h>
#include <dt-bindings/thermal/thermal.h>
/ {
model = "MT6890";
compatible = "mediatek,MT6890";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
/* chosen */
chosen: chosen {
bootargs = "console=tty0 console=ttyS0,921600n1 root=/dev/ram \
vmalloc=400M slub_debug=OFZPU swiotlb=noforce \
firmware_class.path=/vendor/firmware \
page_owner=on";
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
gpio_leds {
compatible = "gpio-leds";
led0 {
label = "led9501:red:sim";
gpios = <&pio 209 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
default-state = "off";
};
led1 {
label = "led9502:red:cellular-stat";
gpios = <&pio 210 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
default-state = "off";
};
led2 {
label = "led9504:red:cellular-data";
gpios = <&pio 211 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
default-state = "off";
};
led3 {
label = "led9505:red:cellular-rat";
gpios = <&pio 212 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
default-state = "off";
};
led4 {
label = "led9506:red:cellular-ims";
gpios = <&pio 213 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
default-state = "off";
};
};
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp0 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <650000>;
};
opp1 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <650000>;
};
opp2 {
opp-hz = /bits/ 64 <684000000>;
opp-microvolt = <668750>;
};
opp3 {
opp-hz = /bits/ 64 <768000000>;
opp-microvolt = <687500>;
};
opp4 {
opp-hz = /bits/ 64 <820000000>;
opp-microvolt = <700000>;
};
opp5 {
opp-hz = /bits/ 64 <937000000>;
opp-microvolt = <725000>;
};
opp6 {
opp-hz = /bits/ 64 <1060000000>;
opp-microvolt = <750000>;
};
opp7 {
opp-hz = /bits/ 64 <1134000000>;
opp-microvolt = <768750>;
};
opp8 {
opp-hz = /bits/ 64 <1275000000>;
opp-microvolt = <800000>;
};
opp9 {
opp-hz = /bits/ 64 <1387000000>;
opp-microvolt = <825000>;
};
opp10 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <850000>;
};
opp11 {
opp-hz = /bits/ 64 <1666000000>;
opp-microvolt = <900000>;
};
opp12 {
opp-hz = /bits/ 64 <1750000000>;
opp-microvolt = <925000>;
};
opp13 {
opp-hz = /bits/ 64 <1833000000>;
opp-microvolt = <950000>;
};
opp14 {
opp-hz = /bits/ 64 <1916000000>;
opp-microvolt = <975000>;
};
opp15 {
opp-hz = /bits/ 64 <2000000000>;
opp-microvolt = <1000000>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0000>;
enable-method = "psci";
clock-frequency = <1701000000>;
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <85>;
#cooling-cells = <2>;
};
cpu1: cpu@001 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0100>;
enable-method = "psci";
clock-frequency = <1701000000>;
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <85>;
#cooling-cells = <2>;
};
cpu2: cpu@002 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0200>;
enable-method = "psci";
clock-frequency = <1701000000>;
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <85>;
#cooling-cells = <2>;
};
cpu3: cpu@003 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0300>;
enable-method = "psci";
clock-frequency = <1701000000>;
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <85>;
#cooling-cells = <2>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
#if 0
idle-states {
entry-method = "arm,psci";
cpuoff_l: cpuoff_l {
compatible = "mediatek,idle-state";
arm,psci-suspend-param = <0x00010001>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <100>;
min-residency-us = <1600>;
};
clusteroff_l: clusteroff_l {
compatible = "mediatek,idle-state";
arm,psci-suspend-param = <0x01010001>;
local-timer-stop;
entry-latency-us = <100>;
exit-latency-us = <250>;
min-residency-us = <2100>;
};
mcusysoff: mcusysoff {
compatible = "mediatek,idle-state";
arm,psci-suspend-param = <0x01010002>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2600>;
};
};
#endif
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
dsu-pmu-0 {
compatible = "arm,dsu-pmu";
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
dvfsp: dvfsp@0011bc00 {
compatible = "mediatek,mcupm-dvfsp";
reg = <0 0x0011bc00 0 0x1400>;
nvmem = <&efuse>;
nvmem-names = "mtk_efuse";
nvmem-cells = <&efuse_segment>;
nvmem-cell-names = "efuse_segment_cell";
};
leakage@1100b000 {
compatible = "mediatek,leakage";
reg = <0 0x1100b000 0 0x1000>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_LOW>;
nvmem = <&efuse>;
nvmem-names = "mtk_efuse";
nvmem-cells = <&efuse_segment>;
nvmem-cell-names = "efuse_segment_cell";
n-domain = <7>;
domain = "LL", "CCI", "VCORE", "MODEM_NR", "VSRAM_CPULL", "VSRAM_MODEM", "VCORE_OFF";
LL = <750 30 0x224 0 0 1>;
CCI = <750 30 0x220 24 0 1>;
VCORE = <750 30 0x21C 16 0 1>;
MODEM_NR = <825 30 0x21C 8 0 1>;
VSRAM_CPULL = <750 30 0X228 16 0 1>;
VSRAM_MODEM = <825 30 0X22C 0 0 1>;
VCORE_OFF = <550 30 0x224 16 0 1>;
};
memory {
device_type = "memory";
#if defined(CONFIG_MTK_MEMORY_SIZE) && (CONFIG_MTK_MEMORY_SIZE == 1024)
reg = <0 0x40000000 0 0x40000000>;
#elif defined(CONFIG_MTK_MEMORY_SIZE) && (CONFIG_MTK_MEMORY_SIZE == 896)
reg = <0 0x40000000 0 0x38000000>;
#elif defined(CONFIG_MTK_MEMORY_SIZE) && (CONFIG_MTK_MEMORY_SIZE == 768)
reg = <0 0x40000000 0 0x30000000>;
#elif defined(CONFIG_MTK_MEMORY_SIZE) && (CONFIG_MTK_MEMORY_SIZE == 640)
reg = <0 0x40000000 0 0x28000000>;
#else
reg = <0 0x40000000 0 0x20000000>;
#endif
};
wed: wed@15010000 {
compatible = "mediatek,wed";
wed_num = <2>;
/* add this property for wed get the pci slot number. */
pci_slot_map = <0>, <1>;
reg = <0 0x15010000 0 0x1000>,
<0 0x15011000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>;
};
wed2: wed2@15011000 {
compatible = "mediatek,wed2";
wed_num = <2>;
reg = <0 0x15010000 0 0x1000>,
<0 0x15011000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>;
};
wdma: wdma@15102800 {
compatible = "mediatek,wed-wdma";
reg = <0 0x15102800 0 0x400>,
<0 0x15102c00 0 0x400>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
};
ap2woccif: ap2woccif@151A9000 {
compatible = "mediatek,ap2woccif";
reg = <0 0x151a9000 0 0x1000>,
<0 0x151ab000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>;
};
wocpu_sysram: wocpu@15180000 {
compatible = "mediatek,wocpu_sysram";
reg = <0 0x15180000 0 0x8000>;
shared = <1>;
};
wocpu_dlm: wocpu_dlm@1518E000 {
compatible = "mediatek,wocpu_dlm";
reg = <0 0x1518E000 0 0x2000>,
<0 0x15192000 0 0x2000>;
resets = <&ethsysrst 0>;
reset-names = "wocpu_rst";
};
cpu_boot: wocpu_boot@15194000 {
compatible = "mediatek,wocpu_boot";
reg = <0 0x15194000 0 0x1000>;
};
pcie_mirror: pcie_mirror@10201000 {
compatible = "mediatek,pcie-mirror";
reg = <0 0x10201000 0 0x1000>;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
reserve-memory-atf {
compatible = "mediatek,reserve-memory-atf";
no-map;
reg = <0 0x42FC0000 0 0x1FA000>;
};
reserve-memory-mcupm_share {
compatible = "mediatek,reserve-memory-mcupm_share";
no-map;
status = "okay";
#if defined(CONFIG_MTK_GMO_RAM_OPTIMIZE) || defined(CONFIG_MTK_MET_MEM_ALLOC)
reg = <0 0x42290000 0 0x210000>; /* 2M + 64K */
#else
reg = <0 0x42290000 0 0x610000>; /* 6M + 64K */
#endif
};
reserve-memory-sspm_share {
compatible = "mediatek,reserve-memory-sspm_share";
no-map;
status = "okay";
#if defined(CONFIG_MTK_GMO_RAM_OPTIMIZE) || defined(CONFIG_MTK_MET_MEM_ALLOC)
reg = <0 0x429A0000 0 0x210000>; /* 2M + 64K */
#else
reg = <0 0x429A0000 0 0x610000>; /* 6M + 64K */
#endif
};
gps_mem: gps-reserve-memory {
compatible = "mediatek,gps-reserve-memory";
no-map;
reg = <0 0x432ca000 0 0x60000>; /* 384KB */
};
reserved-memory-pstore {
compatible = "ramoops";
reg = <0x0 0x4332a000 0x0 0xe0000>;
record-size = <0x1000>;
console-size = <0x40000>;
ftrace-size = <0x1000>;
pmsg-size = <0x10000>;
};
reserved-memory-aee {
reg = <0x0 0x4340a000 0x0 0x100000>;
compatible = "mediatek,aee-lk";
};
reserved-memory-minirdump {
reg = <0x0 0x4350a000 0x0 0x10000>;
no-map;
compatible = "mediatek,minirdump";
};
reserved-memory-ram_console {
reg = <0x0 0x4351a000 0x0 0x10000>;
no-map;
compatible = "mediatek,ram_console";
};
reserved-memory-log_store {
reg = <0x0 0x4352a000 0x0 0x40000>;
compatible = "mediatek,log_store";
};
wocpu0_emi: wocpu0_emi@50000000 {
compatible = "mediatek,wocpu0_emi";
no-map;
reg = <0 0x50000000 0 0x80000>;
shared = <0>;
};
wocpu1_emi: wocpu1_emi@50040000 {
compatible = "mediatek,wocpu1_emi";
no-map;
reg = <0 0x50080000 0 0x80000>;
shared = <0>;
};
wocpu_data: wocpu_data@50100000 {
compatible = "mediatek,wocpu_data";
no-map;
reg = <0 0x50100000 0 0x180000>;
shared = <1>;
};
};
gic: interrupt-controller {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
#redistributor-regions = <1>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x40000>, // distributor
<0 0x0c040000 0 0x200000>; // redistributor
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
clkao: clkao {
compatible = "simple-bus";
};
clocks {
clk_null: clk_null {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
clk10m: clk10m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <10000000>;
};
clk26m: clk26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clk12m: clk12m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
clk32k: clk32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
};
clk13m: clk13m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <13000000>;
};
ulposc: ulposc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <260000000>;
};
};
topckgen_clk: syscon@10000000 {
compatible = "mediatek,mt6890-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
apmixedsys_clk: syscon@1000c000 {
compatible = "mediatek,mt6890-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0xe00>;
#clock-cells=<1>;
};
dbgsys_dem_clk: syscon@0d0a0000 {
compatible = "mediatek,mt6890-dbgsys_dem", "syscon";
reg = <0 0x0d0a0000 0 0x1000>;
#clock-cells = <1>;
};
infracfg_ao_clk: syscon@10001000 {
compatible = "mediatek,mt6890-infracfg_ao", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
pericfg_clk: syscon@10003000 {
compatible = "mediatek,mt6890-pericfg", "syscon";
reg = <0 0x10003000 0 0x1000>;
#clock-cells = <1>;
};
scpsys: power-controller@10006000 {
compatible = "mediatek,mt6890-scpsys", "syscon";
reg = <0 0x10006000 0 0x1000>;
#power-domain-cells = <1>;
infracfg = <&infracfg_ao_clk>;
clocks = <&topckgen_clk CLK_TOP_MM_SEL>,
<&topckgen_clk CLK_TOP_MFG_SEL>,
<&topckgen_clk CLK_TOP_SNPS_ETH_312P5M_SEL>,
<&topckgen_clk CLK_TOP_SNPS_ETH_250M_SEL>,
<&topckgen_clk CLK_TOP_SNPS_ETH_62P4M_PTP_SEL>,
<&topckgen_clk CLK_TOP_SNPS_ETH_50M_RMII_SEL>,
<&topckgen_clk CLK_TOP_EIP97_SEL>,
<&infracfg_ao_clk CLK_IFRAO_AUDIO_26M_BCLK>;
clock-names = "mm",
"mfg",
"snps_eth_312p5m_sel",
"snps_eth_250m_sel",
"snps_ptp_sel",
"snps_rmii_sel",
"eip97_sel",
"audio";
/*status="disabled";*/
};
gce_clk: syscon@10228000 {
compatible = "mediatek,mt6890-gce", "syscon";
reg = <0 0x10228000 0 0x1000>;
#clock-cells = <1>;
};
audsys_clk: syscon@11210000 {
compatible = "mediatek,mt6890-audsys", "syscon";
reg = <0 0x11210000 0 0x1000>;
#clock-cells = <1>;
};
imp_iic_wrap_e_clk: syscon@11c46000 {
compatible = "mediatek,mt6890-imp_iic_wrap_e", "syscon";
reg = <0 0x11c46000 0 0x1000>;
#clock-cells = <1>;
};
mfgsys_clk: syscon@13fbf000 {
compatible = "mediatek,mt6890-mfgsys", "syscon";
reg = <0 0x13fbf000 0 0x1000>;
#clock-cells = <1>;
};
mmsys_config_clk: syson@14000000 {
compatible = "mediatek,mt6890-mmsys_config", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
mtk_lpm: mtk_lpm {
compatible = "mediatek,mtk-lpm";
#address-cells = <2>;
#size-cells = <2>;
ranges;
suspend-method = "system";
irq-remain = <&edge_keypad &edge_mdwdt>;
resource-ctrl = <&bus26m &infra &syspll>,
<&dram_s0 &dram_s1>;
constraints = <&rc_bus26m &rc_syspll &rc_dram>;
lpm_sysram: lpm_sysram@0011b500 {
compatible = "mediatek,lpm-sysram";
reg = <0 0x0011b500 0 0x300>;
};
irq-remain-list {
edge_keypad: edge_keypad {
target = <&keypad>;
value = <1 0 0 0x4>;
};
edge_mdwdt: edge_mdwdt {
target = <&mddriver>;
value = <1 0 0 0x02000000>;
};
};
resource-ctrl-list {
bus26m: bus26m {
id = <0x00000000>;
value = <0>;
};
infra: infra {
id = <0x00000001>;
value = <0>;
};
syspll: syspll {
id = <0x00000002>;
value = <0>;
};
dram_s0: dram_s0 {
id = <0x00000003>;
value = <0>;
};
dram_s1: dram_s1 {
id = <0x00000004>;
value = <0>;
};
};
constraint-list {
rc_bus26m: rc_bus26m {
id = <0x00000000>;
value = <1>;
};
rc_syspll: rc_syspll {
id = <0x00000001>;
value = <1>;
};
rc_dram: rc_dram {
id = <0x00000002>;
value = <1>;
};
};
};
cpupm_sysram: cpupm-sysram@0011b000 {
compatible = "mediatek,cpupm-sysram";
reg = <0 0x0011b000 0 0x500>;
};
mcusys_ctrl: mcusys-ctrl@0c53a000 {
compatible = "mediatek,mcusys-ctrl";
reg = <0 0x0c53a000 0 0x1000>;
};
tboard_thermistor1: thermal-ntc1 {
compatible = "mediatek,mt6880-board-ntc";
#thermal-sensor-cells = <0>;
reg = <0 0x1001C0D4 0 0x4>; /* TIA DATA T0 */
pmic_auxadc = <&pmic_auxadc>;
temperature-lookup-table = <
(-40000) 4397119
(-39000) 4092874
(-38000) 3811717
(-37000) 3551749
(-36000) 3311236
(-35000) 3088599
(-34000) 2882396
(-33000) 2691310
(-32000) 2514137
(-31000) 2349778
(-30000) 2197225
(-29000) 2055558
(-28000) 1923932
(-27000) 1801573
(-26000) 1687773
(-25000) 1581881
(-24000) 1483100
(-23000) 1391113
(-22000) 1305413
(-21000) 1225531
(-20000) 1151037
(-19000) 1081535
(-18000) 1016661
(-17000) 956080
(-16000) 899481
(-15000) 846579
(-14000) 797111
(-13000) 750834
(-12000) 707524
(-11000) 666972
(-10000) 628988
(-9000) 593342
(-8000) 559931
(-7000) 528602
(-6000) 499212
(-5000) 471632
(-4000) 445772
(-3000) 421480
(-2000) 398652
(-1000) 377193
0 357012
1000 338006
2000 320122
3000 303287
4000 287434
5000 272500
6000 258426
7000 245160
8000 232649
9000 220847
10000 209710
11000 199196
12000 189268
13000 179890
14000 171027
15000 162651
16000 154726
17000 147232
18000 140142
19000 133432
20000 127080
21000 121066
22000 115368
23000 109970
24000 104852
25000 100000
26000 95398
27000 91032
28000 86889
29000 82956
30000 79222
31000 75675
32000 72306
33000 69104
34000 66061
35000 63167
36000 60415
37000 57797
38000 55306
39000 52934
40000 50677
41000 48528
42000 46482
43000 44533
44000 42675
45000 40904
46000 39213
47000 37601
48000 36063
49000 34595
50000 33195
51000 31859
52000 30584
53000 29366
54000 28203
55000 27091
56000 26028
57000 25013
58000 24042
59000 23113
60000 22224
61000 21374
62000 20560
63000 19782
64000 19036
65000 18322
66000 17640
67000 16986
68000 16360
69000 15759
70000 15184
71000 14631
72000 14100
73000 13591
74000 13103
75000 12635
76000 12187
77000 11756
78000 11343
79000 10946
80000 10565
81000 10199
82000 9847
83000 9509
84000 9184
85000 8872
86000 8572
87000 8283
88000 8005
89000 7738
90000 7481
91000 7234
92000 6997
93000 6769
94000 6548
95000 6337
96000 6132
97000 5934
98000 5744
99000 5561
100000 5384
101000 5214
102000 5051
103000 4893
104000 4741
105000 4594
106000 4453
107000 4316
108000 4184
109000 4057
110000 3934
111000 3816
112000 3701
113000 3591
114000 3484
115000 3380
116000 3281
117000 3185
118000 3093
119000 3003
120000 2916
121000 2832
122000 2751
123000 2672
124000 2596
125000 2522>;
};
tboard_thermistor2: thermal-ntc2 {
compatible = "mediatek,mt6880-board-ntc";
#thermal-sensor-cells = <0>;
reg = <0 0x1001C0D8 0 0x4>; /* TIA DATA T1 */
pmic_auxadc = <&pmic_auxadc>;
temperature-lookup-table = <
(-40000) 4397119
(-39000) 4092874
(-38000) 3811717
(-37000) 3551749
(-36000) 3311236
(-35000) 3088599
(-34000) 2882396
(-33000) 2691310
(-32000) 2514137
(-31000) 2349778
(-30000) 2197225
(-29000) 2055558
(-28000) 1923932
(-27000) 1801573
(-26000) 1687773
(-25000) 1581881
(-24000) 1483100
(-23000) 1391113
(-22000) 1305413
(-21000) 1225531
(-20000) 1151037
(-19000) 1081535
(-18000) 1016661
(-17000) 956080
(-16000) 899481
(-15000) 846579
(-14000) 797111
(-13000) 750834
(-12000) 707524
(-11000) 666972
(-10000) 628988
(-9000) 593342
(-8000) 559931
(-7000) 528602
(-6000) 499212
(-5000) 471632
(-4000) 445772
(-3000) 421480
(-2000) 398652
(-1000) 377193
0 357012
1000 338006
2000 320122
3000 303287
4000 287434
5000 272500
6000 258426
7000 245160
8000 232649
9000 220847
10000 209710
11000 199196
12000 189268
13000 179890
14000 171027
15000 162651
16000 154726
17000 147232
18000 140142
19000 133432
20000 127080
21000 121066
22000 115368
23000 109970
24000 104852
25000 100000
26000 95398
27000 91032
28000 86889
29000 82956
30000 79222
31000 75675
32000 72306
33000 69104
34000 66061
35000 63167
36000 60415
37000 57797
38000 55306
39000 52934
40000 50677
41000 48528
42000 46482
43000 44533
44000 42675
45000 40904
46000 39213
47000 37601
48000 36063
49000 34595
50000 33195
51000 31859
52000 30584
53000 29366
54000 28203
55000 27091
56000 26028
57000 25013
58000 24042
59000 23113
60000 22224
61000 21374
62000 20560
63000 19782
64000 19036
65000 18322
66000 17640
67000 16986
68000 16360
69000 15759
70000 15184
71000 14631
72000 14100
73000 13591
74000 13103
75000 12635
76000 12187
77000 11756
78000 11343
79000 10946
80000 10565
81000 10199
82000 9847
83000 9509
84000 9184
85000 8872
86000 8572
87000 8283
88000 8005
89000 7738
90000 7481
91000 7234
92000 6997
93000 6769
94000 6548
95000 6337
96000 6132
97000 5934
98000 5744
99000 5561
100000 5384
101000 5214
102000 5051
103000 4893
104000 4741
105000 4594
106000 4453
107000 4316
108000 4184
109000 4057
110000 3934
111000 3816
112000 3701
113000 3591
114000 3484
115000 3380
116000 3281
117000 3185
118000 3093
119000 3003
120000 2916
121000 2832
122000 2751
123000 2672
124000 2596
125000 2522>;
};
tboard_thermistor3: thermal-ntc3 {
compatible = "mediatek,mt6880-board-ntc";
#thermal-sensor-cells = <0>;
reg = <0 0x1001C0DC 0 0x4>; /* TIA DATA T2 */
pmic_auxadc = <&pmic_auxadc>;
temperature-lookup-table = <
(-40000) 4397119
(-39000) 4092874
(-38000) 3811717
(-37000) 3551749
(-36000) 3311236
(-35000) 3088599
(-34000) 2882396
(-33000) 2691310
(-32000) 2514137
(-31000) 2349778
(-30000) 2197225
(-29000) 2055558
(-28000) 1923932
(-27000) 1801573
(-26000) 1687773
(-25000) 1581881
(-24000) 1483100
(-23000) 1391113
(-22000) 1305413
(-21000) 1225531
(-20000) 1151037
(-19000) 1081535
(-18000) 1016661
(-17000) 956080
(-16000) 899481
(-15000) 846579
(-14000) 797111
(-13000) 750834
(-12000) 707524
(-11000) 666972
(-10000) 628988
(-9000) 593342
(-8000) 559931
(-7000) 528602
(-6000) 499212
(-5000) 471632
(-4000) 445772
(-3000) 421480
(-2000) 398652
(-1000) 377193
0 357012
1000 338006
2000 320122
3000 303287
4000 287434
5000 272500
6000 258426
7000 245160
8000 232649
9000 220847
10000 209710
11000 199196
12000 189268
13000 179890
14000 171027
15000 162651
16000 154726
17000 147232
18000 140142
19000 133432
20000 127080
21000 121066
22000 115368
23000 109970
24000 104852
25000 100000
26000 95398
27000 91032
28000 86889
29000 82956
30000 79222
31000 75675
32000 72306
33000 69104
34000 66061
35000 63167
36000 60415
37000 57797
38000 55306
39000 52934
40000 50677
41000 48528
42000 46482
43000 44533
44000 42675
45000 40904
46000 39213
47000 37601
48000 36063
49000 34595
50000 33195
51000 31859
52000 30584
53000 29366
54000 28203
55000 27091
56000 26028
57000 25013
58000 24042
59000 23113
60000 22224
61000 21374
62000 20560
63000 19782
64000 19036
65000 18322
66000 17640
67000 16986
68000 16360
69000 15759
70000 15184
71000 14631
72000 14100
73000 13591
74000 13103
75000 12635
76000 12187
77000 11756
78000 11343
79000 10946
80000 10565
81000 10199
82000 9847
83000 9509
84000 9184
85000 8872
86000 8572
87000 8283
88000 8005
89000 7738
90000 7481
91000 7234
92000 6997
93000 6769
94000 6548
95000 6337
96000 6132
97000 5934
98000 5744
99000 5561
100000 5384
101000 5214
102000 5051
103000 4893
104000 4741
105000 4594
106000 4453
107000 4316
108000 4184
109000 4057
110000 3934
111000 3816
112000 3701
113000 3591
114000 3484
115000 3380
116000 3281
117000 3185
118000 3093
119000 3003
120000 2916
121000 2832
122000 2751
123000 2672
124000 2596
125000 2522>;
};
tboard_thermistor4: thermal-ntc4 {
compatible = "mediatek,mt6880-board-ntc";
#thermal-sensor-cells = <0>;
reg = <0 0x1001C0E0 0 0x4>; /* TIA DATA T3 */
pmic_auxadc = <&pmic_auxadc>;
temperature-lookup-table = <
(-40000) 4397119
(-39000) 4092874
(-38000) 3811717
(-37000) 3551749
(-36000) 3311236
(-35000) 3088599
(-34000) 2882396
(-33000) 2691310
(-32000) 2514137
(-31000) 2349778
(-30000) 2197225
(-29000) 2055558
(-28000) 1923932
(-27000) 1801573
(-26000) 1687773
(-25000) 1581881
(-24000) 1483100
(-23000) 1391113
(-22000) 1305413
(-21000) 1225531
(-20000) 1151037
(-19000) 1081535
(-18000) 1016661
(-17000) 956080
(-16000) 899481
(-15000) 846579
(-14000) 797111
(-13000) 750834
(-12000) 707524
(-11000) 666972
(-10000) 628988
(-9000) 593342
(-8000) 559931
(-7000) 528602
(-6000) 499212
(-5000) 471632
(-4000) 445772
(-3000) 421480
(-2000) 398652
(-1000) 377193
0 357012
1000 338006
2000 320122
3000 303287
4000 287434
5000 272500
6000 258426
7000 245160
8000 232649
9000 220847
10000 209710
11000 199196
12000 189268
13000 179890
14000 171027
15000 162651
16000 154726
17000 147232
18000 140142
19000 133432
20000 127080
21000 121066
22000 115368
23000 109970
24000 104852
25000 100000
26000 95398
27000 91032
28000 86889
29000 82956
30000 79222
31000 75675
32000 72306
33000 69104
34000 66061
35000 63167
36000 60415
37000 57797
38000 55306
39000 52934
40000 50677
41000 48528
42000 46482
43000 44533
44000 42675
45000 40904
46000 39213
47000 37601
48000 36063
49000 34595
50000 33195
51000 31859
52000 30584
53000 29366
54000 28203
55000 27091
56000 26028
57000 25013
58000 24042
59000 23113
60000 22224
61000 21374
62000 20560
63000 19782
64000 19036
65000 18322
66000 17640
67000 16986
68000 16360
69000 15759
70000 15184
71000 14631
72000 14100
73000 13591
74000 13103
75000 12635
76000 12187
77000 11756
78000 11343
79000 10946
80000 10565
81000 10199
82000 9847
83000 9509
84000 9184
85000 8872
86000 8572
87000 8283
88000 8005
89000 7738
90000 7481
91000 7234
92000 6997
93000 6769
94000 6548
95000 6337
96000 6132
97000 5934
98000 5744
99000 5561
100000 5384
101000 5214
102000 5051
103000 4893
104000 4741
105000 4594
106000 4453
107000 4316
108000 4184
109000 4057
110000 3934
111000 3816
112000 3701
113000 3591
114000 3484
115000 3380
116000 3281
117000 3185
118000 3093
119000 3003
120000 2916
121000 2832
122000 2751
123000 2672
124000 2596
125000 2522>;
};
trm: thermal_risk_monitor {
compatible = "mediatek,mt6880-trm";
};
pmic_temp: pmic_temp {
compatible = "mediatek,mt6330-pmic-temp";
io-channels =
<&pmic_auxadc AUXADC_CHIP_TEMP>;
io-channel-names =
"pmic_chip_temp";
#thermal-sensor-cells = <0>;
nvmem-cells = <&thermal_efuse_data1>;
nvmem-cell-names = "t_e_data1@6c";
pmic_temp,cali_factor = <1681>;
pmic_temp,iio_chan = <0>;
};
pmic_vcore: pmic_vcore {
compatible = "mediatek,mt6330-pmic-temp";
io-channels =
<&pmic_auxadc AUXADC_VCORE_TEMP>;
io-channel-names =
"pmic_buck1_temp";
#thermal-sensor-cells = <0>;
nvmem-cells = <&thermal_efuse_data1>;
nvmem-cell-names = "t_e_data1@6c";
pmic_temp,cali_factor = <1863>;
pmic_temp,iio_chan = <1>;
};
pmic_vproc: pmic_vproc {
compatible = "mediatek,mt6330-pmic-temp";
io-channels =
<&pmic_auxadc AUXADC_VPROC_TEMP>;
io-channel-names =
"pmic_buck2_temp";
#thermal-sensor-cells = <0>;
nvmem-cells = <&thermal_efuse_data1>;
nvmem-cell-names = "t_e_data1@6c";
pmic_temp,cali_factor = <1863>;
pmic_temp,iio_chan = <2>;
};
pmic_vgpu: pmic_vgpu {
compatible = "mediatek,mt6330-pmic-temp";
io-channels =
<&pmic_auxadc AUXADC_VGPU_TEMP>;
io-channel-names =
"pmic_buck3_temp";
#thermal-sensor-cells = <0>;
nvmem-cells = <&thermal_efuse_data1>;
nvmem-cell-names = "t_e_data1@6c";
pmic_temp,cali_factor = <1863>;
pmic_temp,iio_chan = <3>;
};
md_rf_ic: md-rf-ic {
compatible = "mediatek,md-rf";
#thermal-sensor-cells = <0>;
};
md_cooler_mutt: mutt {
compatible = "mediatek,mt6297-md-cooler-mutt";
mutt_pa1: mutt-pa1 {
id = <0>;
#cooling-cells = <2>;
};
mutt_pa1_no_ims: mutt-pa1-no-ims {
id = <0>;
#cooling-cells = <2>;
};
mutt_pa2: mutt-pa2 {
id = <1>;
#cooling-cells = <2>;
};
mutt_pa2_no_ims: mutt-pa2-no-ims {
id = <1>;
#cooling-cells = <2>;
};
};
md_cooler_tx_pwr: tx-pwr {
compatible = "mediatek,md-cooler-tx-pwr";
tx_pwr_pa1: tx-pwr-pa1 {
id = <0>;
#cooling-cells = <2>;
};
tx_pwr_pa2: tx-pwr-pa2 {
id = <1>;
#cooling-cells = <2>;
};
};
md_cooler_scg_off: scg-off {
compatible = "mediatek,md-cooler-scg-off";
scg_off_pa2: scg-off-pa2 {
id = <1>;
#cooling-cells = <2>;
};
};
thermal-zones {
soc_max {
polling-delay = <100>; /* milliseconds */
polling-delay-passive = <50>; /* milliseconds */
thermal-sensors = <&lvts 0>;
sustainable-power = <1700>;
trips {
threshold: trip-point@0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
ipa_target: trip-point@1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
soc_max_crit: soc_max_crit@0 {
temperature = <115000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&ipa_target>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
map1 {
trip = <&ipa_target>;
cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
cpu_little0 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 1>;
};
cpu_little1 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 2>;
};
cpu_little2 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 3>;
};
cpu_little3 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 4>;
};
gpu0 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 5>;
};
gpu1 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 6>;
};
dramc {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 7>;
};
mmsys {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 8>;
};
md_5g {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 9>;
};
md_4g {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 10>;
};
md_3g {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 11>;
};
soc_dram_ntc {
polling-delay = <1000>; /* milliseconds */
polling-delay-passive = <1000>; /* milliseconds */
thermal-sensors = <&tboard_thermistor1>;
trips {
soc_dram_ntc_crit: soc_dram_ntc_crit@0 {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
nrpa_ntc {
polling-delay = <1000>; /* milliseconds */
polling-delay-passive = <1000>; /* milliseconds */
thermal-sensors = <&tboard_thermistor2>;
trips {
nrpa_ntc_target: nrpa_ntc_trip@0 {
temperature = <82000>;
hysteresis = <2000>;
type = "passive";
};
nrpa_ntc_no_ims: nrpa_ntc_trip@1 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
};
cooling-maps {
map0 {
trip = <&nrpa_ntc_target>;
cooling-device = <&mutt_pa2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&nrpa_ntc_no_ims>;
cooling-device = <&mutt_pa2_no_ims THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
ltepa_ntc {
polling-delay = <1000>; /* milliseconds */
polling-delay-passive = <1000>; /* milliseconds */
thermal-sensors = <&tboard_thermistor3>;
trips {
ltepa_ntc_target: ltepa_ntc_trip@0 {
temperature = <82000>;
hysteresis = <2000>;
type = "passive";
};
ltepa_ntc_no_ims: ltepa_ntc_trip@1 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
ltepa_ntc_crit: ltepa_ntc_trip@2 {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&ltepa_ntc_target>;
cooling-device = <&mutt_pa1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&ltepa_ntc_no_ims>;
cooling-device = <&mutt_pa1_no_ims THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
rf_ntc {
polling-delay = <1000>; /* milliseconds */
polling-delay-passive = <1000>; /* milliseconds */
thermal-sensors = <&tboard_thermistor4>;
trips {
rf_ntc_crit: rf_ntc_crit@0 {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
pmic {
polling-delay = <1000>; /* milliseconds */
polling-delay-passive = <1000>; /* milliseconds */
thermal-sensors = <&pmic_temp>;
trips {
pmic_temp_crit: pmic_temp_crit@0 {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
};
pmic_vcore {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&pmic_vcore>;
};
pmic_vproc {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&pmic_vproc>;
};
pmic_vgpu {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&pmic_vgpu>;
};
md_rf {
polling-delay = <1000>; /* milliseconds */
polling-delay-passive = <1000>; /* milliseconds */
thermal-sensors = <&md_rf_ic>;
trips {
md_rf_crit: md_rf_crit@0 {
temperature = <117000>;
hysteresis = <2000>;
type = "critical";
};
};
};
conn_gps {
polling-delay = <1000>; /* milliseconds */
polling-delay-passive = <1000>; /* milliseconds */
thermal-sensors = <&consys>;
trips {
consys_max_crit: consys_max_crit@0 {
temperature = <117000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
chipid@08000000 {
compatible = "mediatek,chipid";
reg = <0 0x08000000 0 0x0004>,
<0 0x08000004 0 0x0004>,
<0 0x08000008 0 0x0004>,
<0 0x0800000c 0 0x0004>;
};
dbgtop@1000d000 {
compatible = "mediatek,dbgtop";
reg = <0 0x1000d000 0 0x1000>;
};
mcupm@0C540000 {
compatible = "mediatek,mcupm";
reg =<0 0x0C540000 0 0x22000>,
<0 0x0c55fb00 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c562018 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c562010 0 0x4>,
<0 0x0c55fba0 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c562018 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c562010 0 0x4>,
<0 0x0c55fc40 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c562018 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c562010 0 0x4>,
<0 0x0c55fce0 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c562018 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c562010 0 0x4>,
<0 0x0c55fd80 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c562018 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c562010 0 0x4>,
<0 0x0c55fe20 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c562018 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c562010 0 0x4>,
<0 0x0c55fec0 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c562018 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c562010 0 0x4>,
<0 0x0c55ff60 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c562018 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c562010 0 0x4>;
reg-names = "mcupm_base",
"mbox0_base",
"mbox0_set",
"mbox0_clr",
"mbox0_send",
"mbox0_recv",
"mbox1_base",
"mbox1_set",
"mbox1_clr",
"mbox1_send",
"mbox1_recv",
"mbox2_base",
"mbox2_set",
"mbox2_clr",
"mbox2_send",
"mbox2_recv",
"mbox3_base",
"mbox3_set",
"mbox3_clr",
"mbox3_send",
"mbox3_recv",
"mbox4_base",
"mbox4_set",
"mbox4_clr",
"mbox4_send",
"mbox4_recv",
"mbox5_base",
"mbox5_set",
"mbox5_clr",
"mbox5_send",
"mbox5_recv",
"mbox6_base",
"mbox6_set",
"mbox6_clr",
"mbox6_send",
"mbox6_recv",
"mbox7_base",
"mbox7_set",
"mbox7_clr",
"mbox7_send",
"mbox7_recv";
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mbox0",
"mbox1",
"mbox2",
"mbox3",
"mbox4",
"mbox5",
"mbox6",
"mbox7";
};
topckgen: topckgen@10000000 {
compatible = "mediatek,topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
};
dcm: dcm@10001000 {
compatible = "mediatek,mt6880-dcm";
reg = <0 0x10001000 0 0x1000>,
<0 0x10002000 0 0x1000>,
<0 0x10022000 0 0x1000>,
<0 0x10219000 0 0x1000>,
<0 0x10230000 0 0x2000>,
<0 0x10235000 0 0x1000>,
<0 0x10238000 0 0x1000>,
<0 0x10240000 0 0x2000>,
<0 0x10248000 0 0x1000>,
<0 0xc538000 0 0x5000>,
<0 0xc53a800 0 0x1000>;
reg-names = "infracfg_ao",
"infracfg_ao_mem",
"infra_ao_bcrm",
"emi",
"dramc_ch0_top0",
"chn0_emi",
"dramc_ch0_top5",
"dramc_ch1_top0",
"dramc_ch1_top5",
"mp_cpusys_top",
"cpccfg_reg";
};
infracfg_ao: infracfg_ao@10001000 {
compatible = "mediatek,infracfg_ao", "syscon", "simple-mfd";
reg = <0 0x10001000 0 0x1000>;
infracfg_rst: reset-controller {
compatible = "ti,syscon-reset";
#reset-cells = <1>;
ti,reset-bits = <
0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
0x730 12 0x734 12 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
>;
};
};
infracfg_ao_mem@10002000 {
compatible = "mediatek,infracfg_ao_mem";
reg = <0 0x10002000 0 0x1000>;
};
pericfg@10003000 {
compatible = "mediatek,pericfg";
reg = <0 0x10003000 0 0x1000>;
};
gpio_usage_mapping: gpio_usage_mapping {
compatible = "mediatek,gpio_usage_mapping";
};
gpio: gpio@10005000 {
compatible = "mediatek,gpio";
reg = <0 0x10005000 0 0x1000>;
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt2735-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11c10000 0 0x1000>,
<0 0x11c20000 0 0x1000>,
<0 0x11d00000 0 0x1000>,
<0 0x11d10000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11e00000 0 0x1000>,
<0 0x11f00000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "gpio", "iocfg_rm",
"iocfg_rb", "iocfg_bl",
"iocfg_bm", "iocfg_br",
"iocfg_lt", "iocfg_tl",
"eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 235>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
};
sleep: sleep@10006000 {
compatible = "mediatek,sleep", "syscon";
reg = <0 0x10006000 0 0x1000>;
};
spmtwam: spmtwam@10006000 {
compatible = "mediatek,spmtwam";
reg = <0 0x10006000 0 0x1000>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
spm_twam_con = <0xa0>;
spm_twam_window_len = <0xa4>;
spm_twam_idle_sel = <0xa8>;
spm_irq_mask = <0xb4>;
spm_irq_sta = <0x128>;
spm_twam_last_sta0 = <0x1d0>;
spm_twam_last_sta1 = <0x1d4>;
spm_twam_last_sta2 = <0x1d8>;
spm_twam_last_sta3 = <0x1dc>;
};
srclken: srclken@10006500 {
compatible = "mediatek,srclken";
reg = <0 0x10006500 0 0x1000>,
<0 0x105c4000 0 0x1000>,
<0 0x10005000 0 0x1000>;
reg-names = "srclken", "scpdvfs", "gpio";
srclken-mode = "bringup";
srclken-rst-cfg = <0x0>;
srclken-central-cfg = <0x4 0x8 0x1C>;
srclken-cmd-cfg = <0xC>;
srclken-pmic-cfg = <0x10 0x14>;
srclken-dcxo-fpm-cfg = <0x18>;
srclken-subsys-cfg = <0x20>;
srclken-misc-cfg = <0xB4>;
srclken-spm-cfg = <0xB8>;
srclken-subsys-if-cfg = <0xBC>;
srclken-fsm-sta = <0x60>;
srclken-cmd-sta = <0x64 0x68>;
srclken-spi-sta = <0x6C>;
srclken-pipo-sta = <0x70>;
srclken-subsys-sta = <0x80>;
srclken-dbg-trace-sta = <0xC0 0xC4>;
srclken-scp-enable = "n";
scp-vreq-cfg = <0x54>;
scp-rc-vreq-bit = <27 28>;
srclken-gpio-enable = "n";
gpio-dir-cfg = <0x0>;
gpio-dout-cfg = <0x100>;
gpio-pull-bit = <6>;
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt2735-wdt";
reg = <0 0x10007000 0 0x1000>;
};
apxgpt@10008000 {
compatible = "mediatek,apxgpt";
reg = <0 0x10008000 0 0x1000>;
interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
};
sej@1000a000 {
compatible = "mediatek,sej";
reg = <0 0x1000a000 0 0x1000>;
interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
};
apmixed: apmixed@1000c000 {
compatible = "mediatek,apmixed";
reg = <0 0x1000c000 0 0xe00>;
};
fhctl@1000ce00 {
compatible = "mediatek,mt6880-fhctl";
reg = <0 0x1000ce00 0 0x200>;
mediatek,apmixed = <&apmixed>;
armpll_ll {
mediatek,fh-id = <0>;
mediatek,fh-pll-id = <CLK_APMIXED_ARMPLL_LL>;
mediatek,fh-cpu-pll;
};
mainpll {
mediatek,fh-id = <1>;
mediatek,fh-pll-id = <CLK_APMIXED_MAINPLL>;
};
mpll {
mediatek,fh-id = <2>;
mediatek,fh-pll-id = <CLK_APMIXED_MPLL>;
};
msdcpll {
mediatek,fh-id = <4>;
mediatek,fh-pll-id = <CLK_APMIXED_MSDCPLL>;
};
mfgpll {
mediatek,fh-id = <5>;
mediatek,fh-pll-id = <CLK_APMIXED_MFGPLL>;
};
mmpll {
mediatek,fh-id = <6>;
mediatek,fh-pll-id = <CLK_APMIXED_MMPLL>;
};
};
pwrap@1000d000 {
compatible = "mediatek,pwrap";
reg = <0 0x1000d000 0 0x1000>;
};
keypad:kp@10010000 {
compatible = "mediatek,kp";
reg = <0 0x10010000 0 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
clocks = <&clk26m>;
clock-names = "kpd";
};
gpio-keys {
compatible = "gpio-keys";
button0 {
label = "Modem RF";
gpios = <&pio 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PHONE>;
};
button1 {
label = "GPS";
gpios = <&pio 7 GPIO_ACTIVE_LOW>;
linux,code = <246>;
};
/*
button2 {
label = "Factory Mode";
gpios = <&pio 112 GPIO_ACTIVE_LOW>;
linux,code = <112>;
};
button3 {
label = "WIFI";
gpios = <&pio 114 GPIO_ACTIVE_LOW>;
linux,code = <114>;
};
button4 {
label = "WPS";
gpios = <&pio 115 GPIO_ACTIVE_LOW>;
linux,code = <115>;
};
*/
};
topmisc@10011000 {
compatible = "mediatek,topmisc";
reg = <0 0x10011000 0 0x1000>;
};
dvfsrc: dvfsrc@10012000 {
compatible = "mediatek,mt6890-dvfsrc";
reg = <0 0x10012000 0 0x1000>,
<0 0x10006000 0 0x1000>;
reg-names = "dvfsrc", "spm";
#interconnect-cells = <1>;
dvfsrc_vcore: dvfsrc-vcore {
regulator-name = "dvfsrc-vcore";
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <750000>;
regulator-always-on;
};
dvfsrc_freq_opp6: opp6 {
opp-peak-KBps = <0>;
};
dvfsrc_freq_opp5: opp5 {
opp-peak-KBps = <2500000>;
};
dvfsrc_freq_opp4: opp4 {
opp-peak-KBps = <3800000>;
};
dvfsrc_freq_opp3: opp3 {
opp-peak-KBps = <5100000>;
};
dvfsrc_freq_opp2: opp2 {
opp-peak-KBps = <5900000>;
};
dvfsrc_freq_opp1: opp1 {
opp-peak-KBps = <7600000>;
};
dvfsrc_freq_opp0: opp0 {
opp-peak-KBps = <10200000>;
};
dvfsrc-helper {
compatible = "mediatek,dvfsrc-helper";
vcore-supply = <&mt6330_vcore_buck_reg>;
rc-vcore-supply = <&dvfsrc_vcore>;
interconnects = <&dvfsrc MT6873_MASTER_DBGIF &dvfsrc MT6873_SLAVE_DDR_EMI>;
interconnect-names = "icc-perf-bw";
required-opps = <&dvfsrc_freq_opp0>,
<&dvfsrc_freq_opp1>,
<&dvfsrc_freq_opp2>,
<&dvfsrc_freq_opp3>,
<&dvfsrc_freq_opp4>,
<&dvfsrc_freq_opp5>,
<&dvfsrc_freq_opp6>;
};
dvfsrc-met {
compatible = "mediatek,dvfsrc-met";
};
};
mbist_ao@10013000 {
compatible = "mediatek,mbist_ao";
reg = <0 0x10013000 0 0x1000>;
};
dpmaif_ao@10014000 {
compatible = "mediatek,dpmaif_ao";
reg = <0 0x10014000 0 0x1000>;
};
aes_top0@10016000 {
compatible = "mediatek,aes_top0";
reg = <0 0x10016000 0 0x1000>;
};
timer: timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <13000000>;
};
sys_timer@10017000 {
compatible = "mediatek,sys_timer",
"mediatek,mt6765-timer";
reg = <0 0x10017000 0 0x1000>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk13m>;
};
modem_temp_share@10018000 {
compatible = "mediatek,modem_temp_share";
reg = <0 0x10018000 0 0x1000>;
};
security_ao@1001a000 {
compatible = "mediatek,security_ao";
reg = <0 0x1001a000 0 0x1000>;
};
topckgen_ao@1001b000 {
compatible = "mediatek,topckgen_ao";
reg = <0 0x1001b000 0 0x1000>;
};
devapc_ao_mm@1001c000 {
compatible = "mediatek,devapc_ao_mm";
reg = <0 0x1001c000 0 0x1000>;
};
sleep_sram@1001e000 {
compatible = "mediatek,sleep_sram";
reg = <0 0x1001e000 0 0x4000>;
};
bcrm_ao_peri@10022000 {
compatible = "mediatek,bcrm_ao_peri";
reg = <0 0x10022000 0 0x1000>;
};
debug_ao_peri@10023000 {
compatible = "mediatek,debug_ao_peri";
reg = <0 0x10023000 0 0x1000>;
};
mhccif: mhccif@10024000 {
compatible = "mediatek,mt6880-mhccif";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0 0x10024000 0 0x1000>,
<0 0x10025000 0 0x1000>;
reg-names = "mhccif_rc", "mhccif_ep";
interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
spmi_bus: spmi@10026000 {
compatible = "mediatek,mt6880-pmif-m", "syscon";
reg = <0 0x10026000 0 0x0008F0>,
<0 0x10029000 0 0x000110>;
reg-names = "pmif", "spmimst";
interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
<&pio 216 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pmif_irq", "rcs_irq";
interrupt-controller;
#interrupt-cells = <1>;
irq_event_en = <0x0 0x00180000 0x0 0x0 0x0>;
clocks = <&infracfg_ao_clk CLK_IFRAO_PMIC_AP_SET>,
<&infracfg_ao_clk CLK_IFRAO_PMIC_TMR_SET>,
<&topckgen_clk CLK_TOP_PWRAP_ULPOSC_SEL>,
<&topckgen_clk CLK_TOP_OSC_D10>,
<&topckgen_clk CLK_TOP_TCK_26M_MX9>,
<&topckgen_clk CLK_TOP_SPMI_M_MST_SEL>,
<&topckgen_clk CLK_TOP_TCK_26M_MX9>,
<&topckgen_clk CLK_TOP_OSC_D10>;
clock-names = "pmif_sys_ck",
"pmif_tmr_ck",
"pmif_clk_mux",
"pmif_clk_osc_d10",
"pmif_clk26m",
"spmimst_clk_mux",
"spmimst_clk26m",
"spmimst_clk_osc_d10";
swinf_ch_start = <6>;
ap_swinf_no = <2>;
grpid = <0xB>;
#address-cells = <2>;
#size-cells = <0>;
};
spmi_p_bus: spmi_p@10027000 {
compatible = "mediatek,mt6880-pmif-p";
reg = <0 0x10027000 0 0x0008F0>,
<0 0x10028000 0 0x000110>;
reg-names = "pmif", "spmimst";
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pmif_irq";
irq_event_en = <0x0 0x0 0x0 0x0 0x0>;
clocks = <&infracfg_ao_clk CLK_IFRAO_PMIC_AP_SET>,
<&infracfg_ao_clk CLK_IFRAO_PMIC_TMR_SET>,
<&topckgen_clk CLK_TOP_PWRAP_ULPOSC_SEL>,
<&topckgen_clk CLK_TOP_OSC_D10>,
<&topckgen_clk CLK_TOP_TCK_26M_MX9>,
<&topckgen_clk CLK_TOP_SPMI_P_MST_SEL>,
<&topckgen_clk CLK_TOP_TCK_26M_MX9>,
<&topckgen_clk CLK_TOP_MAINPLL_D7_D8>;
clock-names = "pmif_sys_ck",
"pmif_tmr_ck",
"pmif_clk_mux",
"pmif_clk_osc_d10",
"pmif_clk26m",
"spmimst_clk_mux",
"spmimst_clk26m",
"spmimst_clk_mainpll_d7_d8";
swinf_ch_start = <6>;
ap_swinf_no = <2>;
grpid = <0xB>;
#address-cells = <2>;
#size-cells = <0>;
};
/* ATF logger */
atf_logger {
compatible = "mediatek,atf_logger";
};
bcrm_peri_ao@1002a000 {
compatible = "mediatek,bcrm_peri_ao";
reg = <0 0x1002a000 0 0x1000>;
};
debug_ao_peri@1002b000 {
compatible = "mediatek,debug_ao_peri";
reg = <0 0x1002b000 0 0x1000>;
};
bcrm_peri_ao2@1002d000 {
compatible = "mediatek,bcrm_peri_ao2";
reg = <0 0x1002d000 0 0x1000>;
};
debug_ao_peri2@1002e000 {
compatible = "mediatek,debug_ao_peri2";
reg = <0 0x1002e000 0 0x1000>;
};
devapc_ao_infra@10030000 {
compatible = "mediatek,devapc_ao_infra";
reg = <0 0x10030000 0 0x4000>;
};
devapc_ao_peri@10034000 {
compatible = "mediatek,devapc_ao_peri";
reg = <0 0x10034000 0 0x4000>;
};
devapc_ao_peri2@10038000 {
compatible = "mediatek,devapc_ao_peri2";
reg = <0 0x10038000 0 0x4000>;
};
devapc_ao_peri_par@1003c000 {
compatible = "mediatek,devapc_ao_peri_par";
reg = <0 0x1003c000 0 0x4000>;
};
debug_ao_peri_par@10040000 {
compatible = "mediatek,debug_ao_peri_par";
reg = <0 0x10040000 0 0x1000>;
};
bcrm_peri_par_ao@10041000 {
compatible = "mediatek,bcrm_peri_par_ao";
reg = <0 0x10041000 0 0x1000>;
};
debug_ao_fmem@10042000 {
compatible = "mediatek,debug_ao_fmem";
reg = <0 0x10042000 0 0x1000>;
};
bcrm_fmem_ao@10043000 {
compatible = "mediatek,bcrm_fmem_ao";
reg = <0 0x10043000 0 0x1000>;
};
devapc_ao_fmem@10044000 {
compatible = "mediatek,devapc_ao_fmem";
reg = <0 0x10044000 0 0x4000>;
};
pwm@10048000 {
compatible = "mediatek,mt6880-pwm";
reg = <0 0x10048000 0 0x1000>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen_clk CLK_TOP_PWM_SEL>,
<&infracfg_ao_clk CLK_IFRAO_PWM>,
<&infracfg_ao_clk CLK_IFRAO_PWM1>,
<&infracfg_ao_clk CLK_IFRAO_PWM2>,
<&infracfg_ao_clk CLK_IFRAO_PWM3>,
<&infracfg_ao_clk CLK_IFRAO_PWM4>,
<&infracfg_ao_clk CLK_IFRAO_PWM5>,
<&infracfg_ao_clk CLK_IFRAO_PWM6>,
<&infracfg_ao_clk CLK_IFRAO_PWM7>;
clock-names = "top",
"main",
"pwm1",
"pwm2",
"pwm3",
"pwm4",
"pwm5",
"pwm6",
"pwm7";
};
sgmii0@10060000 {
compatible = "mediatek,sgmii0";
reg = <0 0x10060000 0 0x8000>;
interrupts = <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
};
sgmii1@10070000 {
compatible = "mediatek,sgmii1";
reg = <0 0x10070000 0 0x8000>;
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
};
sys_cirq@10204000 {
compatible = "mediatek,sys_cirq";
reg = <0 0x10204000 0 0x1000>;
interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>;
};
devapc@10207000 {
compatible = "mediatek,mt6880-devapc";
reg = <0 0x10207000 0 0x1000>,
<0 0x10274000 0 0x1000>,
<0 0x10275000 0 0x1000>,
<0 0x11020000 0 0x1000>,
<0 0x10030000 0 0x1000>,
<0 0x1020e000 0 0x1000>,
<0 0x10033000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao_clk CLK_IFRAO_DEVICE_APC>;
clock-names = "devapc-infra-clock";
};
hwrng: hwrng {
compatible = "mediatek,mt67xx-rng";
};
bus_dbg@10208000 {
compatible = "mediatek,bus_dbg-v2";
reg = <0 0x10208000 0 0x1000>,
<0 0x10001000 0 0x1000>;
mediatek,bus_dbg_con_offset = <0x2fc>;
interrupt = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
};
ap_ccif0@10209000 {
compatible = "mediatek,ap_ccif0";
reg = <0 0x10209000 0 0x1000>;
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
};
md_ccif0@1020a000 {
compatible = "mediatek,md_ccif0";
reg = <0 0x1020a000 0 0x1000>;
};
ap_ccif1@1020b000 {
compatible = "mediatek,ap_ccif1";
reg = <0 0x1020b000 0 0x1000>;
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
};
md_ccif1@1020c000 {
compatible = "mediatek,md_ccif1";
reg = <0 0x1020c000 0 0x1000>;
};
infra_mbist@1020d000 {
compatible = "mediatek,infra_mbist";
reg = <0 0x1020d000 0 0x1000>;
};
infracfg@1020e000 {
compatible = "mediatek,infracfg";
reg = <0 0x1020e000 0 0x1000>;
};
trng@1020f000 {
compatible = "mediatek,trng";
reg = <0 0x1020f000 0 0x1000>;
interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
};
dxcc_sec@10210000 {
compatible = "mediatek,dxcc_sec";
reg = <0 0x10210000 0 0x1000>;
};
cq_dma@10212000 {
compatible = "mediatek,cq_dma";
reg = <0 0x10212000 0 0x1000>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
};
md2md_md2_ccif0@10213000 {
compatible = "mediatek,md2md_md2_ccif0";
reg = <0 0x10213000 0 0x1000>;
};
sramrom@10214000 {
compatible = "mediatek,sramrom";
reg = <0 0x10214000 0 0x1000>;
};
bcrm_infra@10215000 {
compatible = "mediatek,bcrm_infra";
reg = <0 0x10215000 0 0x1000>;
};
dbg_tracker2@10218000 {
compatible = "mediatek,dbg_tracker2";
reg = <0 0x10218000 0 0x1000>;
};
emicen: emicen@10219000 {
compatible = "mediatek,mt6880-emicen",
"mediatek,common-emicen";
reg = <0 0x10219000 0 0x1000>;
mediatek,emi-reg = <&emichn>;
};
infra_device_mpu@1021a000 {
compatible = "mediatek,infra_device_mpu";
reg = <0 0x1021a000 0 0x1000>;
};
infra_device_mpu@1021b000 {
compatible = "mediatek,infra_device_mpu";
reg = <0 0x1021b000 0 0x1000>;
};
infracfg_mem@1021c000 {
compatible = "mediatek,infracfg_mem";
reg = <0 0x1021c000 0 0x1000>;
};
emimpu:emimpu@10226000 {
compatible = "mediatek,mt6880-emimpu",
"mediatek,common-emimpu";
reg = <0 0x10226000 0 0x1000>;
mediatek,emi-reg = <&emicen>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
region_cnt = <32>;
domain_cnt = <16>;
addr_align = <16>;
ap_region = <31>;
ap_apc = <0 0 5 5 0 0 6 0>,
<0 0 5 5 5 5 5 5>;
dump = <0x1f0 0x1f8 0x1fc>;
clear = <0x160 0xffffffff 16>,
<0x200 0x00000003 16>,
<0x1f0 0x80000000 1>;
clear_md = <0x1fc 0x80000000 1>;
ctrl_intf = <1>;
slverr = <0>;
};
cldma_sys_ap {
compatible = "mediatek,cldma_sys_ap";
reg = <0 0x1004A000 0 0x1000>, /*CLDMA0_AO_INDMA_AO_MD*/
<0 0x1021E000 0 0x1000>; /*CLDMA0_AO_INDMA_PD_MD*/
interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; /*cldma0_md_int_ap*/
clocks = <&infracfg_ao_clk CLK_IFRAO_RG_133M_CLDMA_TOP>;
clock-names = "infra-cldma0-rh";
mediatek,hif_ids = <1>; /* (1 << HIF_ID_CLDMA) */
};
mrdump_ext_rst: mrdump_ext_rst {
compatible = "mediatek, mrdump_ext_rst-disabled";
mode = "IRQ";
status = "okay";
};
dpmaif:dpmaif@10014000 {
compatible = "mediatek,dpmaif";
reg = <0 0x10014000 0 0x1000>, /*AO_UL*/
<0 0x1022D000 0 0x1000>, /*PD_UL*/
<0 0x1022C000 0 0x1000>, /*PD_MD_MISC*/
<0 0x1022E000 0 0x1000>, /*SRAM*/
<0 0x15B14000 0 0x1000>, /*MED_BMP_CFG*/
<0 0x15B38000 0 0x1000>; /*MED_SSR1_CFG*/
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; /*209+32=241*/
mediatek,dpmaif_capability = <6>;
clocks = <&infracfg_ao_clk CLK_IFRAO_DPMAIF_MAIN>,
<&infracfg_ao_clk CLK_IFRAO_CLDMA_BCLK>;
clock-names = "infra-dpmaif-clk",
"infra-dpmaif-blk-clk";
};
mddriver:mddriver {
compatible = "mediatek,mddriver";
mediatek,mdhif_type = <2>; /* bit0~3: CLDMA|CCIF|DPMAIF */
mediatek,md_id = <0>;
mediatek,cldma_capability = <2>;
reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/
<0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /*CCIF0 174/206*/
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /*CCIF0 175/207*/
<GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; /*MDWDT*/
clocks = <&infracfg_ao_clk CLK_IFRAO_CCIF_AP>,
<&infracfg_ao_clk CLK_IFRAO_CCIF_MD>,
<&infracfg_ao_clk CLK_IFRAO_CCIF1_AP>,
<&infracfg_ao_clk CLK_IFRAO_CCIF1_MD>,
<&infracfg_ao_clk CLK_IFRAO_CCIF2_AP>,
<&infracfg_ao_clk CLK_IFRAO_CCIF2_MD>,
<&infracfg_ao_clk CLK_IFRAO_CCIF4_MD>;
clock-names = "infra-ccif-ap",
"infra-ccif-md",
"infra-ccif1-ap",
"infra-ccif1-md",
"infra-ccif2-ap",
"infra-ccif2-md",
"infra-ccif4-md";
power-domains = <&scpsys MT6890_POWER_DOMAIN_MD1>;
};
/* md_auxadc:md_auxadc {
compatible = "mediatek,md_auxadc";
io-channels = <&auxadc 2>;
io-channel-names = "md-channel",
"md-battery";
};
md_ccci_rtc:md_ccci_rtc {
compatible = "mediatek,md_ccci_rtc";
nvmem-cells = <&ext_32k>;
nvmem-cell-names = "external-32k";
}; */
gce_mbox: gce_mbox@10228000 {
compatible = "mediatek,mailbox-gce";
reg = <0 0x10228000 0 0x4000>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <3>;
#gce-event-cells = <1>;
#gce-subsys-cells = <2>;
default_tokens = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_0>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_1>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_2>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_3>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>,
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT0>,
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT1>;
clocks = <&infracfg_ao_clk CLK_IFRAO_GCE>,
<&infracfg_ao_clk CLK_IFRAO_GCE_26M_SET>;
clock-names = "gce", "gce-timer";
};
cmdq-test {
compatible = "mediatek,cmdq-test";
mediatek,gce = <&gce_mbox>;
mmsys_config = <&mmsys_config>;
mediatek,gce-subsys = <99>, <SUBSYS_1400XXXX>;
mboxes = <&gce_mbox 23 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 22 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>,
<&gce_mbox 11 0 CMDQ_THR_PRIO_1>;
token_user0 = /bits/ 16 <CMDQ_SYNC_TOKEN_USER_0>;
token_gpr_set4 = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>;
};
infra_dpmaif@1022c000 {
compatible = "mediatek,infra_dpmaif";
reg = <0 0x1022c000 0 0x10>;
};
dramc: dramc@10230000 {
compatible = "mediatek,mt6880-dramc",
"mediatek,common-dramc";
reg = <0 0x10230000 0 0x2000>, /* DRAMC AO CHA */
<0 0x10240000 0 0x2000>, /* DRAMC AO CHB */
<0 0x10234000 0 0x1000>, /* DRAMC NAO CHA */
<0 0x10244000 0 0x1000>, /* DRAMC NAO CHB */
<0 0x10238000 0 0x2000>, /* DDRPHY AO CHA */
<0 0x10248000 0 0x2000>, /* DDRPHY AO CHB */
<0 0x10236000 0 0x1000>, /* DDRPHY NAO CHA */
<0 0x10246000 0 0x1000>, /* DDRPHY NAO CHB */
<0 0x10006000 0 0x1000>; /* SLEEP BASE */
mr4_version = <1>;
mr4_rg = <0x0090 0x0000ffff 0>;
fmeter_version = <1>;
crystal_freq = <52>;
pll_id = <0x050c 0x00000100 8>;
shu_lv = <0x050c 0x00030000 16>;
shu_of = <0x700>;
sdmpcw = <0x0704 0xffff0000 16>,
<0x0724 0xffff0000 16>;
prediv = <0x0708 0x000c0000 18>,
<0x0728 0x000c0000 18>;
posdiv = <0x0708 0x00000007 0>,
<0x0728 0x00000007 0>;
ckdiv4 = <0x0874 0x00000004 2>,
<0x0874 0x00000004 2>;
pll_md = <0x0744 0x00000100 8>,
<0x0744 0x00000100 8>;
cldiv2 = <0x08b4 0x00000002 1>,
<0x08b4 0x00000002 1>;
fbksel = <0x070c 0x00000040 6>,
<0x070c 0x00000040 6>;
dqopen = <0x0870 0x00100000 20>,
<0x0870 0x00100000 20>;
};
emiisu: emiisu {
compatible = "mediatek,mt6880-emiisu",
"mediatek,common-emiisu";
ctrl_intf = <1>;
};
emichn: emichn@10235000 {
compatible = "mediatek,mt6880-emichn",
"mediatek,common-emichn";
reg = <0 0x10235000 0 0x1000>,
<0 0x10245000 0 0x1000>;
};
dramc_ch0_top0@10230000 {
compatible = "mediatek,dramc_ch0_top0";
reg = <0 0x10230000 0 0x2000>;
};
dramc_ch0_top1@10232000 {
compatible = "mediatek,dramc_ch0_top1";
reg = <0 0x10232000 0 0x2000>;
};
dramc_ch0_top2@10234000 {
compatible = "mediatek,dramc_ch0_top2";
reg = <0 0x10234000 0 0x1000>;
};
dramc_ch0_top3@10235000 {
compatible = "mediatek,dramc_ch0_top3";
reg = <0 0x10235000 0 0x1000>;
};
dramc_ch0_top4@10236000 {
compatible = "mediatek,dramc_ch0_top4";
reg = <0 0x10236000 0 0x2000>;
};
dramc_ch0_top5@10238000 {
compatible = "mediatek,dramc_ch0_top5";
reg = <0 0x10238000 0 0x2000>;
};
dramc_ch0_top6@1023a000 {
compatible = "mediatek,dramc_ch0_top6";
reg = <0 0x1023a000 0 0x2000>;
};
ap_ccif2@1023c000 {
compatible = "mediatek,ap_ccif2";
reg = <0 0x1023c000 0 0x1000>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
};
md_ccif2@1023d000 {
compatible = "mediatek,md_ccif2";
reg = <0 0x1023d000 0 0x1000>;
};
ap_ccif3@1023e000 {
compatible = "mediatek,ap_ccif3";
reg = <0 0x1023e000 0 0x1000>;
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
};
md_ccif3@1023f000 {
compatible = "mediatek,md_ccif3";
reg = <0 0x1023f000 0 0x1000>;
};
i2c_common: i2c_common {
compatible = "mediatek,i2c_common";
dma_support = /bits/ 8 <3>;
idvfs = /bits/ 8 <1>;
set_dt_div = /bits/ 8 <1>;
check_max_freq = /bits/ 8 <1>;
ver = /bits/ 8 <2>;
set_ltiming = /bits/ 8 <1>;
ext_time_config = /bits/ 16 <0x1801>;
cnt_constraint = /bits/ 8 <1>;
dma_ver = /bits/ 8 <1>;
};
i2c0: i2c0@11c40000 {
compatible = "mediatek,i2c";
id = <0>;
reg = <0 0x11c40000 0 0x1000>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C0_RO>,
<&infracfg_ao_clk CLK_IFRAO_I2C3>;
clock-names = "main", "dma";
clock-div = <5>;
aed = <0x1a>;
};
i2c1: i2c1@11c41000 {
compatible = "mediatek,i2c";
id = <1>;
reg = <0 0x11c41000 0 0x1000>,
<0 0x10217100 0 0x80>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C1_RO>,
<&infracfg_ao_clk CLK_IFRAO_I2C3>;
clock-names = "main", "dma";
clock-div = <5>;
aed = <0x1a>;
};
i2c2: i2c2@11c42000 {
compatible = "mediatek,i2c";
id = <2>;
reg = <0 0x11c42000 0 0x1000>,
<0 0x10217180 0 0x80>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C2_RO>,
<&infracfg_ao_clk CLK_IFRAO_I2C3>;
clock-names = "main", "dma";
clock-div = <5>;
aed = <0x1a>;
};
i2c3: i2c3@11c43000 {
compatible = "mediatek,i2c";
id = <3>;
reg = <0 0x11c43000 0 0x1000>,
<0 0x10217200 0 0x80>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C3_RO>,
<&infracfg_ao_clk CLK_IFRAO_I2C3>;
clock-names = "main", "dma";
clock-div = <5>;
aed = <0x1a>;
};
i2c4: i2c4@11c44000 {
compatible = "mediatek,i2c";
id = <4>;
reg = <0 0x11c44000 0 0x1000>,
<0 0x10217280 0 0x80>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C4_RO>,
<&infracfg_ao_clk CLK_IFRAO_I2C3>;
clock-names = "main", "dma";
clock-div = <5>;
aed = <0x1a>;
};
i2c5: i2c5@11c45000 {
compatible = "mediatek,i2c";
id = <5>;
reg = <0 0x11c45000 0 0x1000>,
<0 0x10217300 0 0x80>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C5_RO>,
<&infracfg_ao_clk CLK_IFRAO_I2C3>;
clock-names = "main", "dma";
clock-div = <5>;
aed = <0x1a>;
};
ssusb: usb@11201000 {
compatible = "mediatek,mtu3";
reg = <0 0x11201000 0 0x2e00>,
<0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
vusb33-supply = <&mt6330_vusb_ldo_reg>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
phy-cells = <1>;
phys = <&u2port0 PHY_TYPE_USB2>,
<&u3port0 PHY_TYPE_USB3>;
plat_type = <1>; /* 0: FPGA 1: ASIC */
dr_mode = "peripheral";
maximum-speed = "super-speed";
clocks = <&infracfg_ao_clk CLK_IFRAO_SSUSB>,
<&infracfg_ao_clk CLK_IFRAO_SSUSB_XHCI>;
clock-names = "sys_ck","ref_ck";
power-domains = <&scpsys MT6890_POWER_DOMAIN_SSUSB>;
usb-role-switch;
mediatek,force-vbus;
mediatek,usb3-drd;
#address-cells = <2>;
#size-cells = <2>;
ranges;
usb_host: xhci0@11200000 {
compatible = "mediatek,mtk-xhci";
reg = <0 0x11200000 0 0x1000>;
reg-names = "mac";
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk26m>;
clock-names = "sys_ck";
};
};
u3fpgaphy: usb-phy {
compatible = "mediatek,fpga-u3phy";
mediatek,ippc = <0x11203e00>;
#address-cells = <2>;
#size-cells = <2>;
fpga_i2c_physical_base = <0x11c42000>;
status = "disabled";
u3fpgaport0: usb-phy@0 {
chip-id= <0xa60931a>;
port = <0>;
pclk_phase = <23>;
#phy-cells = <1>;
};
};
u3phy: usb-phy@11e30000 {
compatible = "mediatek,generic-tphy-v2";
clocks = <&clk26m>;
clock-names = "u3phya_ref";
#address-cells = <2>;
#size-cells = <2>;
ranges;
u2port0: usb2-phy0@11e30000 {
reg = <0 0x11e30000 0 0x700>;
#phy-cells = <1>;
mediatek,eye-rev6 = <1>;
mediatek,eye-vrt = <5>;
mediatek,eye-term = <5>;
mediatek,rx-sqth = <5>;
status = "okay";
};
u3port0: usb3-phy0@11e30700 {
reg = <0 0x11e30700 0 0x900>;
#phy-cells = <1>;
status = "okay";
};
};
apdma: dma-controller@0x10217000 {
compatible = "mediatek, mt6873-uart-dma",
"mediatek,mt6577-uart-dma";
reg = <0 0x10217380 0 0x80>,
<0 0x10217400 0 0x80>,
<0 0x10217480 0 0x80>,
<0 0x10217500 0 0x80>,
<0 0x10217580 0 0x80>,
<0 0x10217600 0 0x80>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
dma-requests = <6>;
dma-bits = <34>;
clocks = <&clk26m>;
#dma-cells = <1>;
};
auxadc: auxadc@11001000 {
compatible = "mediatek,mt6765-auxadc";
reg = <0 0x11001000 0 0x1000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>;
clocks = <&infracfg_ao_clk CLK_IFRAO_AUXADC>;
clock-names = "main";
#io-channel-cells = <1>;
/* Auxadc efuse calibration */
/* 1. Auxadc cali on/off bit shift */
mediatek,cali-en-bit = <20>;
/* 2. Auxadc cali ge bits shift */
mediatek,cali-ge-bit = <10>;
/* 3. Auxadc cali oe bits shift */
mediatek,cali-oe-bit = <0>;
/* 4. Auxadc cali efuse reg offset */
mediatek,cali-efuse-reg-offset = <0xf8>;
nvmem = <&efuse>;
nvmem-names = "mtk_efuse";
#interconnect-cells = <1>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt6873-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk26m>, <&infracfg_ao_clk CLK_IFRAO_UART0>;
clock-names = "baud", "bus";
dmas = <&apdma 0
&apdma 1>;
dma-names = "tx", "rx";
};
uart1: serial@11003000 {
compatible = "mediatek,mt6873-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk26m>, <&infracfg_ao_clk CLK_IFRAO_UART1>;
clock-names = "baud", "bus";
dmas = <&apdma 2
&apdma 3>;
dma-names = "tx", "rx";
};
uart2: serial@11004000 {
compatible = "mediatek,mt6873-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x1000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk26m>, <&infracfg_ao_clk CLK_IFRAO_UART2>;
clock-names = "baud", "bus";
dmas = <&apdma 4
&apdma 5>;
dma-names = "tx", "rx";
};
nandc: nfi@11005000 {
compatible = "mediatek,mt6880-nfc";
reg = <0 0x11005000 0 0x1000>,
<0 0x11006000 0 0x1000>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
status = "ok";
};
nor: nor_flash@0x11250000 {
compatible = "mediatek,mt8173-nor";
reg = <0 0x11250000 0 0x1000>;
clocks =<&topckgen_clk CLK_TOP_SFLASH_SEL>,
<&infracfg_ao_clk CLK_IFRAO_RG_FLASHIF_SFLASH>;
clock-names = "spi", "sf";
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
};
pd-sgmii_0_phy {
compatible = "mediatek,sgmii-bring-up";
power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_0_PHY>;
};
pd-sgmii_0_top {
compatible = "mediatek,sgmii-bring-up";
power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_0_TOP>;
};
pd-sgmii_1_phy {
compatible = "mediatek,sgmii-bring-up";
power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_1_PHY>;
};
pd-sgmii_1_top {
compatible = "mediatek,sgmii-bring-up";
power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_1_TOP>;
};
sgmiisys_0: sgmiisys@10060000 {
compatible = "mediatek,colgin-sgmiisys_0", "syscon";
reg = <0 0x10060000 0 0x1000>;
#clock-cells = <1>;
mediatek,physpeed = "2500";
/*modify by CLK SW Pei-hsuan Cheng */
power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_0_TOP>;
};
sgmiisys_1: sgmiisys@10070000 {
compatible = "mediatek,colgin-sgmiisys_1", "syscon";
reg = <0 0x10070000 0 0x1000>;
#clock-cells = <1>;
mediatek,physpeed = "2500";
/*modify by CLK SW Pei-hsuan Cheng */
power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_1_TOP>;
};
sgmiisys_phy_0: sgmiiphy@11ED0000 {
compatible = "mediatek,colgin-sgmiisys_phy_0", "syscon";
reg = <0 0x11ED0000 0 0x1000>;
#clock-cells = <1>;
/*modify by CLK SW Pei-hsuan Cheng */
power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_0_PHY>;
};
sgmiisys_phy_1: sgmiiphy@11EE0000 {
compatible = "mediatek,colgin-sgmiisys_phy_1", "syscon";
reg = <0 0x11EE0000 0 0x1000>;
#clock-cells = <1>;
/*modify by CLK SW Pei-hsuan Cheng */
power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_1_PHY>;
};
ethsys: ethsys@15000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mediatek,leopard-ethsys", "syscon", "simple-mfd";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
ethsysrst: reset-controller {
compatible = "ti,syscon-reset";
#reset-cells = <1>;
ti,reset-bits = <
0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET) /* 4: wocpu_rst */
>;
};
};
wo: wo@15195000 {
compatible = "mediatek,leopard-ethsys", "syscon", "simple-mfd";
reg = <0 0x15195000 0 0x1000>;
};
eth: ethernet@15100000 {
compatible = "mediatek,mt6890-eth",
"syscon";
reg = <0 0x15100000 0 0x20000>;
interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen_clk CLK_TOP_NETSYS_SEL>,
<&topckgen_clk CLK_TOP_MEDSYS_SEL>,
<&topckgen_clk CLK_TOP_NETSYS_500M_SEL>,
<&topckgen_clk CLK_TOP_NETSYS_MED_MCU_SEL>,
<&topckgen_clk CLK_TOP_NETSYS_WED_MCU_SEL>,
<&topckgen_clk CLK_TOP_NETSYS_2X_SEL>,
<&topckgen_clk CLK_TOP_SGMII_SEL>,
<&topckgen_clk CLK_TOP_SGMII_SBUS_SEL>;
clock-names = "net_sel", "med_sel", "net_500_sel",
"med_mcu_sel", "wed_mcu_sel",
"net_2x_sel", "sgmii_sel", "sgmii_sbus_sel";
/*modify by CLK SW Pei-hsuan Cheng
power-domains = <&scpsys MT6890_POWER_DOMAIN_NETSYS>;*/
mediatek,ethsys = <&ethsys>;
mediatek,wo = <&wo>;
mediatek,sgmiisys = <&sgmiisys_0>,<&sgmiisys_1>;
mediatek,sgmiisys_phy = <&sgmiisys_phy_0>,<&sgmiisys_phy_1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <0x7>;
snps,rd_osr_lmt = <0x7>;
snps,blen = <0 0 0 0 16 8 4>;
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,priority = <0x0>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,priority = <0x0>;
snps,route-ptp;
};
queue2 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,priority = <0x0>;
snps,route-multi-broad;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <3>;
snps,tx-sched-wrr;
queue0 {
snps,weight = <0x10>;
snps,dcb-algorithm;
snps,priority = <0x0>;
};
queue1 {
snps,weight = <0x11>;
snps,dcb-algorithm;
snps,priority = <0x1>;
};
queue2 {
snps,weight = <0x12>;
snps,dcb-algorithm;
snps,priority = <0x2>;
};
};
snps_mac: ethernet@11021000 {
compatible = "mediatek,mt2735-gmac";
reg = <0 0x11021000 0 0x1300>;
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
mac-address = [00 55 7b b5 7d f7];
clock-names = "mac_main",
"ptp_ref",
"eth_cg",
"eth_rmii",
"sgmii_sel",
"sgmii_sbus_sel";
clocks = <&topckgen_clk CLK_TOP_SNPS_ETH_312P5M_SEL>,
<&topckgen_clk CLK_TOP_SNPS_ETH_62P4M_PTP_SEL>,
<&topckgen_clk CLK_TOP_SNPS_ETH_250M_SEL>,
<&topckgen_clk CLK_TOP_SNPS_ETH_50M_RMII_SEL>,
<&topckgen_clk CLK_TOP_SGMII_SEL>,
<&topckgen_clk CLK_TOP_SGMII_SBUS_SEL>;
mediatek,pericfg = <&infracfg_ao>;
snps,axi-config = <&stmmac_axi_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
/*modify by CLK SW Pei-hsuan Cheng */
power-domains = <&scpsys MT6890_POWER_DOMAIN_ETH>;
mediatek,sgmiisys = <&sgmiisys_0>;
mediatek,sgmiisys_phy = <&sgmiisys_phy_0>;
snps,txpbl = <1>;
snps,rxpbl = <1>;
clk_csr = <0>;
status = "disabled";
};
crypto: crypto@10320000 {
/* compatible = "mediatek,eip97-crypto"; */
/* compatible = "safexcel-ip-97-mob"; */
compatible = "inside-secure,safexcel-eip97";
reg = <0 0x10320000 0 0x40000>;
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ring0", "ring1", "ring2", "ring3";
clocks = <&topckgen_clk CLK_TOP_EIP97_SEL>,
<&topckgen_clk CLK_TOP_NET2PLL>,
<&topckgen_clk CLK_TOP_MAINPLL_D5_D2>;
clock-names = "clk-mux", "net2pll", "D5_D2";
power-domains = <&scpsys MT6890_POWER_DOMAIN_EIP97>;
};
dramc_ch1_top0@10240000 {
compatible = "mediatek,dramc_ch1_top0";
reg = <0 0x10240000 0 0x2000>;
};
dramc_ch1_top1@10242000 {
compatible = "mediatek,dramc_ch1_top1";
reg = <0 0x10242000 0 0x2000>;
};
dramc_ch1_top2@10244000 {
compatible = "mediatek,dramc_ch1_top2";
reg = <0 0x10244000 0 0x1000>;
};
dramc_ch1_top3@10245000 {
compatible = "mediatek,dramc_ch1_top3";
reg = <0 0x10245000 0 0x1000>;
};
dramc_ch1_top4@10246000 {
compatible = "mediatek,dramc_ch1_top4";
reg = <0 0x10246000 0 0x2000>;
};
dramc_ch1_top5@10248000 {
compatible = "mediatek,dramc_ch1_top5";
reg = <0 0x10248000 0 0x2000>;
};
dramc_ch1_top6@1024a000 {
compatible = "mediatek,dramc_ch1_top6";
reg = <0 0x1024a000 0 0x2000>;
};
ap_ccif4@1024c000 {
compatible = "mediatek,ap_ccif4";
reg = <0 0x1024c000 0 0x1000>;
};
md_ccif4@1024d000 {
compatible = "mediatek,md_ccif4";
reg = <0 0x1024d000 0 0x1000>;
};
md_ccif4@1024e000 {
compatible = "mediatek,md_ccif4";
reg = <0 0x1024e000 0 0x1000>;
};
dramc_ch2_top0@10250000 {
compatible = "mediatek,dramc_ch2_top0";
reg = <0 0x10250000 0 0x2000>;
};
dramc_ch2_top1@10252000 {
compatible = "mediatek,dramc_ch2_top1";
reg = <0 0x10252000 0 0x2000>;
};
dramc_ch2_top2@10254000 {
compatible = "mediatek,dramc_ch2_top2";
reg = <0 0x10254000 0 0x1000>;
};
dramc_ch2_top3@10255000 {
compatible = "mediatek,dramc_ch2_top3";
reg = <0 0x10255000 0 0x1000>;
};
dramc_ch2_top4@10256000 {
compatible = "mediatek,dramc_ch2_top4";
reg = <0 0x10256000 0 0x2000>;
};
dramc_ch2_top5@10258000 {
compatible = "mediatek,dramc_ch2_top5";
reg = <0 0x10258000 0 0x2000>;
};
dramc_ch2_top6@1025a000 {
compatible = "mediatek,dramc_ch2_top6";
reg = <0 0x1025a000 0 0x2000>;
};
ap_ccif5@1025c000 {
compatible = "mediatek,ap_ccif5";
reg = <0 0x1025c000 0 0x1000>;
};
md_ccif5@1025d000 {
compatible = "mediatek,md_ccif5";
reg = <0 0x1025d000 0 0x1000>;
};
mm_vpu_m0_sub_common@1025e000 {
compatible = "mediatek,mm_vpu_m0_sub_common";
reg = <0 0x1025e000 0 0x1000>;
};
mm_vpu_m1_sub_common@1025f000 {
compatible = "mediatek,mm_vpu_m1_sub_common";
reg = <0 0x1025f000 0 0x1000>;
};
dramc_ch3_top0@10260000 {
compatible = "mediatek,dramc_ch3_top0";
reg = <0 0x10260000 0 0x2000>;
};
dramc_ch3_top1@10262000 {
compatible = "mediatek,dramc_ch3_top1";
reg = <0 0x10262000 0 0x2000>;
};
dramc_ch3_top2@10264000 {
compatible = "mediatek,dramc_ch3_top2";
reg = <0 0x10264000 0 0x1000>;
};
dramc_ch3_top3@10265000 {
compatible = "mediatek,dramc_ch3_top3";
reg = <0 0x10265000 0 0x1000>;
};
dramc_ch3_top4@10266000 {
compatible = "mediatek,dramc_ch3_top4";
reg = <0 0x10266000 0 0x2000>;
};
dramc_ch3_top5@10268000 {
compatible = "mediatek,dramc_ch3_top5";
reg = <0 0x10268000 0 0x2000>;
};
dramc_ch3_top6@1026a000 {
compatible = "mediatek,dramc_ch3_top6";
reg = <0 0x1026a000 0 0x2000>;
};
bcrm_peri@10272000 {
compatible = "mediatek,bcrm_peri";
reg = <0 0x10272000 0 0x1000>;
};
bcrm_peri2@10273000 {
compatible = "mediatek,bcrm_peri2";
reg = <0 0x10273000 0 0x1000>;
};
devapc_peri@10274000 {
compatible = "mediatek,devapc_peri";
reg = <0 0x10274000 0 0x1000>;
};
devapc_peri2@10275000 {
compatible = "mediatek,devapc_peri2";
reg = <0 0x10275000 0 0x1000>;
};
bcrm_fmem@10276000 {
compatible = "mediatek,bcrm_fmem";
reg = <0 0x10276000 0 0x1000>;
};
mm_vpu_m0_sub_common@10309000 {
compatible = "mediatek,mm_vpu_m0_sub_common";
reg = <0 0x10309000 0 0x1000>;
};
mm_vpu_m1_sub_common@1030a000 {
compatible = "mediatek,mm_vpu_m1_sub_common";
reg = <0 0x1030a000 0 0x1000>;
};
mm_vpu_m1_sub_common@1030b000 {
compatible = "mediatek,mm_vpu_m1_sub_common";
reg = <0 0x1030b000 0 0x1000>;
};
mm_vpu_m1_sub_common@1030c000 {
compatible = "mediatek,mm_vpu_m1_sub_common";
reg = <0 0x1030c000 0 0x1000>;
};
mm_vpu_m1_sub_common@1030d000 {
compatible = "mediatek,mm_vpu_m1_sub_common";
reg = <0 0x1030d000 0 0x1000>;
};
sys_cirq1@10312000 {
compatible = "mediatek,sys_cirq1";
reg = <0 0x10312000 0 0x1000>;
};
sys_cirq2@10313000 {
compatible = "mediatek,sys_cirq2";
reg = <0 0x10313000 0 0x1000>;
};
dbg_tracker@10314000 {
compatible = "mediatek,dbg_tracker";
reg = <0 0x10314000 0 0x1000>;
};
pwrmcu@10400000 {
compatible = "mediatek,pwrmcu";
reg = <0 0x10400000 0 0x100000>;
};
sspm@10400000 {
compatible = "mediatek,sspm";
reg = <0 0x10400000 0 0x28000>,
<0 0x10440000 0 0x10000>,
<0 0x10450000 0 0x100>,
<0 0x10451000 0 0x4>,
<0 0x10451004 0 0x4>,
<0 0x10460000 0 0x100>,
<0 0x10461000 0 0x4>,
<0 0x10461004 0 0x4>,
<0 0x10470000 0 0x100>,
<0 0x10471000 0 0x4>,
<0 0x10471004 0 0x4>,
<0 0x10480000 0 0x100>,
<0 0x10481000 0 0x4>,
<0 0x10481004 0 0x4>,
<0 0x10490000 0 0x100>,
<0 0x10491000 0 0x4>,
<0 0x10491004 0 0x4>;
reg-names = "sspm_base",
"cfgreg",
"mbox0_base",
"mbox0_set",
"mbox0_clr",
"mbox1_base",
"mbox1_set",
"mbox1_clr",
"mbox2_base",
"mbox2_set",
"mbox2_clr",
"mbox3_base",
"mbox3_set",
"mbox3_clr",
"mbox4_base",
"mbox4_set",
"mbox4_clr";
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ipc",
"mbox0",
"mbox1",
"mbox2",
"mbox3",
"mbox4";
};
tinsys@10500000 {
compatible = "mediatek,tinsys";
reg = <0 0x10500000 0 0x0>;
};
dramc_ch1_rsv0@10900000 {
compatible = "mediatek,dramc_ch1_rsv0";
reg = <0 0x10900000 0 0x40000>;
};
dramc_ch1_rsv1@10940000 {
compatible = "mediatek,dramc_ch1_rsv1";
reg = <0 0x10940000 0 0xc0000>;
};
mali: mali@13000000 {
compatible = "mediatek,mali", "arm,mali-midgard", "arm,mali-bifrost";
reg = <0 0x13000000 0 0x4000>;
interrupts =
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names =
"GPU",
"MMU",
"JOB",
"EVENT";
operating-points-v2 = <&gpu_mali_opp>;
#cooling-cells = <2>;
gpufreq-supply = <&gpufreq>;
};
gpu_mali_opp: opp-table0 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <780000000>;
opp-microvolt = <750000>;
};
opp01 {
opp-hz = /bits/ 64 <570000000>;
opp-microvolt = <650000>;
};
opp02 {
opp-hz = /bits/ 64 <360000000>;
opp-microvolt = <600000>;
};
opp03 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <550000>;
};
};
gpufreq: gpufreq {
compatible = "mediatek,gpufreq";
clocks =
<&topckgen_clk CLK_TOP_MFG_SEL>,
<&topckgen_clk CLK_TOP_MFGPLL>,
<&topckgen_clk CLK_TOP_MFG_REF_SEL>,
<&mfgsys_clk CLK_MFGCFG_BG3D>;
clock-names =
"clk_mux", /* switch main/sub */
"clk_main_parent", /* main pll freq */
"clk_sub_parent", /* default 218.4 MHz */
"cg_bg3d";
/* power-domains = <&scpsys MT6890_POWER_DOMAIN_MFG0>; */
status = "disabled";
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt6880-mmc";
reg = <0 0x11230000 0 0x1000>,
<0 0x11f10000 0 0x1000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen_clk CLK_TOP_MSDC50_0_SEL>,
<&infracfg_ao_clk CLK_IFRAO_MSDC0>,
<&infracfg_ao_clk CLK_IFRAO_MSDC0_SRC_CLK>;
clock-names = "source", "hclk", "source_cg";
power-domains = <&scpsys MT6890_POWER_DOMAIN_MSDC>;
status = "disabled";
};
mmc1: mmc@11240000 {
compatible = "mediatek,mt6880-mmc";
reg = <0 0x11240000 0 0x1000>,
<0 0x11f20000 0 0x1000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen_clk CLK_TOP_MSDC30_1_SEL>,
<&infracfg_ao_clk CLK_IFRAO_MSDC1>,
<&infracfg_ao_clk CLK_IFRAO_MSDC1_SRC_CLK>;
clock-names = "source", "hclk", "source_cg";
power-domains = <&scpsys MT6890_POWER_DOMAIN_MSDC>;
status = "disabled";
};
lvts: lvts@1100b000 {
compatible = "mediatek,mt6880-lvts";
reg = <0 0x1100b000 0 0x1000>,
<0 0x11278000 0 0x1000>,
<0 0x10001000 0 0x1000>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao_clk CLK_IFRAO_THERM>;
clock-names = "lvts_clk";
resets = <&infracfg_rst 0>,
<&infracfg_rst 1>;
nvmem-cells = <&lvts_e_data1>;
nvmem-cell-names = "e_data1";
#thermal-sensor-cells = <1>;
};
disp_pwm: disp_pwm0@1100e000 {
compatible = "mediatek,disp_pwm0",
"mediatek,mt6890-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <2>;
clocks = <&infracfg_ao CLK_IFRAO_DISP_PWM>,
<&topckgen CLK_TOP_DISP_PWM_SEL>;
clock-names = "main", "mm";
};
pcie0: pcie@11280000 {
compatible = "mediatek,mt2735-pcie";
reg = <0 0x11280000 0 0x2000>;
reg-names = "pcie-mac";
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x00000000
0x0 0x30000000 0 0x10000000>;
status = "disabled";
clocks = <&infracfg_ao_clk CLK_IFRAO_PCIE_TL_26M>,
<&infracfg_ao_clk CLK_IFRAO_PCIE_TL_96M>,
<&infracfg_ao_clk CLK_IFRAO_PCIE_TL_32K>,
<&infracfg_ao_clk CLK_IFRAO_PCIE_PERI_26M>,
<&infracfg_ao_clk CLK_IFRAO_RG_133M_PCIE_P0>;
phys = <&pciephy0>;
phy-names = "pcie-phy";
power-domains = <&scpsys MT6890_POWER_DOMAIN_PEXTP_D_2LX1>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
pcie_intc0: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pciephy0: phy0@11e40000 {
compatible = "mediatek,mt2735-pcie-phy";
#address-cells = <2>;
#size-cells = <2>;
#phy-cells = <0>;
reg = <0 0x11e40000 0 0x10000>,
<0 0x11e50000 0 0x10000>;
reg-names = "phy-sif", "phy-ckm";
nvmem = <&efuse>;
nvmem-names = "mtk_efuse";
nvmem-cells = <&efuse_segment>;
nvmem-cell-names = "efuse_segment_cell";
power-domains = <&scpsys MT6890_POWER_DOMAIN_PEXTP_D_2LX1_PHY>;
};
efuse: efuse@11ec0000 {
compatible = "mediatek,devinfo";
reg = <0 0x11ec0000 0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
efuse_segment: segment@78 {
reg = <0x78 0x4>;
};
lvts_e_data1: data1 {
reg = <0x1E0 0x24>;
};
};
dfd@13e00000 {
compatible = "mediatek,dfd";
reg = <0 0x13e00000 0 0x40000>;
};
g3d_dvfs@13fbc000 {
compatible = "mediatek,g3d_dvfs";
reg = <0 0x13fbc000 0 0x1000>;
};
g3d_testbench@13fbd000 {
compatible = "mediatek,g3d_testbench";
reg = <0 0x13fbd000 0 0x1000>;
};
g3d_config@13fbf000 {
compatible = "mediatek,g3d_config";
reg = <0 0x13fbf000 0 0x1000>;
};
mmsys_config: mmsys_config@14000000 {
compatible = "mediatek,mmsys_config";
reg = <0 0x14000000 0 0x1000>;
};
disp_mutex0@14001000 {
compatible = "mediatek,disp_mutex0";
reg = <0 0x14001000 0 0x1000>;
};
mdp_rdma0@14002000 {
compatible = "mediatek,mdp_rdma0";
reg = <0 0x14002000 0 0x1000>;
};
mdp_rsz0@14003000 {
compatible = "mediatek,mdp_rsz0";
reg = <0 0x14003000 0 0x1000>;
};
mdp_wrot0@14004000 {
compatible = "mediatek,mdp_wrot0";
reg = <0 0x14004000 0 0x1000>;
};
mdp_tdshp0@14005000 {
compatible = "mediatek,mdp_tdshp0";
reg = <0 0x14005000 0 0x1000>;
};
disp_ovl0@14006000 {
compatible = "mediatek,disp_ovl0";
reg = <0 0x14006000 0 0x1000>;
};
disp_rdma0@14007000 {
compatible = "mediatek,disp_rdma0";
reg = <0 0x14007000 0 0x1000>;
};
disp_color0@14008000 {
compatible = "mediatek,disp_color0";
reg = <0 0x14008000 0 0x1000>;
};
disp_ccorr0@14009000 {
compatible = "mediatek,disp_ccorr0";
reg = <0 0x14009000 0 0x1000>;
};
disp_aal0@1400a000 {
compatible = "mediatek,disp_aal0";
reg = <0 0x1400a000 0 0x1000>;
};
disp_gamma0@1400b000 {
compatible = "mediatek,disp_gamma0";
reg = <0 0x1400b000 0 0x1000>;
};
disp_dither0@1400c000 {
compatible = "mediatek,disp_dither0";
reg = <0 0x1400c000 0 0x1000>;
};
disp_wdma0@1400d000 {
compatible = "mediatek,disp_wdma0";
reg = <0 0x1400d000 0 0x1000>;
};
dsi0@1400e000 {
compatible = "mediatek,dsi0";
reg = <0 0x1400e000 0 0x1000>;
};
dbpi0@1400f000 {
compatible = "mediatek,dbpi0";
reg = <0 0x1400f000 0 0x1000>;
};
smi_sub_common0@14010000 {
compatible = "mediatek,smi_sub_common0";
reg = <0 0x14010000 0 0x1000>;
};
smi_common0@14016000 {
compatible = "mediatek,smi_common0";
reg = <0 0x14016000 0 0x1000>;
};
smi_larb0: larb@14017000 {
compatible = "mediatek,smi_larb0";
reg = <0 0x14017000 0 0x1000>;
mediatek,larb-id = <0>;
};
spi0: spi0@1100a000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x1100a000 0 0x100>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen_clk CLK_TOP_SPI_SEL>,
<&infracfg_ao_clk CLK_IFRAO_SPI0>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
spi1: spi1@11010000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x11010000 0 0x100>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen_clk CLK_TOP_SPI_SEL>,
<&infracfg_ao_clk CLK_IFRAO_SPI1>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
spi2: spi2@11012000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x11012000 0 0x100>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen_clk CLK_TOP_SPI_SEL>,
<&infracfg_ao_clk CLK_IFRAO_SPI2>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
spi3: spi3@11013000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x11013000 0 0x100>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen_clk CLK_TOP_SPI_SEL>,
<&infracfg_ao_clk CLK_IFRAO_SPI3>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
iommu0: iommu@14011000 {
compatible = "mediatek,mt6880-m4u";
reg = <0 14011000 0 0x1000>;
mediatek,larbs = <&smi_larb0>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
#if 0
clocks = <&dispsys_config MM_SMI_INFRA>,
<&dispsys_config MM_SMI_IOMMU>,
<&scpsys SCP_SYS_DIS>;
clock-names = "disp-infra-ck", "disp-iommu-ck", "power";
#endif
#iommu-cells = <1>;
};
amms_control {
compatible = "mediatek,amms";
interrupts = <GIC_SPI 425 IRQ_TYPE_EDGE_RISING>;
};
mtk_m4u_debug {
compatible = "mediatek,mt6880-m4u-debug";
#if 0
iommus = <&iommu0 M4U_PORT_DISP_POSTMASK0>,
<&iommu0 M4U_PORT_OVL_RDMA0_HDR>,
<&iommu0 M4U_PORT_OVL_RDMA0>,
<&iommu0 M4U_PORT_DISP_FAKE0>;
#endif
};
reserved@14018000 {
compatible = "mediatek,reserved";
reg = <0 0x14018000 0 0x1000>;
};
reserved@14019000 {
compatible = "mediatek,reserved";
reg = <0 0x14019000 0 0x1000>;
};
reserved@1401a000 {
compatible = "mediatek,reserved";
reg = <0 0x1401a000 0 0x1000>;
};
reserved@1401b000 {
compatible = "mediatek,reserved";
reg = <0 0x1401b000 0 0x1000>;
};
reserved@1401c000 {
compatible = "mediatek,reserved";
reg = <0 0x1401c000 0 0x1000>;
};
reserved@1401d000 {
compatible = "mediatek,reserved";
reg = <0 0x1401d000 0 0x1000>;
};
reserved@1401e000 {
compatible = "mediatek,reserved";
reg = <0 0x1401e000 0 0x1000>;
};
reserved@1401f000 {
compatible = "mediatek,reserved";
reg = <0 0x1401f000 0 0x1000>;
};
reserved@14020000 {
compatible = "mediatek,reserved";
reg = <0 0x14020000 0 0x1000>;
};
reserved@14021000 {
compatible = "mediatek,reserved";
reg = <0 0x14021000 0 0x1000>;
};
reserved@14022000 {
compatible = "mediatek,reserved";
reg = <0 0x14022000 0 0x1000>;
};
reserved@14023000 {
compatible = "mediatek,reserved";
reg = <0 0x14023000 0 0x1000>;
};
reserved@14024000 {
compatible = "mediatek,reserved";
reg = <0 0x14024000 0 0x1000>;
};
reserved@14025000 {
compatible = "mediatek,reserved";
reg = <0 0x14025000 0 0x1000>;
};
reserved@14026000 {
compatible = "mediatek,reserved";
reg = <0 0x14026000 0 0xda000>;
};
medmcu: medmcu@15f00000 {
compatible = "mediatek,medmcu";
status = "okay";
reg = <0 0x15d00000 0 0x20000>, /* tcm */
<0 0x15f24000 0 0x1000>, /* cfg */
<0 0x15f21000 0 0x1000>, /* clk*/
<0 0x15f30000 0 0x1000>, /* cfg core0 */
<0 0x15f40000 0 0x1000>, /* cfg core1 */
<0 0x15f52000 0 0x1000>, /* bus tracker */
<0 0x15f60000 0 0x40000>, /* llc */
<0 0x15fa5000 0 0x4>, /* cfg_sec */
<0 0x15ffb000 0 0x100>, /* mbox0 base */
<0 0x15ffb100 0 0x4>, /* mbox0 set */
<0 0x15ffb10c 0 0x4>, /* mbox0 clr */
<0 0x15fa5020 0 0x4>, /* mbox0 init */
<0 0x15ffc000 0 0x100>, /* mbox1 base */
<0 0x15ffc100 0 0x4>, /* mbox1 set */
<0 0x15ffc10c 0 0x4>, /* mbox1 clr */
<0 0x15fa5024 0 0x4>, /* mbox1 init */
<0 0x15ffd000 0 0x100>, /* mbox2 base */
<0 0x15ffd100 0 0x4>, /* mbox2 set */
<0 0x15ffd10c 0 0x4>, /* mbox2 clr */
<0 0x15fa5028 0 0x4>, /* mbox2 init */
<0 0x15ffe000 0 0x100>, /* mbox3 base */
<0 0x15ffe100 0 0x4>, /* mbox3 set */
<0 0x15ffe10c 0 0x4>, /* mbox3 clr */
<0 0x15fa502c 0 0x4>, /* mbox3 init */
<0 0x15fff000 0 0x100>, /* mbox4 base */
<0 0x15fff100 0 0x4>, /* mbox4 set */
<0 0x15fff10c 0 0x4>, /* mbox4 clr */
<0 0x15fa5030 0 0x4>; /* mbox4 init */
reg-names = "scp_sram_base",
"scp_cfgreg",
"scp_clkreg",
"scp_cfgreg_core0",
"scp_cfgreg_core1",
"scp_bus_tracker",
"scp_l1creg",
"scp_cfgreg_sec",
"mbox0_base",
"mbox0_set",
"mbox0_clr",
"mbox0_init",
"mbox1_base",
"mbox1_set",
"mbox1_clr",
"mbox1_init",
"mbox2_base",
"mbox2_set",
"mbox2_clr",
"mbox2_init",
"mbox3_base",
"mbox3_set",
"mbox3_clr",
"mbox3_init",
"mbox4_base",
"mbox4_set",
"mbox4_clr",
"mbox4_init";
interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mbox0",
"mbox1",
"mbox2",
"mbox3",
"mbox4";
core_0 = "enable";
scp_sramSize = <0x00020000>;
};
consys: consys@18000000 {
compatible = "mediatek,mt6880-consys";
#thermal-sensor-cells = <0>;
/* conn_infra_rgu */
reg = <0 0x18000000 0 0x1000>,
/* conn_infra_cfg */
<0 0x18001000 0 0x1000>,
/* conn_host_csr_top */
<0 0x18060000 0 0x10000>,
/* infracfg_ao */
<0 0x10001000 0 0x1000>,
/* TOP RGU */
<0 0x10007000 0 0x1000>,
/* SPM */
<0 0x10006000 0 0x1000>,
/* INFRACFG */
<0 0x1020e000 0 0x1000>,
/* conn_wt_slp_ctl_reg */
<0 0x18005000 0 0x1000>,
/* conn_afe_ctl */
<0 0x18003000 0 0x1000>,
/* GPIO */
<0 0x10005000 0 0x1000>,
/* conn_rf_spi_mst_reg */
<0 0x18004000 0 0x1000>,
/* conn_semaphore */
<0 0x18070000 0 0x10000>,
/* conn_top_therm_ctl */
<0 0x18002000 0 0x1000>,
/* IOCFG_BM */
<0 0x11d10000 0 0x1000>,
/* debug_ctrl */
<0 0x1800f000 0 0x1000>,
/* conn_infra_clkgen_on_top */
<0 0x18009000 0 0x1000>,
/* conn_infra_bus_cr */
<0 0x1800e000 0 0x400>,
/* conn_infra_debug_ctrl_ao */
<0 0x1802f000 0 0x430>;
power-domains = <&scpsys MT6890_POWER_DOMAIN_CONN>;
};
gps: gps@18C00000 {
compatible = "mediatek,connac2-gps";
reg = <0 0x18000000 0 0x100000>,
<0 0x18C00000 0 0x100000>,
<0 0x10003304 0 0x4>,
<0 0x1001C000 0 0x4>,
<0 0x1001C030 0 0x4>;
reg-names = "conn_infra_base", "conn_gps_base",
"status_dummy_cr", "tia2_gps_on", "tia2_gps_rc_sel";
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&gps_mem>;
pmic = <&pmic_efuse>;
mtk-vcore-supply = <&dvfsrc_vcore>;
};
odm: odm {
compatible = "simple-bus";
/* reserved for overlay by odm */
};
pmic_clock_buffer_ctrl: pmic_clock_buffer_ctrl {
compatible = "mediatek,pmic_clock_buffer";
mediatek,clkbuf-quantity = <7>;
mediatek,clkbuf-config = <2 1 1 2 0 0 2>;
mediatek,clkbuf-output-impedance = <3 4 3 4 0 0 3>;
mediatek,clkbuf-controls-for-desense = <0 4 0 3 0 0 0>;
mediatek,bblpm-support = "enable";
pwrap-dcxo-en = <0x24 4 0x28 1 0x28 0>;
pwrap-dcxo-conn = <0x5c 0 0x5c 16 0x60 0 0x60 16>;
pwrap-dcxo-nfc = <0x64 0 0x64 16 0x68 0 0x68 16>;
spm-pwr-status = <0x16c 0 0x16c 1>;
spm-io-en = <0x2c 7>;
spm-power-on-val = <0x8 21 0x8 14>;
spm-sck-con = <0xc 24>;
pcm-reg7-rf = <0x10c 21>;
pwrap = <&spmi_bus>;
sleep = <&sleep>;
};
typec_switch: typec_switch {
compatible = "mediatek,typec_switch";
};
afe: mt6880-afe-pcm@11210000 {
compatible = "mediatek,mt6880-sound";
reg = <0 0x11210000 0 0x1000>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
i2s3-share = "I2S0";
topckgen = <&topckgen_clk>;
power-domains = <&scpsys MT6890_POWER_DOMAIN_AUDIO>;
clocks = <&audsys_clk CLK_AUDSYS_AFE>,
<&audsys_clk CLK_AUDSYS_DAC>,
<&audsys_clk CLK_AUDSYS_DAC_PREDIS>,
<&audsys_clk CLK_AUDSYS_ADC>,
<&audsys_clk CLK_AUDSYS_22M>,
<&audsys_clk CLK_AUDSYS_24M>,
<&audsys_clk CLK_AUDSYS_APLL_TUNER>,
<&audsys_clk CLK_AUDSYS_APLL2_TUNER>,
<&audsys_clk CLK_AUDSYS_TDM>,
<&audsys_clk CLK_AUDSYS_TML>,
<&infracfg_ao_clk CLK_IFRAO_AUDIO>,
<&infracfg_ao_clk CLK_IFRAO_AUDIO_26M_BCLK>,
<&topckgen_clk CLK_TOP_AUDIO_SEL>,
<&topckgen_clk CLK_TOP_AUD_INTBUS_SEL>,
<&topckgen_clk CLK_TOP_MMPLL_D4_D4>,
<&topckgen_clk CLK_TOP_AUD_1_SEL>,
<&topckgen_clk CLK_TOP_APLL1>,
<&topckgen_clk CLK_TOP_AUD_2_SEL>,
<&topckgen_clk CLK_TOP_APLL2>,
<&topckgen_clk CLK_TOP_AUD_ENGEN1_SEL>,
<&topckgen_clk CLK_TOP_APLL1_D8>,
<&topckgen_clk CLK_TOP_AUD_ENGEN2_SEL>,
<&topckgen_clk CLK_TOP_APLL2_D8>,
<&topckgen_clk CLK_TOP_APLL_I2S0_MCK_SEL>,
<&topckgen_clk CLK_TOP_APLL_I2S1_MCK_SEL>,
<&topckgen_clk CLK_TOP_APLL_I2S2_MCK_SEL>,
<&topckgen_clk CLK_TOP_APLL_I2S4_MCK_SEL>,
<&topckgen_clk CLK_TOP_APLL_TDMOUT_MCK_SEL>,
<&topckgen_clk CLK_TOP_APLL_I2S5_MCK_SEL>,
<&topckgen_clk CLK_TOP_APLL_I2S6_MCK_SEL>,
<&topckgen_clk CLK_TOP_APLL12_CK_DIV0>,
<&topckgen_clk CLK_TOP_APLL12_CK_DIV1>,
<&topckgen_clk CLK_TOP_APLL12_CK_DIV2>,
<&topckgen_clk CLK_TOP_APLL12_CK_DIV4>,
<&topckgen_clk CLK_TOP_APLL12_CK_DIV_TDMOUT_M>,
<&topckgen_clk CLK_TOP_APLL12_CK_DIV_TDMOUT_B>,
<&topckgen_clk CLK_TOP_APLL12_CK_DIV5>,
<&topckgen_clk CLK_TOP_APLL12_CK_DIV6>,
<&topckgen_clk CLK_TOP_TCK_26M_MX9>;
clock-names = "aud_afe_clk",
"aud_dac_clk",
"aud_dac_predis_clk",
"aud_adc_clk",
"aud_apll22m_clk",
"aud_apll24m_clk",
"aud_apll1_tuner_clk",
"aud_apll2_tuner_clk",
"aud_tdm_clk",
"aud_tml_clk",
"aud_infra_clk",
"mtkaif_26m_clk",
"top_mux_audio",
"top_mux_audio_int",
"top_mainpll_d2_d4",
"top_mux_aud_1",
"top_apll1_ck",
"top_mux_aud_2",
"top_apll2_ck",
"top_mux_aud_eng1",
"top_apll1_d8",
"top_mux_aud_eng2",
"top_apll2_d8",
"top_i2s0_m_sel",
"top_i2s1_m_sel",
"top_i2s2_m_sel",
"top_i2s4_m_sel",
"top_tdm_m_sel",
"top_i2s5_m_sel",
"top_i2s6_m_sel",
"top_apll12_div0",
"top_apll12_div1",
"top_apll12_div2",
"top_apll12_div4",
"top_apll12_divm",
"top_apll12_divb",
"top_apll12_div5",
"top_apll12_div6",
"top_clk26m_clk";
pinctrl-names = "aud_gpio_i2s0_off",
"aud_gpio_i2s0_on",
"aud_gpio_i2s1_off",
"aud_gpio_i2s1_on",
"aud_gpio_i2s2_off",
"aud_gpio_i2s2_on",
"aud_gpio_i2s3_off",
"aud_gpio_i2s3_on",
"aud_gpio_i2s4_off",
"aud_gpio_i2s4_on",
"aud_gpio_i2s5_off",
"aud_gpio_i2s5_on",
"aud_gpio_i2s6_off",
"aud_gpio_i2s6_on",
"aud_gpio_proslic_off",
"aud_gpio_proslic_on",
"aud_gpio_tdm_off",
"aud_gpio_tdm_on",
"extamp-pullhigh",
"extamp-pulllow";
pinctrl-0 = <&aud_gpio_i2s0_off>;
pinctrl-1 = <&aud_gpio_i2s0_on>;
pinctrl-2 = <&aud_gpio_i2s1_off>;
pinctrl-3 = <&aud_gpio_i2s1_on>;
pinctrl-4 = <&aud_gpio_i2s2_off>;
pinctrl-5 = <&aud_gpio_i2s2_on>;
pinctrl-6 = <&aud_gpio_i2s3_off>;
pinctrl-7 = <&aud_gpio_i2s3_on>;
pinctrl-8 = <&aud_gpio_i2s4_off>;
pinctrl-9 = <&aud_gpio_i2s4_on>;
pinctrl-10 = <&aud_gpio_i2s5_off>;
pinctrl-11 = <&aud_gpio_i2s5_on>;
pinctrl-12 = <&aud_gpio_i2s6_off>;
pinctrl-13 = <&aud_gpio_i2s6_on>;
pinctrl-14 = <&aud_gpio_proslic_off>;
pinctrl-15 = <&aud_gpio_proslic_on>;
pinctrl-16 = <&aud_gpio_tdm_off>;
pinctrl-17 = <&aud_gpio_tdm_on>;
pinctrl-18 = <&aud_pins_extamp_high>;
pinctrl-19 = <&aud_pins_extamp_low>;
};
sound: sound {
compatible = "mediatek,mt6880-mt6359-sound";
mediatek,platform = <&afe>;
};
audio_sram@11211000 {
compatible = "mediatek,audio_sram";
reg = <0 0x11211000 0 0x10000>;
prefer_mode = <1>;
mode_size = <0xC000 0x10000>;
block_size = <0x1000>;
};
smart_pa: smart_pa {
};
extcon_usb: extcon_usb {
compatible = "mediatek,extcon-usb";
dev-conn = <&ssusb>;
};
};
&spmi_bus {
mt6315_5: mt6315@5 {
compatible = "mediatek,mt6315", "mtk,spmi-pmic";
reg = <0x5 SPMI_USID 0xb SPMI_GSID>;
#address-cells = <1>;
#size-cells = <0>;
mt6315_5_regulator: mt6315_5_regulator {
compatible = "mediatek,mt6315_5-regulator";
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&pio>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
};
md1_sim1_hot_plug_eint: md1_sim1_hot_plug_eint {
};
md1_sim2_hot_plug_eint: md1_sim2_hot_plug_eint {
};
};
#include "mt6890-clkao.dtsi"
#include "mt6330.dtsi"
#include "cust_mt6890_msdc.dtsi"
&pmic {
mt63xx_ot_debug: mt63xx-ot-debug {
compatible = "mediatek,mt63xx-ot-debug";
interrupt-parent = <&mt6315_5_regulator>;
/* INT_TEMP_H */
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
};
};