| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | Kernel driver ina209 |
| 2 | ===================== |
| 3 | |
| 4 | Supported chips: |
| 5 | * Burr-Brown / Texas Instruments INA209 |
| 6 | Prefix: 'ina209' |
| 7 | Addresses scanned: - |
| 8 | Datasheet: |
| 9 | http://www.ti.com/lit/gpn/ina209 |
| 10 | |
| 11 | Author: Paul Hays <Paul.Hays@cattail.ca> |
| 12 | Author: Ira W. Snyder <iws@ovro.caltech.edu> |
| 13 | Author: Guenter Roeck <linux@roeck-us.net> |
| 14 | |
| 15 | |
| 16 | Description |
| 17 | ----------- |
| 18 | |
| 19 | The TI / Burr-Brown INA209 monitors voltage, current, and power on the high side |
| 20 | of a D.C. power supply. It can perform measurements and calculations in the |
| 21 | background to supply readings at any time. It includes a programmable |
| 22 | calibration multiplier to scale the displayed current and power values. |
| 23 | |
| 24 | |
| 25 | Sysfs entries |
| 26 | ------------- |
| 27 | |
| 28 | The INA209 chip is highly configurable both via hardwiring and via |
| 29 | the I2C bus. See the datasheet for details. |
| 30 | |
| 31 | This tries to expose most monitoring features of the hardware via |
| 32 | sysfs. It does not support every feature of this chip. |
| 33 | |
| 34 | |
| 35 | in0_input shunt voltage (mV) |
| 36 | in0_input_highest shunt voltage historical maximum reading (mV) |
| 37 | in0_input_lowest shunt voltage historical minimum reading (mV) |
| 38 | in0_reset_history reset shunt voltage history |
| 39 | in0_max shunt voltage max alarm limit (mV) |
| 40 | in0_min shunt voltage min alarm limit (mV) |
| 41 | in0_crit_max shunt voltage crit max alarm limit (mV) |
| 42 | in0_crit_min shunt voltage crit min alarm limit (mV) |
| 43 | in0_max_alarm shunt voltage max alarm limit exceeded |
| 44 | in0_min_alarm shunt voltage min alarm limit exceeded |
| 45 | in0_crit_max_alarm shunt voltage crit max alarm limit exceeded |
| 46 | in0_crit_min_alarm shunt voltage crit min alarm limit exceeded |
| 47 | |
| 48 | in1_input bus voltage (mV) |
| 49 | in1_input_highest bus voltage historical maximum reading (mV) |
| 50 | in1_input_lowest bus voltage historical minimum reading (mV) |
| 51 | in1_reset_history reset bus voltage history |
| 52 | in1_max bus voltage max alarm limit (mV) |
| 53 | in1_min bus voltage min alarm limit (mV) |
| 54 | in1_crit_max bus voltage crit max alarm limit (mV) |
| 55 | in1_crit_min bus voltage crit min alarm limit (mV) |
| 56 | in1_max_alarm bus voltage max alarm limit exceeded |
| 57 | in1_min_alarm bus voltage min alarm limit exceeded |
| 58 | in1_crit_max_alarm bus voltage crit max alarm limit exceeded |
| 59 | in1_crit_min_alarm bus voltage crit min alarm limit exceeded |
| 60 | |
| 61 | power1_input power measurement (uW) |
| 62 | power1_input_highest power historical maximum reading (uW) |
| 63 | power1_reset_history reset power history |
| 64 | power1_max power max alarm limit (uW) |
| 65 | power1_crit power crit alarm limit (uW) |
| 66 | power1_max_alarm power max alarm limit exceeded |
| 67 | power1_crit_alarm power crit alarm limit exceeded |
| 68 | |
| 69 | curr1_input current measurement (mA) |
| 70 | |
| 71 | update_interval data conversion time; affects number of samples used |
| 72 | to average results for shunt and bus voltages. |
| 73 | |
| 74 | General Remarks |
| 75 | --------------- |
| 76 | |
| 77 | The power and current registers in this chip require that the calibration |
| 78 | register is programmed correctly before they are used. Normally this is expected |
| 79 | to be done in the BIOS. In the absence of BIOS programming, the shunt resistor |
| 80 | voltage can be provided using platform data. The driver uses platform data from |
| 81 | the ina2xx driver for this purpose. If calibration register data is not provided |
| 82 | via platform data, the driver checks if the calibration register has been |
| 83 | programmed (ie has a value not equal to zero). If so, this value is retained. |
| 84 | Otherwise, a default value reflecting a shunt resistor value of 10 mOhm is |
| 85 | programmed into the calibration register. |
| 86 | |
| 87 | |
| 88 | Output Pins |
| 89 | ----------- |
| 90 | |
| 91 | Output pin programming is a board feature which depends on the BIOS. It is |
| 92 | outside the scope of a hardware monitoring driver to enable or disable output |
| 93 | pins. |