| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /*: |
| 2 | * Address mappings and base address for OMAP5 interconnects |
| 3 | * and peripherals. |
| 4 | * |
| 5 | * Copyright (C) 2012 Texas Instruments |
| 6 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 7 | * Sricharan <r.sricharan@ti.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | #ifndef __ASM_SOC_OMAP54XX_H |
| 14 | #define __ASM_SOC_OMAP54XX_H |
| 15 | |
| 16 | /* |
| 17 | * Please place only base defines here and put the rest in device |
| 18 | * specific headers. |
| 19 | */ |
| 20 | #define L4_54XX_BASE 0x4a000000 |
| 21 | #define L4_WK_54XX_BASE 0x4ae00000 |
| 22 | #define L4_PER_54XX_BASE 0x48000000 |
| 23 | #define L3_54XX_BASE 0x44000000 |
| 24 | #define OMAP54XX_32KSYNCT_BASE 0x4ae04000 |
| 25 | #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000 |
| 26 | #define OMAP54XX_CM_CORE_BASE 0x4a008000 |
| 27 | #define OMAP54XX_PRM_BASE 0x4ae06000 |
| 28 | #define OMAP54XX_PRCM_MPU_BASE 0x48243000 |
| 29 | #define OMAP54XX_SCM_BASE 0x4a002000 |
| 30 | #define OMAP54XX_CTRL_BASE 0x4a002800 |
| 31 | #define OMAP54XX_SAR_RAM_BASE 0x4ae26000 |
| 32 | |
| 33 | /* DRA7 specific base addresses */ |
| 34 | #define L3_MAIN_SN_DRA7XX_BASE 0x44000000 |
| 35 | #define L4_PER1_DRA7XX_BASE 0x48000000 |
| 36 | #define L4_CFG_MPU_DRA7XX_BASE 0x48210000 |
| 37 | #define L4_PER2_DRA7XX_BASE 0x48400000 |
| 38 | #define L4_PER3_DRA7XX_BASE 0x48800000 |
| 39 | #define L4_CFG_DRA7XX_BASE 0x4A000000 |
| 40 | #define L4_WKUP_DRA7XX_BASE 0x4ae00000 |
| 41 | #define DRA7XX_CM_CORE_AON_BASE 0x4a005000 |
| 42 | #define DRA7XX_CTRL_BASE 0x4a003400 |
| 43 | #define DRA7XX_TAP_BASE 0x4ae0c000 |
| 44 | |
| 45 | #endif /* __ASM_SOC_OMAP555554XX_H */ |