| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (c) 2004 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * |
| 6 | * S3C2410 Power Manager (Suspend-To-RAM) support |
| 7 | * |
| 8 | * Based on PXA/SA1100 sleep code by: |
| 9 | * Nicolas Pitre, (c) 2002 Monta Vista Software Inc |
| 10 | * Cliff Brake, (c) 2001 |
| 11 | */ |
| 12 | |
| 13 | #include <linux/linkage.h> |
| 14 | #include <linux/serial_s3c.h> |
| 15 | #include <asm/assembler.h> |
| 16 | #include <mach/hardware.h> |
| 17 | #include <mach/map.h> |
| 18 | |
| 19 | #include <mach/regs-gpio.h> |
| 20 | #include <mach/regs-clock.h> |
| 21 | |
| 22 | #include "regs-mem.h" |
| 23 | |
| 24 | /* s3c2410_cpu_suspend |
| 25 | * |
| 26 | * put the cpu into sleep mode |
| 27 | */ |
| 28 | |
| 29 | ENTRY(s3c2410_cpu_suspend) |
| 30 | @@ prepare cpu to sleep |
| 31 | |
| 32 | ldr r4, =S3C2410_REFRESH |
| 33 | ldr r5, =S3C24XX_MISCCR |
| 34 | ldr r6, =S3C2410_CLKCON |
| 35 | ldr r7, [r4] @ get REFRESH (and ensure in TLB) |
| 36 | ldr r8, [r5] @ get MISCCR (and ensure in TLB) |
| 37 | ldr r9, [r6] @ get CLKCON (and ensure in TLB) |
| 38 | |
| 39 | orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command |
| 40 | orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals |
| 41 | orr r9, r9, #S3C2410_CLKCON_POWER @ power down command |
| 42 | |
| 43 | teq pc, #0 @ first as a trial-run to load cache |
| 44 | bl s3c2410_do_sleep |
| 45 | teq r0, r0 @ now do it for real |
| 46 | b s3c2410_do_sleep @ |
| 47 | |
| 48 | @@ align next bit of code to cache line |
| 49 | .align 5 |
| 50 | s3c2410_do_sleep: |
| 51 | streq r7, [r4] @ SDRAM sleep command |
| 52 | streq r8, [r5] @ SDRAM power-down config |
| 53 | streq r9, [r6] @ CPU sleep |
| 54 | 1: beq 1b |
| 55 | ret lr |