| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mm/tlbv4wb.S |
| 3 | * |
| 4 | * Copyright (C) 1997-2002 Russell King |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * ARM architecture version 4 TLB handling functions. |
| 11 | * These assume a split I/D TLBs w/o I TLB entry, with a write buffer. |
| 12 | * |
| 13 | * Processors: SA110 SA1100 SA1110 |
| 14 | */ |
| 15 | #include <linux/linkage.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <asm/assembler.h> |
| 18 | #include <asm/asm-offsets.h> |
| 19 | #include <asm/tlbflush.h> |
| 20 | #include "proc-macros.S" |
| 21 | |
| 22 | .align 5 |
| 23 | /* |
| 24 | * v4wb_flush_user_tlb_range(start, end, mm) |
| 25 | * |
| 26 | * Invalidate a range of TLB entries in the specified address space. |
| 27 | * |
| 28 | * - start - range start address |
| 29 | * - end - range end address |
| 30 | * - mm - mm_struct describing address space |
| 31 | */ |
| 32 | .align 5 |
| 33 | ENTRY(v4wb_flush_user_tlb_range) |
| 34 | vma_vm_mm ip, r2 |
| 35 | act_mm r3 @ get current->active_mm |
| 36 | eors r3, ip, r3 @ == mm ? |
| 37 | retne lr @ no, we dont do anything |
| 38 | vma_vm_flags r2, r2 |
| 39 | mcr p15, 0, r3, c7, c10, 4 @ drain WB |
| 40 | tst r2, #VM_EXEC |
| 41 | mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB |
| 42 | bic r0, r0, #0x0ff |
| 43 | bic r0, r0, #0xf00 |
| 44 | 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry |
| 45 | add r0, r0, #PAGE_SZ |
| 46 | cmp r0, r1 |
| 47 | blo 1b |
| 48 | ret lr |
| 49 | |
| 50 | /* |
| 51 | * v4_flush_kern_tlb_range(start, end) |
| 52 | * |
| 53 | * Invalidate a range of TLB entries in the specified kernel |
| 54 | * address range. |
| 55 | * |
| 56 | * - start - virtual address (may not be aligned) |
| 57 | * - end - virtual address (may not be aligned) |
| 58 | */ |
| 59 | ENTRY(v4wb_flush_kern_tlb_range) |
| 60 | mov r3, #0 |
| 61 | mcr p15, 0, r3, c7, c10, 4 @ drain WB |
| 62 | bic r0, r0, #0x0ff |
| 63 | bic r0, r0, #0xf00 |
| 64 | mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB |
| 65 | 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry |
| 66 | add r0, r0, #PAGE_SZ |
| 67 | cmp r0, r1 |
| 68 | blo 1b |
| 69 | ret lr |
| 70 | |
| 71 | __INITDATA |
| 72 | |
| 73 | /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */ |
| 74 | define_tlb_functions v4wb, v4wb_tlb_flags |