| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * intc2.c -- support for the 2nd INTC controller of the 5249 |
| 3 | * |
| 4 | * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> |
| 5 | * |
| 6 | * This file is subject to the terms and conditions of the GNU General Public |
| 7 | * License. See the file COPYING in the main directory of this archive |
| 8 | * for more details. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/types.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/irq.h> |
| 16 | #include <linux/io.h> |
| 17 | #include <asm/coldfire.h> |
| 18 | #include <asm/mcfsim.h> |
| 19 | |
| 20 | static void intc2_irq_gpio_mask(struct irq_data *d) |
| 21 | { |
| 22 | u32 imr; |
| 23 | imr = readl(MCFSIM2_GPIOINTENABLE); |
| 24 | imr &= ~(0x1 << (d->irq - MCF_IRQ_GPIO0)); |
| 25 | writel(imr, MCFSIM2_GPIOINTENABLE); |
| 26 | } |
| 27 | |
| 28 | static void intc2_irq_gpio_unmask(struct irq_data *d) |
| 29 | { |
| 30 | u32 imr; |
| 31 | imr = readl(MCFSIM2_GPIOINTENABLE); |
| 32 | imr |= (0x1 << (d->irq - MCF_IRQ_GPIO0)); |
| 33 | writel(imr, MCFSIM2_GPIOINTENABLE); |
| 34 | } |
| 35 | |
| 36 | static void intc2_irq_gpio_ack(struct irq_data *d) |
| 37 | { |
| 38 | writel(0x1 << (d->irq - MCF_IRQ_GPIO0), MCFSIM2_GPIOINTCLEAR); |
| 39 | } |
| 40 | |
| 41 | static struct irq_chip intc2_irq_gpio_chip = { |
| 42 | .name = "CF-INTC2", |
| 43 | .irq_mask = intc2_irq_gpio_mask, |
| 44 | .irq_unmask = intc2_irq_gpio_unmask, |
| 45 | .irq_ack = intc2_irq_gpio_ack, |
| 46 | }; |
| 47 | |
| 48 | static int __init mcf_intc2_init(void) |
| 49 | { |
| 50 | int irq; |
| 51 | |
| 52 | /* GPIO interrupt sources */ |
| 53 | for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO7); irq++) { |
| 54 | irq_set_chip(irq, &intc2_irq_gpio_chip); |
| 55 | irq_set_handler(irq, handle_edge_irq); |
| 56 | } |
| 57 | |
| 58 | return 0; |
| 59 | } |
| 60 | |
| 61 | arch_initcall(mcf_intc2_init); |