| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | |
| 3 | /* |
| 4 | |
| 5 | * Copyright (c) 2019 MediaTek Inc. |
| 6 | |
| 7 | */ |
| 8 | |
| 9 | #include <linux/clk-provider.h> |
| 10 | #include <linux/platform_device.h> |
| 11 | |
| 12 | #include "clk-mtk.h" |
| 13 | #include "clk-gate.h" |
| 14 | |
| 15 | #include <dt-bindings/clock/mt6880-clk.h> |
| 16 | |
| 17 | #define MT_CLKMGR_MODULE_INIT 0 |
| 18 | |
| 19 | #define MT_CCF_BRINGUP 1 |
| 20 | |
| 21 | #define INV_OFS -1 |
| 22 | |
| 23 | /* get spm power status struct to register inside clk_data */ |
| 24 | static struct pwr_status pwr_stat = GATE_PWR_STAT(0x16C, |
| 25 | 0x170, INV_OFS, BIT(2), BIT(2)); |
| 26 | |
| 27 | static const struct mtk_gate_regs mfgcfg_cg_regs = { |
| 28 | .set_ofs = 0x4, |
| 29 | .clr_ofs = 0x8, |
| 30 | .sta_ofs = 0x0, |
| 31 | }; |
| 32 | |
| 33 | #define GATE_MFGCFG(_id, _name, _parent, _shift) { \ |
| 34 | .id = _id, \ |
| 35 | .name = _name, \ |
| 36 | .parent_name = _parent, \ |
| 37 | .regs = &mfgcfg_cg_regs, \ |
| 38 | .shift = _shift, \ |
| 39 | .ops = &mtk_clk_gate_ops_setclr, \ |
| 40 | .pwr_stat = &pwr_stat, \ |
| 41 | } |
| 42 | |
| 43 | static const struct mtk_gate mfgcfg_clks[] = { |
| 44 | GATE_MFGCFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d", |
| 45 | "mfg_ck"/* parent */, 0), |
| 46 | }; |
| 47 | |
| 48 | static int clk_mt6880_mfgcfg_probe(struct platform_device *pdev) |
| 49 | { |
| 50 | struct clk_onecell_data *clk_data; |
| 51 | int r; |
| 52 | struct device_node *node = pdev->dev.of_node; |
| 53 | |
| 54 | #if MT_CCF_BRINGUP |
| 55 | pr_notice("%s init begin\n", __func__); |
| 56 | #endif |
| 57 | |
| 58 | clk_data = mtk_alloc_clk_data(CLK_MFGCFG_NR_CLK); |
| 59 | |
| 60 | mtk_clk_register_gates(node, mfgcfg_clks, ARRAY_SIZE(mfgcfg_clks), |
| 61 | clk_data); |
| 62 | |
| 63 | r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| 64 | |
| 65 | if (r) |
| 66 | pr_err("%s(): could not register clock provider: %d\n", |
| 67 | __func__, r); |
| 68 | |
| 69 | #if MT_CCF_BRINGUP |
| 70 | pr_notice("%s init end\n", __func__); |
| 71 | #endif |
| 72 | |
| 73 | return r; |
| 74 | } |
| 75 | |
| 76 | static const struct of_device_id of_match_clk_mt6880_mfgcfg[] = { |
| 77 | { .compatible = "mediatek,mt6880-mfgsys", }, |
| 78 | {} |
| 79 | }; |
| 80 | |
| 81 | #if MT_CLKMGR_MODULE_INIT |
| 82 | |
| 83 | static struct platform_driver clk_mt6880_mfgcfg_drv = { |
| 84 | .probe = clk_mt6880_mfgcfg_probe, |
| 85 | .driver = { |
| 86 | .name = "clk-mt6880-mfgcfg", |
| 87 | .of_match_table = of_match_clk_mt6880_mfgcfg, |
| 88 | }, |
| 89 | }; |
| 90 | |
| 91 | builtin_platform_driver(clk_mt6880_mfgcfg_drv); |
| 92 | |
| 93 | #else |
| 94 | |
| 95 | static struct platform_driver clk_mt6880_mfgcfg_drv = { |
| 96 | .probe = clk_mt6880_mfgcfg_probe, |
| 97 | .driver = { |
| 98 | .name = "clk-mt6880-mfgcfg", |
| 99 | .of_match_table = of_match_clk_mt6880_mfgcfg, |
| 100 | }, |
| 101 | }; |
| 102 | static int __init clk_mt6880_mfgcfg_platform_init(void) |
| 103 | { |
| 104 | return platform_driver_register(&clk_mt6880_mfgcfg_drv); |
| 105 | } |
| 106 | arch_initcall(clk_mt6880_mfgcfg_platform_init); |
| 107 | |
| 108 | #endif /* MT_CLKMGR_MODULE_INIT */ |