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192.168.1.100 / T800 / 0b39b87cb0cd96fd68f16a6d004c85c06a954fb2 / . / src / kernel / linux / v4.19 / drivers / clk / mediatek / clk-mt6890-mm.c
blob: 9685da0130e4af99120bf485240a965d61a47481 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2
3/*
4
5 * Copyright (c) 2019 MediaTek Inc.
6
7 */
8
9
10#include <linux/clk-provider.h>
11#include <linux/platform_device.h>
12
13#include "clk-mtk.h"
14#include "clk-gate.h"
15
16#include <dt-bindings/clock/mt6890-clk.h>
17
18#define MT_CLKMGR_MODULE_INIT 0
19
20#define MT_CCF_BRINGUP 1
21
22#define INV_OFS -1
23
24
25
26static const struct mtk_gate_regs mm_cg0_regs = {
27 .set_ofs = 0x104,
28 .clr_ofs = 0x108,
29 .sta_ofs = 0x100,
30};
31static const struct mtk_gate_regs mm_cg1_regs = {
32 .set_ofs = 0x114,
33 .clr_ofs = 0x118,
34 .sta_ofs = 0x110,
35};
36static const struct mtk_gate_regs mm_cg2_regs = {
37 .set_ofs = 0x124,
38 .clr_ofs = 0x128,
39 .sta_ofs = 0x120,
40};
41
42#define GATE_MM0(_id, _name, _parent, _shift) { \
43 .id = _id, \
44 .name = _name, \
45 .parent_name = _parent, \
46 .regs = &mm_cg0_regs, \
47 .shift = _shift, \
48 .ops = &mtk_clk_gate_ops_setclr, \
49 }
50#define GATE_MM1(_id, _name, _parent, _shift) { \
51 .id = _id, \
52 .name = _name, \
53 .parent_name = _parent, \
54 .regs = &mm_cg1_regs, \
55 .shift = _shift, \
56 .ops = &mtk_clk_gate_ops_setclr, \
57 }
58#define GATE_MM2(_id, _name, _parent, _shift) { \
59 .id = _id, \
60 .name = _name, \
61 .parent_name = _parent, \
62 .regs = &mm_cg2_regs, \
63 .shift = _shift, \
64 .ops = &mtk_clk_gate_ops_setclr, \
65 }
66static const struct mtk_gate mm_clks[] = {
67 GATE_MM0(CLK_MMSYS_MUTEX0, "mmsys_mutex0",
68 "mm_ck"/* parent */, 0),
69 GATE_MM0(CLK_MMSYS_APB_BUS, "mmsys_apb_bus",
70 "mm_ck"/* parent */, 1),
71 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0",
72 "mm_ck"/* parent */, 2),
73 GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0",
74 "mm_ck"/* parent */, 3),
75 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0",
76 "mm_ck"/* parent */, 4),
77 GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0",
78 "mm_ck"/* parent */, 5),
79 GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0",
80 "mm_ck"/* parent */, 6),
81 GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0",
82 "mm_ck"/* parent */, 7),
83 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0",
84 "mm_ck"/* parent */, 8),
85 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0",
86 "mm_ck"/* parent */, 9),
87 GATE_MM0(CLK_MMSYS_FAKE_ENG0, "mmsys_fake_eng0",
88 "mm_ck"/* parent */, 10),
89 GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0",
90 "mm_ck"/* parent */, 11),
91 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0",
92 "mm_ck"/* parent */, 12),
93 GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0",
94 "mm_ck"/* parent */, 13),
95 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0",
96 "mm_ck"/* parent */, 14),
97 GATE_MM0(CLK_MM_DBPI0, "mm_dbpi0",
98 "mm_ck"/* parent */, 15),
99 GATE_MM0(CLK_MM_DISP_DSI0, "mm_disp_dsi0",
100 "mm_ck"/* parent */, 16),
101 GATE_MM0(CLK_MMSYS_SMI_COMMON, "mmsys_smi_common",
102 "mm_ck"/* parent */, 17),
103 GATE_MM1(CLK_MMSYS_SMI_COMMON, "disp_axi",
104 "axi_ck"/* parent */, 0),
105 GATE_MM1(CLK_MMSYS_SMI_COMMON, "dsi",
106 "mm_ck"/* parent */, 16),
107 GATE_MM2(CLK_MMSYS_SMI_COMMON, "dbi",
108 "dbi_ck"/* parent */, 0),
109};
110
111static int clk_mt6890_mm_probe(struct platform_device *pdev)
112{
113 struct clk_onecell_data *clk_data;
114 int r;
115 struct device_node *node = pdev->dev.of_node;
116
117#if MT_CCF_BRINGUP
118 pr_notice("%s init begin\n", __func__);
119#endif
120
121 clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
122
123 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
124 clk_data);
125
126 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
127
128 if (r)
129 pr_err("%s(): could not register clock provider: %d\n",
130 __func__, r);
131
132#if MT_CCF_BRINGUP
133 pr_notice("%s init end\n", __func__);
134#endif
135
136 return r;
137}
138
139static const struct of_device_id of_match_clk_mt6890_mm[] = {
140 { .compatible = "mediatek,mt6890-mmsys_config", },
141 {}
142};
143
144#if MT_CLKMGR_MODULE_INIT
145
146static struct platform_driver clk_mt6890_mm_drv = {
147 .probe = clk_mt6890_mm_probe,
148 .driver = {
149 .name = "clk-mt6890-mm",
150 .of_match_table = of_match_clk_mt6890_mm,
151 },
152};
153
154builtin_platform_driver(clk_mt6890_mm_drv);
155
156#else
157
158static struct platform_driver clk_mt6890_mm_drv = {
159 .probe = clk_mt6890_mm_probe,
160 .driver = {
161 .name = "clk-mt6890-mm",
162 .of_match_table = of_match_clk_mt6890_mm,
163 },
164};
165static int __init clk_mt6890_mm_platform_init(void)
166{
167 return platform_driver_register(&clk_mt6890_mm_drv);
168}
169arch_initcall(clk_mt6890_mm_platform_init);
170
171#endif /* MT_CLKMGR_MODULE_INIT */