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192.168.1.100 / T800 / 0b39b87cb0cd96fd68f16a6d004c85c06a954fb2 / . / src / kernel / linux / v4.19 / drivers / clk / mediatek / clkdbg-mt6880.c
blob: 366966c21d73c9117336dc2e6d056bdbec0b5ec2 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2
3/*
4
5 * Copyright (c) 2019 MediaTek Inc.
6
7 */
8
9#include <linux/clk.h>
10#include <linux/clk-provider.h>
11#include <linux/io.h>
12#include <linux/seq_file.h>
13#include <linux/delay.h>
14
15#ifdef CONFIG_MTK_DEVAPC
16#include <linux/soc/mediatek/devapc_public.h>
17#endif
18#include "clk-mux.h"
19#include "clkdbg.h"
20#include "clkdbg-mt6880.h"
21#include "clk-mt6880-fmeter.h"
22
23#define DUMP_INIT_STATE 0
24
25/*
26 * clkdbg dump_regs
27 */
28
29#define REGBASE_V(_phys, _id_name, _pg) { .phys = _phys, \
30 .name = #_id_name, .pg = _pg}
31
32static DEFINE_SPINLOCK(meter_lock);
33#define fmeter_lock(flags) spin_lock_irqsave(&meter_lock, flags)
34#define fmeter_unlock(flags) spin_unlock_irqrestore(&meter_lock, flags)
35/*
36 * checkpatch.pl ERROR:COMPLEX_MACRO
37 *
38 * #define REGBASE(_phys, _id_name) [_id_name] = REGBASE_V(_phys, _id_name)
39 */
40
41static struct regbase rb[] = {
42 [top] = REGBASE_V(0x10000000, top, NULL),
43 [dbgsys_dem] = REGBASE_V(0x0d0a0000, dbgsys_dem, NULL),
44 [ifrao] = REGBASE_V(0x10001000, ifrao, NULL),
45 [infracfg_ao_bus] = REGBASE_V(0x10001000, infracfg_ao_bus, NULL),
46 [peri] = REGBASE_V(0x10003000, peri, NULL),
47 [spm] = REGBASE_V(0x10006000, spm, NULL),
48 [apmixed] = REGBASE_V(0x1000C000, apmixed, NULL),
49 [gce] = REGBASE_V(0x10228000, gce, NULL),
50 [audsys] = REGBASE_V(0x11210000, audsys, "MT6880_POWER_DOMAIN_AUDIO"),
51 [impe] = REGBASE_V(0x11c46000, impe, NULL),
52 [mfgcfg] = REGBASE_V(0x13fbf000, mfgcfg, "MT6880_POWER_DOMAIN_MFG0"),
53 [mm] = REGBASE_V(0x14000000, mm, "MT6880_POWER_DOMAIN_DIS"),
54 {},
55};
56
57#define REGNAME(_base, _ofs, _name) \
58 { .base = &rb[_base], .ofs = _ofs, .name = #_name }
59
60static struct regname rn[] = {
61 /* TOPCKGEN register */
62 REGNAME(top, 0x0010, CLK_CFG_0),
63 REGNAME(top, 0x0020, CLK_CFG_1),
64 REGNAME(top, 0x0030, CLK_CFG_2),
65 REGNAME(top, 0x0040, CLK_CFG_3),
66 REGNAME(top, 0x0050, CLK_CFG_4),
67 REGNAME(top, 0x0060, CLK_CFG_5),
68 REGNAME(top, 0x0070, CLK_CFG_6),
69 REGNAME(top, 0x0080, CLK_CFG_7),
70 REGNAME(top, 0x0090, CLK_CFG_8),
71 REGNAME(top, 0x00A0, CLK_CFG_9),
72 REGNAME(top, 0x00B0, CLK_CFG_10),
73 REGNAME(top, 0x00C0, CLK_CFG_11),
74 REGNAME(top, 0x00D0, CLK_CFG_12),
75 REGNAME(top, 0x0320, CLK_AUDDIV_0),
76 REGNAME(top, 0x0328, CLK_AUDDIV_2),
77 REGNAME(top, 0x0334, CLK_AUDDIV_3),
78 /* DBGSYS_DEM register */
79 REGNAME(dbgsys_dem, 0x70, ATB),
80 REGNAME(dbgsys_dem, 0x2c, DBGBUSCLK_EN),
81 REGNAME(dbgsys_dem, 0x30, DBGSYSCLK_EN),
82 /* INFRACFG_AO register */
83 REGNAME(ifrao, 0x70, INFRA_BUS_DCM_CTRL),
84 REGNAME(ifrao, 0x90, MODULE_SW_CG_0),
85 REGNAME(ifrao, 0x94, MODULE_SW_CG_1),
86 REGNAME(ifrao, 0xac, MODULE_SW_CG_2),
87 REGNAME(ifrao, 0xc8, MODULE_SW_CG_3),
88 REGNAME(ifrao, 0xe8, MODULE_SW_CG_4),
89 REGNAME(ifrao, 0x74, PERI_BUS_DCM_CTRL),
90 /* INFRACFG_AO_BUS register */
91 REGNAME(infracfg_ao_bus, 0x0710, INFRA_TOPAXI_PROTECTEN_2),
92 REGNAME(infracfg_ao_bus, 0x0720, INFRA_TOPAXI_PROTECTEN_STA0_2),
93 REGNAME(infracfg_ao_bus, 0x0724, INFRA_TOPAXI_PROTECTEN_STA1_2),
94 REGNAME(infracfg_ao_bus, 0x0220, INFRA_TOPAXI_PROTECTEN),
95 REGNAME(infracfg_ao_bus, 0x0224, INFRA_TOPAXI_PROTECTEN_STA0),
96 REGNAME(infracfg_ao_bus, 0x0228, INFRA_TOPAXI_PROTECTEN_STA1),
97 REGNAME(infracfg_ao_bus, 0x0250, INFRA_TOPAXI_PROTECTEN_1),
98 REGNAME(infracfg_ao_bus, 0x0254, INFRA_TOPAXI_PROTECTEN_STA0_1),
99 REGNAME(infracfg_ao_bus, 0x0258, INFRA_TOPAXI_PROTECTEN_STA1_1),
100 REGNAME(infracfg_ao_bus, 0x0B80, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR),
101 REGNAME(infracfg_ao_bus, 0x0B8c, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_STA0),
102 REGNAME(infracfg_ao_bus, 0x0B90, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_STA1),
103 REGNAME(infracfg_ao_bus, 0x0BA0, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1),
104 REGNAME(infracfg_ao_bus, 0x0BAc, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_STA0),
105 REGNAME(infracfg_ao_bus, 0x0BB0, INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_STA1),
106 REGNAME(infracfg_ao_bus, 0x0BB4, INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR),
107 REGNAME(infracfg_ao_bus, 0x0BC0, INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_STA0),
108 REGNAME(infracfg_ao_bus, 0x0BC4, INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_STA1),
109 REGNAME(infracfg_ao_bus, 0x02D0, INFRA_TOPAXI_PROTECTEN_MM),
110 REGNAME(infracfg_ao_bus, 0x02E8, INFRA_TOPAXI_PROTECTEN_MM_STA0),
111 REGNAME(infracfg_ao_bus, 0x02EC, INFRA_TOPAXI_PROTECTEN_MM_STA1),
112 /* PERICFG register */
113 REGNAME(peri, 0x20c, PERIAXI_SI0_CTL),
114 /* SPM register */
115 REGNAME(spm, 0x308, MFG0_PWR_CON),
116 REGNAME(spm, 0x324, IFR_PWR_CON),
117 REGNAME(spm, 0x32C, DPY_PWR_CON),
118 REGNAME(spm, 0x330, PEXTP_D_2LX1_PWR_CON),
119 REGNAME(spm, 0x334, PEXTP_R_2LX1_PWR_CON),
120 REGNAME(spm, 0x338, PEXTP_R_1LX2_PWR_CON),
121 REGNAME(spm, 0x33C, ETH_PWR_CON),
122 REGNAME(spm, 0x34C, NETSYS_PWR_CON),
123 REGNAME(spm, 0x350, DIS_PWR_CON),
124 REGNAME(spm, 0x354, AUDIO_PWR_CON),
125 REGNAME(spm, 0x300, MD1_PWR_CON),
126 REGNAME(spm, 0x328, EIP97_PWR_CON),
127 REGNAME(spm, 0x304, CONN_PWR_CON),
128 REGNAME(spm, 0x3C4, DPY2_PWR_CON),
129 REGNAME(spm, 0x3C0, MCUPM_PWR_CON),
130 REGNAME(spm, 0x3A4, MSDC_PWR_CON),
131 REGNAME(spm, 0x3D0, PERI_PWR_CON),
132 REGNAME(spm, 0x344, HSMTOP_PWR_CON),
133 REGNAME(spm, 0x340, SSUSB_PWR_CON),
134 REGNAME(spm, 0x31C, SSUSB_PHY_PWR_CON),
135 REGNAME(spm, 0x358, SGMII_0_PHY_PWR_CON),
136 REGNAME(spm, 0x360, SGMII_0_TOP_PWR_CON),
137 REGNAME(spm, 0x35C, SGMII_1_PHY_PWR_CON),
138 REGNAME(spm, 0x364, SGMII_1_TOP_PWR_CON),
139 REGNAME(spm, 0x30C, PEXTP_D_2LX1_PHY_PWR_CON),
140 REGNAME(spm, 0x310, PEXTP_R_2LX1_PHY_PWR_CON),
141 REGNAME(spm, 0x314, PEXTP_R_1LX2_0P_PHY_PWR_CON),
142 REGNAME(spm, 0x318, PEXTP_R_1LX2_1P_PHY_PWR_CON),
143 REGNAME(spm, 0x368, DRAMC_MD32_PWR_CON),
144 /* APMIXEDSYS register */
145 REGNAME(apmixed, 0x204, ARMPLL_LL_CON0),
146 REGNAME(apmixed, 0x208, ARMPLL_LL_CON1),
147 REGNAME(apmixed, 0x20c, ARMPLL_LL_CON2),
148 REGNAME(apmixed, 0x210, ARMPLL_LL_CON3),
149 REGNAME(apmixed, 0x214, ARMPLL_LL_CON4),
150 REGNAME(apmixed, 0x218, CCIPLL_CON0),
151 REGNAME(apmixed, 0x21c, CCIPLL_CON1),
152 REGNAME(apmixed, 0x220, CCIPLL_CON2),
153 REGNAME(apmixed, 0x224, CCIPLL_CON3),
154 REGNAME(apmixed, 0x228, CCIPLL_CON4),
155 REGNAME(apmixed, 0x604, MPLL_CON0),
156 REGNAME(apmixed, 0x608, MPLL_CON1),
157 REGNAME(apmixed, 0x60c, MPLL_CON2),
158 REGNAME(apmixed, 0x610, MPLL_CON3),
159 REGNAME(apmixed, 0x614, MPLL_CON4),
160 REGNAME(apmixed, 0x404, MAINPLL_CON0),
161 REGNAME(apmixed, 0x408, MAINPLL_CON1),
162 REGNAME(apmixed, 0x40c, MAINPLL_CON2),
163 REGNAME(apmixed, 0x410, MAINPLL_CON3),
164 REGNAME(apmixed, 0x414, MAINPLL_CON4),
165 REGNAME(apmixed, 0x418, UNIVPLL_CON0),
166 REGNAME(apmixed, 0x41c, UNIVPLL_CON1),
167 REGNAME(apmixed, 0x420, UNIVPLL_CON2),
168 REGNAME(apmixed, 0x424, UNIVPLL_CON3),
169 REGNAME(apmixed, 0x428, UNIVPLL_CON4),
170 REGNAME(apmixed, 0x22c, MSDCPLL_CON0),
171 REGNAME(apmixed, 0x230, MSDCPLL_CON1),
172 REGNAME(apmixed, 0x234, MSDCPLL_CON2),
173 REGNAME(apmixed, 0x238, MSDCPLL_CON3),
174 REGNAME(apmixed, 0x23c, MSDCPLL_CON4),
175 REGNAME(apmixed, 0x42c, MMPLL_CON0),
176 REGNAME(apmixed, 0x430, MMPLL_CON1),
177 REGNAME(apmixed, 0x434, MMPLL_CON2),
178 REGNAME(apmixed, 0x438, MMPLL_CON3),
179 REGNAME(apmixed, 0x43c, MMPLL_CON4),
180 REGNAME(apmixed, 0x618, MFGPLL_CON0),
181 REGNAME(apmixed, 0x61c, MFGPLL_CON1),
182 REGNAME(apmixed, 0x620, MFGPLL_CON2),
183 REGNAME(apmixed, 0x624, MFGPLL_CON3),
184 REGNAME(apmixed, 0x628, MFGPLL_CON4),
185 REGNAME(apmixed, 0x454, APLL1_CON0),
186 REGNAME(apmixed, 0x458, APLL1_CON1),
187 REGNAME(apmixed, 0x45c, APLL1_CON2),
188 REGNAME(apmixed, 0x460, APLL1_CON3),
189 REGNAME(apmixed, 0x464, APLL1_CON4),
190 REGNAME(apmixed, 0x468, APLL1_CON5),
191 REGNAME(apmixed, 0x46c, APLL2_CON0),
192 REGNAME(apmixed, 0x470, APLL2_CON1),
193 REGNAME(apmixed, 0x474, APLL2_CON2),
194 REGNAME(apmixed, 0x478, APLL2_CON3),
195 REGNAME(apmixed, 0x47c, APLL2_CON4),
196 REGNAME(apmixed, 0x480, APLL2_CON5),
197 REGNAME(apmixed, 0x804, NET1PLL_CON0),
198 REGNAME(apmixed, 0x808, NET1PLL_CON1),
199 REGNAME(apmixed, 0x80c, NET1PLL_CON2),
200 REGNAME(apmixed, 0x810, NET1PLL_CON3),
201 REGNAME(apmixed, 0x814, NET1PLL_CON4),
202 REGNAME(apmixed, 0x818, NET2PLL_CON0),
203 REGNAME(apmixed, 0x81c, NET2PLL_CON1),
204 REGNAME(apmixed, 0x820, NET2PLL_CON2),
205 REGNAME(apmixed, 0x824, NET2PLL_CON3),
206 REGNAME(apmixed, 0x828, NET2PLL_CON4),
207 REGNAME(apmixed, 0x82c, WEDMCUPLL_CON0),
208 REGNAME(apmixed, 0x830, WEDMCUPLL_CON1),
209 REGNAME(apmixed, 0x834, WEDMCUPLL_CON2),
210 REGNAME(apmixed, 0x838, WEDMCUPLL_CON3),
211 REGNAME(apmixed, 0x83c, WEDMCUPLL_CON4),
212 REGNAME(apmixed, 0x840, MEDMCUPLL_CON0),
213 REGNAME(apmixed, 0x844, MEDMCUPLL_CON1),
214 REGNAME(apmixed, 0x848, MEDMCUPLL_CON2),
215 REGNAME(apmixed, 0x84c, MEDMCUPLL_CON3),
216 REGNAME(apmixed, 0x850, MEDMCUPLL_CON4),
217 REGNAME(apmixed, 0x240, SGMIIPLL_CON0),
218 REGNAME(apmixed, 0x244, SGMIIPLL_CON1),
219 REGNAME(apmixed, 0x248, SGMIIPLL_CON2),
220 REGNAME(apmixed, 0x24c, SGMIIPLL_CON3),
221 REGNAME(apmixed, 0x250, SGMIIPLL_CON4),
222 /* GCE register */
223 REGNAME(gce, 0xf0, GCE_CTL_INT0),
224 /* AUDIO register */
225 REGNAME(audsys, 0x0, AUDIO_TOP_0),
226 REGNAME(audsys, 0x4, AUDIO_TOP_1),
227 REGNAME(audsys, 0x8, AUDIO_TOP_2),
228 /* IMP_IIC_WRAP_E register */
229 REGNAME(impe, 0xe00, AP_CLOCK_CG_RO_EST),
230 /* MFGCFG register */
231 REGNAME(mfgcfg, 0x0, MFG_CG),
232 /* MMSYS CONFIG register */
233 REGNAME(mm, 0x100, MMSYS_CG_CON0),
234 REGNAME(mm, 0x110, MMSYS_CG_CON1),
235 REGNAME(mm, 0x120, MMSYS_CG_CON2),
236 {},
237};
238
239/*
240 * clkdbg vf table
241 */
242
243struct mtk_vf {
244 const char *name;
245 int freq_table[4];
246};
247
248#define MTK_VF_TABLE(_n, _freq0, _freq1, _freq2, _freq3) { \
249 .name = _n, \
250 .freq_table = {_freq0, _freq1, _freq2, _freq3}, \
251 }
252
253/*
254 * Opp0 : 0p75v
255 * Opp1 : 0p65v
256 * Opp2 : 0p60v
257 * Opp3 : 0p55v
258 *//*
259static struct mtk_vf vf_table[] = {
260 // Opp0, Opp1, Opp2, Opp3
261 MTK_VF_TABLE("axi_sel", 156000, 156000, 156000, 136500),
262 MTK_VF_TABLE("spm_sel", 78000, 78000, 78000, 78000),
263 MTK_VF_TABLE("bus_aximem_sel", 218400, 156000,156000, 156000),
264 MTK_VF_TABLE("mm_sel", 208000, 178285, 178285, 178285),
265 MTK_VF_TABLE("mfg_ref_sel", 416000, 416000, 218400, 218400),
266 MTK_VF_TABLE("uart_sel", 52000, 52000, 52000, 52000),
267 MTK_VF_TABLE("msdc50_0_hclk_sel", 273000, 273000, 273000, 273000),
268 MTK_VF_TABLE("msdc50_0_sel", 416000, 416000, 416000, 416000),
269 MTK_VF_TABLE("msdc30_1_sel", 208000, 208000, 208000, 208000),
270 MTK_VF_TABLE("audio_sel", 54600, 54600, 54600, 54600),
271 MTK_VF_TABLE("aud_intbus_sel", 136500, 136500, 136500, 136500),
272 MTK_VF_TABLE("aud_engen1_sel", 22579, 22579, 22579, 22579),
273 MTK_VF_TABLE("aud_engen2_sel", 24576, 24576,24576, 24576),
274 MTK_VF_TABLE("aud_1_sel", 180633, 180633, 180633, 180633),
275 MTK_VF_TABLE("aud_2_sel", 196608, 196608, 196608, 196608),
276 MTK_VF_TABLE("pwrap_ulposc_sel", 65000, 65000, 65000, 65000),
277 MTK_VF_TABLE("atb_sel", 273000, 273000, 273000, 273000),
278 MTK_VF_TABLE("pwrmcu_sel", 364000, 312000, 312000, 273000),
279 MTK_VF_TABLE("dbi_sel", 124800, 124800, 124800, 124800),
280 MTK_VF_TABLE("disp_pwm_sel", 130000, 130000, 130000, 130000),
281 MTK_VF_TABLE("usb_top_sel", 124800, 124800, 124800, 124800),
282 MTK_VF_TABLE("ssusb_xhci_sel", 124800, 124800, 124800, 124800),
283 MTK_VF_TABLE("i2c_sel", 124800, 124800, 124800, 124800),
284 MTK_VF_TABLE("tl_sel", 136500, 136500, 136500, 136500),
285 MTK_VF_TABLE("dpmaif_main_sel", 364000, 364000, 364000, 273000),
286 MTK_VF_TABLE("pwm_sel", 78000, 78000, 78000, 78000),
287 MTK_VF_TABLE("spmi_m_mst_sel", 32500, 32500, 32500, 32500),
288 MTK_VF_TABLE("spmi_p_mst_sel", 32500, 32500, 32500, 32500),
289 MTK_VF_TABLE("dvfsrc_sel", 26000, 26000, 26000, 26000),
290 MTK_VF_TABLE("mcupm_sel", 182000, 182000, 182000, 182000),
291 MTK_VF_TABLE("sflash_sel", 62400, 62400, 62400, 62400),
292 MTK_VF_TABLE("gcpu_sel", 416000, 364000, 364000, 273000),
293 MTK_VF_TABLE("spi_sel", 208000, 208000, 208000, 178285),
294 MTK_VF_TABLE("spis_sel", 416000, 416000, 312000, 104000),
295 MTK_VF_TABLE("ecc_sel", 312000, 242666, 242666, 136500),
296 MTK_VF_TABLE("nfi1x_sel", 182000, 182000, 182000, 182000),
297 MTK_VF_TABLE("spinfi_bclk_sel", 124800, 124800, 124800, 124800),
298 MTK_VF_TABLE("netsys_sel", 78000, 356571, 242666, 156000),
299 MTK_VF_TABLE("medsys_sel", 78000, 356571, 242666, 156000),
300 MTK_VF_TABLE("hsm_crypto_sel", 312000, 312000, 26000, 26000),
301 MTK_VF_TABLE("hsm_arc_sel", 26000, 26000, 182000, 182000),
302 MTK_VF_TABLE("eip97_sel", 800000, 546000, 364000, 218400),
303 MTK_VF_TABLE("snps_eth_312p5m_sel", 312500, 312500, 312500, 312500),
304 MTK_VF_TABLE("snps_eth_250m_sel", 250000, 250000, 250000, 250000),
305 MTK_VF_TABLE("snps_eth_62p4m_ptp_sel", 62400, 62400, 62400, 62400),
306 MTK_VF_TABLE("snps_eth_50m_rmii_sel", 50000, 50000, 50000, 50000),
307 MTK_VF_TABLE("netsys_500m_sel", 500000, 500000, 500000, 500000),
308 MTK_VF_TABLE("netsys_med_mcu_sel", 580000, 356571, 273000, 104000),
309 MTK_VF_TABLE("netsys_wed_mcu_sel", 760000, 436800, 364000, 182000),
310 MTK_VF_TABLE("netsys_2x_sel", 800000, 546000, 273000, 124800),
311 MTK_VF_TABLE("sgmii_sel", 325000, 325000, 325000, 325000),
312 MTK_VF_TABLE("sgmii_sbus_sel", 78000, 78000,78000, 78000),
313};*/
314
315/*
316 * clkdbg fmeter
317 */
318
319#define clk_readl(addr) readl(addr)
320#define clk_writel(addr, val) \
321 do { writel(val, addr); wmb(); } while (0) /* sync write */
322
323#define FMCLK2(_t, _i, _n, _o, _p) { .type = _t, \
324 .id = _i, .name = _n, .ofs = _o, .pdn = _p}
325#define FMCLK(_t, _i, _n) { .type = _t, .id = _i, .name = _n }
326
327static const struct fmeter_clk fclks[] = {
328 /* CKGEN Part */
329 FMCLK2(CKGEN, FM_AXI_CK, "fm_axi_ck", 0x0010, 7),
330 FMCLK2(CKGEN, FM_SPM_CK, "fm_spm_ck", 0x0010, 15),
331 FMCLK2(CKGEN, FM_BUS_CK, "fm_bus_ck", 0x0010, 23),
332 FMCLK2(CKGEN, FM_MM_CK, "fm_mm_ck", 0x0010, 31),
333 FMCLK2(CKGEN, FM_MFG_REF_CK, "fm_mfg_ref_ck", 0x0020, 7),
334 FMCLK2(CKGEN, FM_FUART_CK, "fm_fuart_ck", 0x0020, 15),
335 FMCLK2(CKGEN, FM_MSDC50_0_H_CK, "fm_msdc50_0_h_ck", 0x0020, 23),
336 FMCLK2(CKGEN, FM_MSDC50_0_CK, "fm_msdc50_0_ck", 0x0020, 31),
337 FMCLK2(CKGEN, FM_MSDC30_1_CK, "fm_msdc30_1_ck", 0x0030, 7),
338 FMCLK2(CKGEN, FM_AUDIO_CK, "fm_audio_ck", 0x0030, 15),
339 FMCLK2(CKGEN, FM_AUD_INTBUS_CK, "fm_aud_intbus_ck", 0x0030, 23),
340 FMCLK2(CKGEN, FM_AUD_ENGEN1_CK, "fm_aud_engen1_ck", 0x0030, 31),
341 FMCLK2(CKGEN, FM_AUD_ENGEN2_CK, "fm_aud_engen2_ck", 0x0040, 7),
342 FMCLK2(CKGEN, FM_AUD1_CK, "fm_aud1_ck", 0x0040, 15),
343 FMCLK2(CKGEN, FM_AUD2_CK, "fm_aud2_ck", 0x0040, 23),
344 FMCLK2(CKGEN, FM_FPWRAP_ULPOSC_CK, "fm_fpwrap_ulposc_ck", 0x0040, 31),
345 FMCLK2(CKGEN, FM_ATB_CK, "fm_atb_ck", 0x0050, 7),
346 FMCLK2(CKGEN, FM_PWRMCU_CK, "fm_pwrmcu_ck", 0x0050, 15),
347 FMCLK2(CKGEN, FM_DBI_CK, "fm_dbi_ck", 0x0050, 23),
348 FMCLK2(CKGEN, FM_FDISP_PWM_CK, "fm_fdisp_pwm_ck", 0x0050, 31),
349 FMCLK2(CKGEN, FM_FUSB_CK, "fm_fusb_ck", 0x0060, 7),
350 FMCLK2(CKGEN, FM_FSSUSB_XHCI_CK, "fm_fssusb_xhci_ck", 0x0060, 15),
351 FMCLK2(CKGEN, FM_I2C_CK, "fm_i2c_ck", 0x0060, 23),
352 FMCLK2(CKGEN, FM_TL_CK, "fm_tl_ck", 0x0060, 31),
353 FMCLK2(CKGEN, FM_DPMAIF_MAIN_CK, "fm_dpmaif_main_ck", 0x0070, 7),
354 FMCLK2(CKGEN, FM_PWM_CK, "fm_pwm_ck", 0x0070, 15),
355 FMCLK2(CKGEN, FM_SPMI_M_MST_CK, "fm_spmi_m_mst_ck", 0x0070, 23),
356 FMCLK2(CKGEN, FM_SPMI_P_MST_CK, "fm_spmi_p_mst_ck", 0x0070, 31),
357 FMCLK2(CKGEN, FM_DVFSRC_CK, "fm_dvfsrc_ck", 0x0080, 7),
358 FMCLK2(CKGEN, FM_MCUPM_CK, "fm_mcupm_ck", 0x0080, 15),
359 FMCLK2(CKGEN, FM_SFLASH_CK, "fm_sflash_ck", 0x0080, 23),
360 FMCLK2(CKGEN, FM_GCPU_CK, "fm_gcpu_ck", 0x0080, 31),
361 FMCLK2(CKGEN, FM_SPI_CK, "fm_spi_ck", 0x0090, 7),
362 FMCLK2(CKGEN, FM_SPIS_CK, "fm_spis_ck", 0x0090, 15),
363 FMCLK2(CKGEN, FM_ECC_CK, "fm_ecc_ck", 0x0090, 23),
364 FMCLK2(CKGEN, FM_NFI1X_CK, "fm_nfi1x_ck", 0x0090, 31),
365 FMCLK2(CKGEN, FM_SPINFI_BCLK_CK, "fm_spinfi_bclk_ck", 0x00A0, 7),
366 FMCLK2(CKGEN, FM_NETSYS_CK, "fm_netsys_ck", 0x00A0, 15),
367 FMCLK2(CKGEN, FM_MEDSYS_CK, "fm_medsys_ck", 0x00A0, 23),
368 FMCLK2(CKGEN, FM_HSM_CRYPTO_CK, "fm_hsm_crypto_ck", 0x00A0, 31),
369 FMCLK2(CKGEN, FM_HSM_ARC_CK, "fm_hsm_arc_ck", 0x00B0, 7),
370 FMCLK2(CKGEN, FM_EIP97_CK, "fm_eip97_ck", 0x00B0, 15),
371 FMCLK2(CKGEN, FM_SNPS_ETH_312P5M_CK, "fm_snps_eth_312p5m_ck", 0x00B0, 23),
372 FMCLK2(CKGEN, FM_SNPS_ETH_250M_CK, "fm_snps_eth_250m_ck", 0x00B0, 31),
373 FMCLK2(CKGEN, FM_SNPS_PTP_CK, "fm_snps_ptp_ck", 0x00C0, 7),
374 FMCLK2(CKGEN, FM_SNPS_ETH_50M_RMII_CK, "fm_snps_eth_50m_rmii_ck", 0x00C0, 15),
375 FMCLK2(CKGEN, FM_NETSYS_500M_CK, "fm_netsys_500m_ck", 0x00C0, 23),
376 FMCLK2(CKGEN, FM_NETSYS_MED_MCU_CK, "fm_netsys_med_mcu_ck", 0x00C0, 31),
377 FMCLK2(CKGEN, FM_NETSYS_WED_MCU_CK, "fm_netsys_wed_mcu_ck", 0x00D0, 7),
378 FMCLK2(CKGEN, FM_NETSYS_2X_CK, "fm_netsys_2x_ck", 0x00D0, 15),
379 FMCLK2(CKGEN, FM_SGMII_CK, "fm_sgmii_ck", 0x00D0, 23),
380 FMCLK2(CKGEN, FM_SGMII_SBUS_CK, "fm_sgmii_sbus_ck", 0x00D0, 31),
381 /* ABIST Part */
382 FMCLK(ABIST, FM_APLL1_CK, "fm_apll1_ck"),
383 FMCLK(ABIST, FM_APLL2_CK, "fm_apll2_ck"),
384 FMCLK(ABIST, FM_APPLLGP_MON_FM_CK, "fm_appllgp_mon_fm_ck"),
385 FMCLK(ABIST, FM_ARMPLL_LL_CK, "fm_armpll_ll_ck"),
386 FMCLK(ABIST, FM_CCIPLL_CK, "fm_ccipll_ck"),
387 FMCLK(ABIST, FM_NET1PLL_CK, "fm_net1pll_ck"),
388 FMCLK(ABIST, FM_NET2PLL_CK, "fm_net2pll_ck"),
389 FMCLK(ABIST, FM_WEDMCUPLL_CK, "fm_wedmcupll_ck"),
390 FMCLK(ABIST, FM_MEDMCUPLL_CK, "fm_medmcupll_ck"),
391 FMCLK(ABIST, FM_SGMIIPLL_CK, "fm_sgmiipll_ck"),
392 FMCLK(ABIST, FM_SNPSETHPLL_CK, "fm_snpsethpll_ck"),
393 FMCLK(ABIST, FM_DSI0_LNTC_DSICLK, "fm_dsi0_lntc_dsiclk"),
394 FMCLK(ABIST, FM_DSI0_MPPLL_TST_CK, "fm_dsi0_mppll_tst_ck"),
395 FMCLK(ABIST, FM_MDPLL1_FS26M_DRF_GUIDE, "fm_mdpll1_fs26m_drf_guide"),
396 FMCLK(ABIST, FM_MFG_CK, "fm_mfg_ck"),
397 FMCLK(ABIST, FM_MAINPLL_CK, "fm_mainpll_ck"),
398 FMCLK(ABIST, FM_MDPLL1_FS26M_GUIDE, "fm_mdpll1_fs26m_guide"),
399 FMCLK(ABIST, FM_MFGPLL_CK, "fm_mfgpll_ck"),
400 FMCLK(ABIST, FM_MMPLL_CK, "fm_mmpll_ck"),
401 FMCLK(ABIST, FM_MMPLL_D3_CK, "fm_mmpll_d3_ck"),
402 FMCLK(ABIST, FM_MPLL_CK, "fm_mpll_ck"),
403 FMCLK(ABIST, FM_MSDCPLL_CK, "fm_msdcpll_ck"),
404 FMCLK(ABIST, FM_RCLRPLL_DIV4_CK, "fm_rclrpll_div4_ck"),
405 FMCLK(ABIST, FM_RPHYPLL_DIV4_CK, "fm_rphypll_div4_ck"),
406 FMCLK(ABIST, FM_ULPOSC_CK, "fm_ulposc_ck"),
407 FMCLK(ABIST, FM_UNIVPLL_CK, "fm_univpll_ck"),
408 FMCLK(ABIST, FMEM_AFT_CH0, "fmem_aft_ch0"),
409 FMCLK(ABIST, FMEM_AFT_CH1, "fmem_aft_ch1"),
410 FMCLK(ABIST, FM_TRNG_FREQ_DEBUG_OUT0, "fm_trng_freq_debug_out0"),
411 FMCLK(ABIST, FM_TRNG_FREQ_DEBUG_OUT1, "fm_trng_freq_debug_out1"),
412 FMCLK(ABIST, FMEM_BFE_CH0, "fmem_bfe_ch0"),
413 FMCLK(ABIST, FMEM_BFE_CH1, "fmem_bfe_ch1"),
414 FMCLK(ABIST, FM_466M_FMEM_INFRASYS, "fm_466m_fmem_infrasys"),
415 FMCLK(ABIST, FM_MCUSYS_ARM_OUT_ALL, "fm_mcusys_arm_out_all"),
416 FMCLK(ABIST, FM_RTC32K_I_VAO, "fm_rtc32k_i_vao"),
417 /* ABIST_2 Part */
418 FMCLK(ABIST_2, FM_MCUPM_CK, "fm_mcupm_ck"),
419 FMCLK(ABIST_2, FM_SFLASH_CK, "fm_sflash_ck"),
420 FMCLK(ABIST_2, FM_UNIPLL_SES_CK, "fm_unipll_ses_ck"),
421 FMCLK(ABIST_2, FM_ULPOSC_CK, "fm_ulposc_ck"),
422 FMCLK(ABIST_2, FM_ULPOSC_CORE_CK, "fm_ulposc_core_ck"),
423 FMCLK(ABIST_2, FM_SRCK_CK, "fm_srck_ck"),
424 FMCLK(ABIST_2, FM_MAINPLL_H728M_CK, "fm_mainpll_h728m_ck"),
425 FMCLK(ABIST_2, FM_MAINPLL_H546M_CK, "fm_mainpll_h546m_ck"),
426 FMCLK(ABIST_2, FM_MAINPLL_H436P8M_CK, "fm_mainpll_h436p8m_ck"),
427 FMCLK(ABIST_2, FM_MAINPLL_H364M_CK, "fm_mainpll_h364m_ck"),
428 FMCLK(ABIST_2, FM_MAINPLL_H312M_CK, "fm_mainpll_h312m_ck"),
429 FMCLK(ABIST_2, FM_UNIVPLL_1248M_CK, "fm_univpll_1248m_ck"),
430 FMCLK(ABIST_2, FM_UNIVPLL_832M_CK, "fm_univpll_832m_ck"),
431 FMCLK(ABIST_2, FM_UNIVPLL_624M_CK, "fm_univpll_624m_ck"),
432 FMCLK(ABIST_2, FM_UNIVPLL_499M_CK, "fm_univpll_499m_ck"),
433 FMCLK(ABIST_2, FM_UNIVPLL_416M_CK, "fm_univpll_416m_ck"),
434 FMCLK(ABIST_2, FM_UNIVPLL_356P6M_CK, "fm_univpll_356p6m_ck"),
435 FMCLK(ABIST_2, FM_MMPLL_D3_CK, "fm_mmpll_d3_ck"),
436 FMCLK(ABIST_2, FM_MMPLL_D4_CK, "fm_mmpll_d4_ck"),
437 FMCLK(ABIST_2, FM_MMPLL_D5_CK, "fm_mmpll_d5_ck"),
438 FMCLK(ABIST_2, FM_MMPLL_D6_CK, "fm_mmpll_d6_ck"),
439 FMCLK(ABIST_2, FM_MMPLL_D7_CK, "fm_mmpll_d7_ck"),
440 FMCLK(ABIST_2, FM_MMPLL_D9_CK, "fm_mmpll_d9_ck"),
441 FMCLK(ABIST_2, FM_NET1PLL_CK, "fm_net1pll_ck"),
442 FMCLK(ABIST_2, FM_NET2PLL_CK, "fm_net2pll_ck"),
443 FMCLK(ABIST_2, FM_WEDMCUPLL_CK, "fm_wedmcupll_ck"),
444 FMCLK(ABIST_2, FM_MEDMCUPLL_CK, "fm_medmcupll_ck"),
445 FMCLK(ABIST_2, FM_SGMIIPLL_CK, "fm_sgmiipll_ck"),
446 {},
447};
448
449#define _CKGEN(x) (rb[top].virt + (x))
450#define CLK_CFG_0 _CKGEN(0x10)
451#define CLK_CFG_1 _CKGEN(0x20)
452#define CLK_CFG_2 _CKGEN(0x30)
453#define CLK_CFG_3 _CKGEN(0x40)
454#define CLK_CFG_4 _CKGEN(0x50)
455#define CLK_CFG_5 _CKGEN(0x60)
456#define CLK_CFG_6 _CKGEN(0x70)
457#define CLK_CFG_7 _CKGEN(0x80)
458#define CLK_CFG_8 _CKGEN(0x90)
459#define CLK_CFG_9 _CKGEN(0xA0)
460#define CLK_CFG_10 _CKGEN(0xB0)
461#define CLK_CFG_11 _CKGEN(0xC0)
462#define CLK_CFG_12 _CKGEN(0xD0)
463//#define CLK_CFG_13 _CKGEN(0xE0)
464#define CLK_MISC_CFG_0 _CKGEN(0x140)
465#define CLK_DBG_CFG _CKGEN(0x17C)
466#define CLK26CALI_0 _CKGEN(0x220)
467#define CLK26CALI_1 _CKGEN(0x224)
468
469/*
470 * clkdbg dump_clks
471 */
472
473 static const char * const *get_pwr_names(void)
474{
475 static const char * const pwr_names[] = {
476 [0] = "md1",
477 [1] = "conn",
478 [2] = "mfg0",
479 [3] = "pextp_d_2lx1_phy",
480 [4] = "pextp_r_2lx1_phy",
481 [5] = "pextp_r_1lx2_0p_phy",
482 [6] = "pextp_r_1lx2_1p_phy",
483 [7] = "ssusb_phy",
484 [8] = "sgmii_0_phy",
485 [9] = "infra",
486 [10] = "sgmii_1_phy",
487 [11] = "dpy",
488 [12] = "pextp_d_2lx1",
489 [13] = "pextp_r_2lx1",
490 [14] = "pextp_r_1lx2",
491 [15] = "eth",
492 [16] = "ssusb",
493 [17] = "sgmii_0_top",
494 [18] = "sgmii_1_top",
495 [19] = "netsys",
496 [20] = "dis",
497 [21] = "audio",
498 [22] = "eip97",
499 [23] = "hsmtop",
500 [24] = "dramc_md32",
501 [25] = "(Reserved)",
502 [26] = "(Reserved)",
503 [27] = "(Reserved)",
504 [28] = "dpy2",
505 [29] = "mcupm",
506 [30] = "msdc",
507 [31] = "peri",
508 };
509 return pwr_names;
510}
511
512 static const char * const *get_all_clk_names(void)
513{
514 return get_mt6880_all_clk_names();
515}
516
517 static const struct regname *get_all_regnames(void)
518{
519 return rn;
520}
521
522static void __init init_regbase(void)
523{
524 int i;
525 for (i = 0; i < ARRAY_SIZE(rb); i++) {
526 if (!rb[i].phys)
527 continue;
528 rb[i].virt = ioremap_nocache(rb[i].phys, 0x1000);
529 }
530}
531
532unsigned int mt_get_abist_freq(unsigned int ID)
533{
534 int output = 0, i = 0;
535 unsigned long flags;
536 unsigned int temp, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1 = 0;
537 fmeter_lock(flags);
538 while (clk_readl(CLK26CALI_0) & 0x1000) {
539 udelay(10);
540 i++;
541 if (i > 30)
542 break;
543 }
544 ;
545 clk_dbg_cfg = clk_readl(CLK_DBG_CFG);
546 clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xFFC0FFFC)|(ID << 16));
547 clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0);
548 clk_writel(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF) | (3 << 24));
549 clk26cali_1 = clk_readl(CLK26CALI_1);
550 clk_writel(CLK26CALI_0, 0x1000);
551 clk_writel(CLK26CALI_0, 0x1010);
552 /* wait frequency meter finish */
553 while (clk_readl(CLK26CALI_0) & 0x10) {
554 udelay(10);
555 i++;
556 if (i > 30)
557 break;
558 }
559 /* illegal pass */
560 if (i == 0) {
561 clk_writel(CLK26CALI_0, 0x0000);
562 //re-trigger
563 clk_writel(CLK26CALI_0, 0x1000);
564 clk_writel(CLK26CALI_0, 0x1010);
565 while (clk_readl(CLK26CALI_0) & 0x10) {
566 udelay(10);
567 i++;
568 if (i > 30)
569 break;
570 }
571 }
572 temp = clk_readl(CLK26CALI_1) & 0xFFFF;
573 output = (temp * 26000) / 1024;
574 clk_writel(CLK_DBG_CFG, clk_dbg_cfg);
575 clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0);
576 /*clk_writel(CLK26CALI_0, clk26cali_0);*/
577 /*clk_writel(CLK26CALI_1, clk26cali_1);*/
578 clk_writel(CLK26CALI_0, 0x0000);
579 fmeter_unlock(flags);
580 if (i > 30)
581 return 0;
582 else {
583 if ((output * 4) < 25000) {
584 pr_notice("%s: CLK_DBG_CFG = 0x%x, CLK_MISC_CFG_0 = 0x%x, CLK26CALI_0 = 0x%x, CLK26CALI_1 = 0x%x\n",
585 __func__,
586 clk_readl(CLK_DBG_CFG),
587 clk_readl(CLK_MISC_CFG_0),
588 clk_readl(CLK26CALI_0),
589 clk_readl(CLK26CALI_1));
590 }
591 return (output * 4);
592 }
593}
594
595static unsigned int mt_get_abist2_freq(unsigned int ID)
596{
597 int output = 0, i = 0;
598 unsigned long flags;
599 unsigned int temp, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1 = 0;
600 fmeter_lock(flags);
601 while (clk_readl(CLK26CALI_0) & 0x1000) {
602 udelay(10);
603 i++;
604 if (i > 30)
605 break;
606 }
607 ;
608 clk_dbg_cfg = clk_readl(CLK_DBG_CFG);
609 clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xC0FFFFFC)
610 | (ID << 24) | (0x2));
611 clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0);
612 clk_writel(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF) | (1 << 24));
613 clk26cali_1 = clk_readl(CLK26CALI_1);
614 clk_writel(CLK26CALI_0, 0x1000);
615 clk_writel(CLK26CALI_0, 0x1010);
616 // wait frequency meter finish
617 while (clk_readl(CLK26CALI_0) & 0x10) {
618 udelay(10);
619 i++;
620 if (i > 30)
621 break;
622 }
623 // illegal pass
624 if (i == 0) {
625 clk_writel(CLK26CALI_0, 0x0000);
626 //re-trigger
627 clk_writel(CLK26CALI_0, 0x1000);
628 clk_writel(CLK26CALI_0, 0x1010);
629 while (clk_readl(CLK26CALI_0) & 0x10) {
630 udelay(10);
631 i++;
632 if (i > 30)
633 break;
634 }
635 }
636 temp = clk_readl(CLK26CALI_1) & 0xFFFF;
637 output = (temp * 26000) / 1024;
638 clk_writel(CLK_DBG_CFG, clk_dbg_cfg);
639 clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0);
640 //clk_writel(CLK26CALI_0, clk26cali_0);
641 //clk_writel(CLK26CALI_1, clk26cali_1);
642 clk_writel(CLK26CALI_0, 0x0000);
643 //pr_debug("%s = %d Khz\n", abist_array[ID-1], output);
644 fmeter_unlock(flags);
645 if (i > 30)
646 return 0;
647 else
648 return (output * 2);
649}
650
651static unsigned int check_mux_pdn(unsigned int ID)
652{
653 int i;
654 if ((ID > 0) && (ID < 64)) {
655 for (i = 0; i < ARRAY_SIZE(fclks); i++)
656 if (fclks[i].id == ID)
657 break;
658 if (i >= ARRAY_SIZE(fclks))
659 return 1;
660 if ((clk_readl(rb[top].virt + fclks[i].ofs)
661 & BIT(fclks[i].pdn)))
662 return 1;
663 else
664 return 0;
665 } else
666 return 1;
667}
668
669unsigned int mt_get_ckgen_freq(unsigned int ID)
670{
671 int output = 0, i = 0;
672 unsigned int temp, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1 = 0;
673 unsigned long flags;
674 if (check_mux_pdn(ID)) {
675 pr_notice("ID-%d: MUX PDN, return 0.\n", ID);
676 return 0;
677 }
678 fmeter_lock(flags);
679 while (clk_readl(CLK26CALI_0) & 0x1000) {
680 udelay(10);
681 i++;
682 if (i > 30)
683 break;
684 }
685 clk_dbg_cfg = clk_readl(CLK_DBG_CFG);
686 clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xFFFFC0FC)|(ID << 8)|(0x1));
687 clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0);
688 clk_writel(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF) | (3 << 24));
689 clk26cali_1 = clk_readl(CLK26CALI_1);
690 clk_writel(CLK26CALI_0, 0x1000);
691 clk_writel(CLK26CALI_0, 0x1010);
692 /* wait frequency meter finish */
693 while (clk_readl(CLK26CALI_0) & 0x10) {
694 udelay(10);
695 i++;
696 if (i > 30)
697 break;
698 }
699 /* illegal pass */
700 if (i == 0) {
701 clk_writel(CLK26CALI_0, 0x0000);
702 //re-trigger
703 clk_writel(CLK26CALI_0, 0x1000);
704 clk_writel(CLK26CALI_0, 0x1010);
705 while (clk_readl(CLK26CALI_0) & 0x10) {
706 udelay(10);
707 i++;
708 if (i > 30)
709 break;
710 }
711 }
712 temp = clk_readl(CLK26CALI_1) & 0xFFFF;
713 output = (temp * 26000) / 1024;
714 clk_writel(CLK_DBG_CFG, clk_dbg_cfg);
715 clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0);
716 /*clk_writel(CLK26CALI_0, clk26cali_0);*/
717 /*clk_writel(CLK26CALI_1, clk26cali_1);*/
718 clk_writel(CLK26CALI_0, 0x0000);
719 fmeter_unlock(flags);
720 /*print("ckgen meter[%d] = %d Khz\n", ID, output);*/
721 if (i > 30)
722 return 0;
723 else {
724 if ((output * 4) < 25000) {
725 pr_notice("%s: CLK_DBG_CFG = 0x%x, CLK_MISC_CFG_0 = 0x%x, CLK26CALI_0 = 0x%x, CLK26CALI_1 = 0x%x\n",
726 __func__,
727 clk_readl(CLK_DBG_CFG),
728 clk_readl(CLK_MISC_CFG_0),
729 clk_readl(CLK26CALI_0),
730 clk_readl(CLK26CALI_1));
731 }
732 return (output * 4);
733 }
734}
735
736 static u32 fmeter_freq_op(const struct fmeter_clk *fclk)
737{
738 if (fclk->type == ABIST)
739 return mt_get_abist_freq(fclk->id);
740 else if (fclk->type == ABIST_2)
741 return mt_get_abist2_freq(fclk->id);
742 else if (fclk->type == CKGEN)
743 return mt_get_ckgen_freq(fclk->id);
744 return 0;
745}
746
747static const struct fmeter_clk *get_all_fmeter_clks(void)
748{
749 return fclks;
750}
751
752void setup_provider_clk(struct provider_clk *pvdck)
753{
754 static const struct {
755 const char *pvdname;
756 u32 pwr_mask;
757 } pvd_pwr_mask[] = {
758 };
759
760 int i;
761 const char *pvdname = pvdck->provider_name;
762
763 if (!pvdname)
764 return;
765
766 for (i = 0; i < ARRAY_SIZE(pvd_pwr_mask); i++) {
767 if (strcmp(pvdname, pvd_pwr_mask[i].pvdname) == 0) {
768 pvdck->pwr_mask = pvd_pwr_mask[i].pwr_mask;
769 return;
770 }
771 }
772}
773
774/*
775 * chip_ver functions
776 */
777/*
778static int clkdbg_chip_ver(struct seq_file *s, void *v)
779{
780 static const char * const sw_ver_name[] = {
781 "CHIP_SW_VER_01",
782 "CHIP_SW_VER_02",
783 "CHIP_SW_VER_03",
784 "CHIP_SW_VER_04",
785 };
786
787 seq_printf(s, "mt_get_chip_sw_ver(): %d (%s)\n", 0, sw_ver_name[0]);
788
789 return 0;
790}*/
791
792/*
793 * init functions
794 */
795
796static struct clkdbg_ops clkdbg_mt6880_ops = {
797 .get_all_fmeter_clks = get_all_fmeter_clks,
798 .prepare_fmeter = NULL,
799 .unprepare_fmeter = NULL,
800 .fmeter_freq = fmeter_freq_op,
801 .get_all_regnames = get_all_regnames,
802 .get_all_clk_names = get_all_clk_names,
803 .get_pwr_names = get_pwr_names,
804 .setup_provider_clk = setup_provider_clk,
805};
806
807static void __init init_custom_cmds(void)
808{
809 /*static const struct cmd_fn cmds[] = {
810 CMDFN("chip_ver", clkdbg_chip_ver),
811 {}
812 };
813
814 set_custom_cmds(cmds);*/
815}
816
817static int __init clkdbg_mt6880_init(void)
818{
819/* if (!of_machine_is_compatible("mediatek,MT6880"))
820 return -ENODEV;
821*/
822 init_regbase();
823
824 init_custom_cmds();
825 set_clkdbg_ops(&clkdbg_mt6880_ops);
826
827#ifdef CONFIG_MTK_DEVAPC
828// register_devapc_vio_callback(&devapc_vio_handle);
829#endif
830
831#if DUMP_INIT_STATE
832 print_regs();
833 print_fmeter_all();
834#endif /* DUMP_INIT_STATE */
835
836 return 0;
837}
838subsys_initcall(clkdbg_mt6880_init);
839
840/*
841 * MT6880: for mtcmos debug
842 */
843static bool is_valid_reg(void __iomem *addr)
844{
845#ifdef CONFIG_64BIT
846 return ((u64)addr & 0xf0000000) != 0UL ||
847 (((u64)addr >> 32U) & 0xf0000000) != 0UL;
848#else
849 return ((u32)addr & 0xf0000000) != 0U;
850#endif
851}
852
853void print_subsys_reg(enum dbg_sys_id id)
854{
855 struct regbase *rb_dump;
856 const struct regname *rns = &rn[0];
857 int i;
858 /*if (rns == NULL)
859 return;*/
860 if (id >= dbg_sys_num || id < 0) {
861 pr_info("wrong id:%d\n", id);
862 return;
863 }
864 rb_dump = &rb[id];
865 for (i = 0; i < ARRAY_SIZE(rn) - 1; i++, rns++) {
866 if (!is_valid_reg(ADDR(rns)))
867 return;
868 /* filter out the subsys that we don't want */
869 if (rns->base != rb_dump)
870 continue;
871 pr_info("%-18s: [0x%08x] = 0x%08x\n",
872 rns->name, PHYSADDR(rns), clk_readl(ADDR(rns)));
873 }
874}