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192.168.1.100 / T800 / 0b39b87cb0cd96fd68f16a6d004c85c06a954fb2 / . / src / kernel / linux / v4.19 / drivers / clk / mediatek / clkdbg-mt8168.c
blob: 2d142a783e58c1c37de3df7df0fc687ed2e3b72d [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 MediaTek Inc.
4 */
5
6#include <linux/clk-provider.h>
7#include <linux/io.h>
8
9#include "clkdbg.h"
10
11#define DUMP_INIT_STATE 0
12#define DEFAULT_CYCLE_COUNT 0x1FF
13/*
14 * clkdbg dump_regs
15 */
16
17enum {
18 topckgen,
19 infracfg,
20 scpsys,
21 apmixedsys,
22 audiosys,
23 mfgsys,
24 mmsys,
25 camsys,
26 vdecsys,
27 vencsys,
28};
29
30#define REGBASE_V(_phys, _id_name) { .phys = _phys, .name = #_id_name }
31
32/*
33 * checkpatch.pl ERROR:COMPLEX_MACRO
34 *
35 * #define REGBASE(_phys, _id_name) [_id_name] = REGBASE_V(_phys, _id_name)
36 */
37
38static struct regbase rb[] = {
39 [topckgen] = REGBASE_V(0x10000000, topckgen),
40 [infracfg] = REGBASE_V(0x10001000, infracfg),
41 [scpsys] = REGBASE_V(0x10006000, scpsys),
42 [apmixedsys] = REGBASE_V(0x1000c000, apmixedsys),
43 [audiosys] = REGBASE_V(0x11220000, audiosys),
44 [mfgsys] = REGBASE_V(0x13000000, mfgsys),
45 [mmsys] = REGBASE_V(0x14000000, mmsys),
46 [camsys] = REGBASE_V(0x15000000, camsys),
47 [vdecsys] = REGBASE_V(0x16000000, vdecsys),
48 [vencsys] = REGBASE_V(0x17000000, vencsys),
49};
50
51#define REGNAME(_base, _ofs, _name) \
52 { .base = &rb[_base], .ofs = _ofs, .name = #_name }
53
54static struct regname rn[] = {
55 REGNAME(topckgen, 0x040, CLK_CFG_0),
56 REGNAME(topckgen, 0x050, CLK_CFG_1),
57 REGNAME(topckgen, 0x060, CLK_CFG_2),
58 REGNAME(topckgen, 0x070, CLK_CFG_3),
59 REGNAME(topckgen, 0x080, CLK_CFG_4),
60 REGNAME(topckgen, 0x090, CLK_CFG_5),
61 REGNAME(topckgen, 0x0a0, CLK_CFG_6),
62 REGNAME(topckgen, 0x0b0, CLK_CFG_7),
63 REGNAME(topckgen, 0x0c0, CLK_CFG_8),
64 REGNAME(topckgen, 0x0d0, CLK_CFG_9),
65 REGNAME(topckgen, 0x0e0, CLK_CFG_10),
66 REGNAME(topckgen, 0x0ec, CLK_CFG_11),
67 REGNAME(audiosys, 0x000, AUDIO_TOP_CON0),
68 REGNAME(audiosys, 0x004, AUDIO_TOP_CON1),
69 REGNAME(camsys, 0x000, CAMSYS_CG),
70 REGNAME(infracfg, 0x090, MODULE_SW_CG_0),
71 REGNAME(infracfg, 0x094, MODULE_SW_CG_1),
72 REGNAME(infracfg, 0x0ac, MODULE_SW_CG_2),
73 REGNAME(infracfg, 0x0c8, MODULE_SW_CG_3),
74 REGNAME(infracfg, 0x0d8, MODULE_SW_CG_4),
75 REGNAME(mfgsys, 0x000, MFG_CG),
76 REGNAME(mmsys, 0x100, MMSYS_CG_CON0),
77 REGNAME(mmsys, 0x110, MMSYS_CG_CON1),
78 REGNAME(vencsys, 0x004, VENCSYS_CG),
79 REGNAME(vdecsys, 0x000, VDEC_CKEN),
80 REGNAME(vdecsys, 0x008, VDEC_LARB3_CKEN),
81 REGNAME(apmixedsys, 0x30C, ARMPLL_CON0),
82 REGNAME(apmixedsys, 0x310, ARMPLL_CON1),
83 REGNAME(apmixedsys, 0x318, ARMPLL_PWR_CON0),
84 REGNAME(apmixedsys, 0x228, MAINPLL_CON0),
85 REGNAME(apmixedsys, 0x22C, MAINPLL_CON1),
86 REGNAME(apmixedsys, 0x234, MAINPLL_PWR_CON0),
87 REGNAME(apmixedsys, 0x208, UNIVPLL_CON0),
88 REGNAME(apmixedsys, 0x20C, UNIVPLL_CON1),
89 REGNAME(apmixedsys, 0x214, UNIVPLL_PWR_CON0),
90 REGNAME(apmixedsys, 0x218, MFGPLL_CON0),
91 REGNAME(apmixedsys, 0x21C, MFGPLL_CON1),
92 REGNAME(apmixedsys, 0x224, MFGPLL_PWR_CON0),
93 REGNAME(apmixedsys, 0x350, MSDCPLL_CON0),
94 REGNAME(apmixedsys, 0x354, MSDCPLL_CON1),
95 REGNAME(apmixedsys, 0x35C, MSDCPLL_PWR_CON0),
96 REGNAME(apmixedsys, 0x330, MMPLL_CON0),
97 REGNAME(apmixedsys, 0x334, MMPLL_CON1),
98 REGNAME(apmixedsys, 0x33C, MMPLL_PWR_CON0),
99 REGNAME(apmixedsys, 0x31C, APLL1_CON0),
100 REGNAME(apmixedsys, 0x320, APLL1_CON1),
101 REGNAME(apmixedsys, 0x32C, APLL1_PWR_CON0),
102 REGNAME(apmixedsys, 0x360, APLL2_CON0),
103 REGNAME(apmixedsys, 0x364, APLL2_CON1),
104 REGNAME(apmixedsys, 0x370, APLL2_PWR_CON0),
105 REGNAME(apmixedsys, 0x340, MPLL_CON0),
106 REGNAME(apmixedsys, 0x344, MPLL_CON1),
107 REGNAME(apmixedsys, 0x34C, MPLL_PWR_CON0),
108 REGNAME(apmixedsys, 0x374, LVDSPLL_CON0),
109 REGNAME(apmixedsys, 0x378, LVDSPLL_CON1),
110 REGNAME(apmixedsys, 0x380, LVDSPLL_PWR_CON0),
111 REGNAME(apmixedsys, 0x390, DSPPLL_CON0),
112 REGNAME(apmixedsys, 0x394, DSPPLL_CON1),
113 REGNAME(apmixedsys, 0x39C, DSPPLL_PWR_CON0),
114 REGNAME(apmixedsys, 0x3A0, APUPLL_CON0),
115 REGNAME(apmixedsys, 0x3A4, APUPLL_CON1),
116 REGNAME(apmixedsys, 0x3AC, APUPLL_PWR_CON0),
117 REGNAME(scpsys, 0x0180, PWR_STATUS),
118 REGNAME(scpsys, 0x0184, PWR_STATUS_2ND),
119 REGNAME(scpsys, 0x0338, MFG_PWR_CON),
120 REGNAME(scpsys, 0x032C, CONN_PWR_CON),
121 REGNAME(scpsys, 0x0314, AUD_PWR_CON),
122 REGNAME(scpsys, 0x030C, DIS_PWR_CON),
123 REGNAME(scpsys, 0x0344, CAM_PWR_CON),
124 REGNAME(scpsys, 0x0300, VDEC_PWR_CON),
125 REGNAME(scpsys, 0x0304, VENC_PWR_CON),
126 REGNAME(scpsys, 0x0378, APU_PWR_CON),
127 REGNAME(scpsys, 0x037C, DSP_PWR_CON),
128 {}
129};
130
131static const struct regname *get_all_regnames(void)
132{
133 return rn;
134}
135
136static void __init init_regbase(void)
137{
138 size_t i;
139
140 for (i = 0; i < ARRAY_SIZE(rb); i++)
141 rb[i].virt = ioremap(rb[i].phys, PAGE_SIZE);
142}
143
144/*
145 * clkdbg fmeter
146 */
147
148#include <linux/delay.h>
149
150#define clk_readl(addr) readl(addr)
151#define clk_writel(addr, val) \
152 do { writel(val, addr); wmb(); } while (0) /* sync write */
153
154#define FMCLK(_t, _i, _n) { .type = _t, .id = _i, .name = _n }
155#define CKGEN_K1 0x3
156
157static const struct fmeter_clk fclks[] = {
158 FMCLK(CKGEN, 1, "axi_ck"),
159 FMCLK(CKGEN, 2, "mem_ck"),
160 FMCLK(CKGEN, 3, "mm_ck"),
161 FMCLK(CKGEN, 4, "scp_ck"),
162 FMCLK(CKGEN, 5, "mfg_ck"),
163 FMCLK(CKGEN, 7, "camtg_ck"),
164 FMCLK(CKGEN, 8, "camtg1_ck"),
165 FMCLK(CKGEN, 9, "uart_ck"),
166 FMCLK(CKGEN, 10, "f_fspi_ck"),
167 FMCLK(CKGEN, 11, "msdc50_0_hclk_ck"),
168 FMCLK(CKGEN, 12, "fmsdc2_2_hclk_ck"),
169 FMCLK(CKGEN, 13, "msdc50_0_ck"),
170 FMCLK(CKGEN, 14, "msdc50_2_ck"),
171 FMCLK(CKGEN, 15, "msdc30_1_ck"),
172 FMCLK(CKGEN, 16, "audio_ck"),
173 FMCLK(CKGEN, 17, "aud_intbus_ck"),
174 FMCLK(CKGEN, 18, "aud_1_ck"),
175 FMCLK(CKGEN, 19, "aud_2_ck"),
176 FMCLK(CKGEN, 20, "aud_engen1_ck"),
177 FMCLK(CKGEN, 21, "aud_engen2_ck"),
178 FMCLK(CKGEN, 22, "hf_faud_spdif_ck"),
179 FMCLK(CKGEN, 23, "disp_pwm_ck"),
180 FMCLK(CKGEN, 24, "sspm_ck"),
181 FMCLK(CKGEN, 25, "dxcc_ck"),
182 FMCLK(CKGEN, 26, "ssusb_sys_ck"),
183 FMCLK(CKGEN, 27, "ssusb_xhci_ck"),
184 FMCLK(CKGEN, 28, "spm_ck"),
185 FMCLK(CKGEN, 29, "i2c_ck"),
186 FMCLK(CKGEN, 30, "pwm_ck"),
187 FMCLK(CKGEN, 31, "seninf_ck"),
188 FMCLK(CKGEN, 32, "aes_fde_ck"),
189 FMCLK(CKGEN, 33, "camtm_ck"),
190 FMCLK(CKGEN, 34, "dpi0_ck"),
191 FMCLK(CKGEN, 35, "dpi1_ck"),
192 FMCLK(CKGEN, 36, "dsp_ck"),
193 FMCLK(CKGEN, 37, "nfi2x_ck"),
194 FMCLK(CKGEN, 38, "nfiecc_ck"),
195 FMCLK(CKGEN, 39, "ecc_ck"),
196 FMCLK(CKGEN, 40, "eth_ck"),
197 FMCLK(CKGEN, 41, "gcpu_ck"),
198 FMCLK(CKGEN, 42, "gcpu_cpm_ck"),
199 FMCLK(CKGEN, 43, "apu_ck"),
200 FMCLK(CKGEN, 44, "apu_if_ck"),
201 FMCLK(CKGEN, 45, "mbist_diag_clk"),
202 FMCLK(CKGEN, 48, "f_ufs_mp_sap_cfg_ck"),
203 FMCLK(CKGEN, 49, "f_ufs_tick1us_ck"),
204 FMCLK(CKGEN, 50, "hd_faxi_east_ck"),
205 FMCLK(CKGEN, 51, "hd_faxi_west_ck"),
206 FMCLK(CKGEN, 52, "hd_faxi_north_ck"),
207 FMCLK(CKGEN, 53, "hd_faxi_south_ck"),
208 FMCLK(CKGEN, 54, "hd_fmipicfg_tx_ck"),
209 FMCLK(CKGEN, 55, "fmem_ck_bfe_dcm_ch0"),
210 FMCLK(CKGEN, 56, "fmem_ck_aft_dcm_ch0"),
211 FMCLK(CKGEN, 57, "fmem_ck_bfe_dcm_ch1"),
212 FMCLK(CKGEN, 58, "fmem_ck_aft_dcm_ch1"),
213 FMCLK(ABIST, 1, "AD_ARMPLL_CK"),
214 FMCLK(ABIST, 2, "0"),
215 FMCLK(ABIST, 3, "AD_MAINPLL_CK"),
216 FMCLK(ABIST, 4, "AD_CSI0A_CDPHY_DELAYCAL_CK"),
217 FMCLK(ABIST, 5, "AD_CSI0B_CDPHY_DELAYCAL_CK"),
218 FMCLK(ABIST, 7, "AD_USB20_CLK480M"),
219 FMCLK(ABIST, 8, "AD_USB20_CLK480M_1P"),
220 FMCLK(ABIST, 9, "AD_MADADC_26MCKO"),
221 FMCLK(ABIST, 10, "AD_MAINPLL_H546M_CK"),
222 FMCLK(ABIST, 11, "AD_MAINPLL_H364M_CK"),
223 FMCLK(ABIST, 12, "AD_MAINPLL_H218P4M_CK"),
224 FMCLK(ABIST, 13, "AD_MAINPLL_H156M_CK"),
225 FMCLK(ABIST, 14, "AD_UNIVPLL_1248M_CK"),
226 FMCLK(ABIST, 15, "AD_USB20_192M_CK"),
227 FMCLK(ABIST, 16, "AD_UNIVPLL_624M_CK"),
228 FMCLK(ABIST, 17, "AD_UNIVPLL_416M_CK"),
229 FMCLK(ABIST, 18, "AD_UNIVPLL_249P6M_CK"),
230 FMCLK(ABIST, 19, "AD_UNIVPLL_178P3M_CK"),
231 FMCLK(ABIST, 20, "AD_SYS_26M_CK"),
232 FMCLK(ABIST, 21, "AD_CSI1A_DPHY_DELAYCAL_CK"),
233 FMCLK(ABIST, 22, "AD_CSI1B_DPHY_DELAYCAL_CK"),
234 FMCLK(ABIST, 23, "AD_CSI2A_DPHY_DELAYCAL_CK"),
235 FMCLK(ABIST, 24, "AD_CSI2B_DPHY_DELAYCAL_CK"),
236 FMCLK(ABIST, 25, "RTC32K"),
237 FMCLK(ABIST, 26, "AD_MMPLL_CK"),
238 FMCLK(ABIST, 27, "AD_MFGPLL_CK"),
239 FMCLK(ABIST, 28, "AD_MSDCPLL_CK"),
240 FMCLK(ABIST, 29, "AD_DSI0_LNTC_DSICLK"),
241 FMCLK(ABIST, 30, "AD_DSI0_MPPLL_TST_CK"),
242 FMCLK(ABIST, 31, "AD_APPLLGP_TST_CK"),
243 FMCLK(ABIST, 32, "AD_APLL1_CK"),
244 FMCLK(ABIST, 33, "AD_APLL2_CK"),
245 FMCLK(ABIST, 34, "AD_MADCKO_TEST"),
246 FMCLK(ABIST, 35, "AD_MPLL_208M_CK"),
247 FMCLK(ABIST, 36, "Armpll_ll_mon_ck"),
248 FMCLK(ABIST, 37, "vad_clk_i"),
249 FMCLK(ABIST, 38, "msdc01_in_ck"),
250 FMCLK(ABIST, 40, "msdc11_in_ck"),
251 FMCLK(ABIST, 41, "msdc12_in_ck"),
252 FMCLK(ABIST, 42, "AD_PLLGP_TST_CK"),
253 FMCLK(ABIST, 43, "AD_LVDSTX_CLKDIG_CTS"),
254 FMCLK(ABIST, 44, "AD_LVDSTX_CLKDIG"),
255 FMCLK(ABIST, 45, "AD_VPLL_DPIX_CK"),
256 FMCLK(ABIST, 46, "DA_USB20_48M_DIV_CK"),
257 FMCLK(ABIST, 47, "DA_UNIV_48M_DIV_CK"),
258 FMCLK(ABIST, 48, "DA_MPLL_104M_DIV_CK"),
259 FMCLK(ABIST, 49, "DA_MPLL_52M_DIV_CK"),
260 FMCLK(ABIST, 50, "DA_PLLGP_CPU_CK_MON"),
261 FMCLK(ABIST, 51, "trng_freq_debug_out0"),
262 FMCLK(ABIST, 52, "trng_freq_debug_out1"),
263 FMCLK(ABIST, 53, "AD_LVDSTX_MONCLK"),
264 FMCLK(ABIST, 54, "AD_VPLL_MONREF_CK"),
265 FMCLK(ABIST, 55, "AD_VPLL_MONFBK_CK"),
266 FMCLK(ABIST, 56, "AD_LVDSPLL_300M_CK"),
267 FMCLK(ABIST, 57, "AD_DSPPLL_CK"),
268 FMCLK(ABIST, 58, "AD_APUPLL_CK"),
269 {}
270};
271
272#define CLK_MISC_CFG_0 (rb[topckgen].virt + 0x104)
273#define CLK_DBG_CFG (rb[topckgen].virt + 0x10C)
274#define CLK26CALI_0 (rb[topckgen].virt + 0x220)
275#define CLK26CALI_1 (rb[topckgen].virt + 0x224)
276
277static unsigned int mt_get_ckgen_freq(unsigned int ID)
278{
279 int output = 0, i = 0;
280 unsigned int tmp, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1, clk26cali_0;
281
282 clk_dbg_cfg = clk_readl(CLK_DBG_CFG);
283 clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xFFFFC0FC) | (ID << 8) | (0x1));
284
285 clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0);
286 clk_writel(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF));
287
288 clk26cali_0 = clk_readl(CLK26CALI_0);
289 clk26cali_1 = clk_readl(CLK26CALI_1);
290 clk_writel(CLK26CALI_1,
291 (clk26cali_1 & ~(0x3FF0000)) | (DEFAULT_CYCLE_COUNT << 16));
292 mdelay(1);
293 clk_writel(CLK26CALI_0, 0x1000);
294 clk_writel(CLK26CALI_0, 0x1010);
295
296 while (clk_readl(CLK26CALI_0) & 0x10) {
297 mdelay(10);
298 i++;
299 if (i > 10)
300 break;
301 }
302
303 tmp = clk_readl(CLK26CALI_1);
304 output = ((tmp & 0xFFFF) * 26000) / (DEFAULT_CYCLE_COUNT + 1);
305
306 clk_writel(CLK_DBG_CFG, clk_dbg_cfg);
307 clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0);
308 clk_writel(CLK26CALI_0, clk26cali_0);
309 clk_writel(CLK26CALI_1, clk26cali_1);
310
311 if (i > 10)
312 return 0;
313 else
314 return output;
315
316}
317
318static unsigned int mt_get_abist_freq(unsigned int ID)
319{
320 int output = 0, i = 0;
321 unsigned int tmp, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1, clk26cali_0;
322
323 clk_dbg_cfg = clk_readl(CLK_DBG_CFG);
324 clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xFFC0FFFC) | (ID << 16));
325
326 clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0);
327 clk_writel(CLK_MISC_CFG_0,
328 (clk_misc_cfg_0 & 0x00FFFFFF) | (CKGEN_K1 << 24));
329
330 clk26cali_0 = clk_readl(CLK26CALI_0);
331 clk26cali_1 = clk_readl(CLK26CALI_1);
332 clk_writel(CLK26CALI_1,
333 (clk26cali_1 & ~(0x3FF0000)) | (DEFAULT_CYCLE_COUNT << 16));
334 mdelay(1);
335 clk_writel(CLK26CALI_0, 0x1000);
336 clk_writel(CLK26CALI_0, 0x1010);
337
338 while (clk_readl(CLK26CALI_0) & 0x10) {
339 mdelay(10);
340 i++;
341 if (i > 10)
342 break;
343 }
344
345 tmp = clk_readl(CLK26CALI_1);
346 output = ((tmp & 0xFFFF) * 26000) / (DEFAULT_CYCLE_COUNT + 1);
347
348 clk_writel(CLK_DBG_CFG, clk_dbg_cfg);
349 clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0);
350 clk_writel(CLK26CALI_0, clk26cali_0);
351 clk_writel(CLK26CALI_1, clk26cali_1);
352
353 if (i > 10)
354 return 0;
355 else
356 return (output * (CKGEN_K1 + 1));
357}
358
359static u32 fmeter_freq_op(const struct fmeter_clk *fclk)
360{
361 if (fclk->type == ABIST)
362 return mt_get_abist_freq(fclk->id);
363 else if (fclk->type == CKGEN)
364 return mt_get_ckgen_freq(fclk->id);
365 return 0;
366}
367
368static const struct fmeter_clk *get_all_fmeter_clks(void)
369{
370 return fclks;
371}
372
373/*
374 * clkdbg dump_state
375 */
376
377static const char * const *get_all_clk_names(void)
378{
379 static const char * const clks[] = {
380
381 "i2s0_bck",
382 "dsi0_lntc_dsick",
383 "vpll_dpix",
384 "lvdstx_dig_cts",
385 "mfgpll_ck",
386 "syspll_d2",
387 "syspll1_d2",
388 "syspll1_d4",
389 "syspll1_d8",
390 "syspll1_d16",
391 "syspll_d3",
392 "syspll2_d2",
393 "syspll2_d4",
394 "syspll2_d8",
395 "syspll_d5",
396 "syspll3_d2",
397 "syspll3_d4",
398 "syspll_d7",
399 "syspll4_d2",
400 "syspll4_d4",
401 "univpll_d2",
402 "univpll1_d2",
403 "univpll1_d4",
404 "univpll_d3",
405 "univpll2_d2",
406 "univpll2_d4",
407 "univpll2_d8",
408 "univpll2_d32",
409 "univpll_d5",
410 "univpll3_d2",
411 "univpll3_d4",
412 "mmpll_ck",
413 "mmpll_d2",
414 "lvdspll_d2",
415 "lvdspll_d4",
416 "lvdspll_d8",
417 "lvdspll_d16",
418 "usb20_192m_ck",
419 "usb20_192m_d4",
420 "usb20_192m_d8",
421 "usb20_192m_d16",
422 "usb20_192m_d32",
423 "apll1_ck",
424 "apll1_d2",
425 "apll1_d4",
426 "apll1_d8",
427 "apll2_ck",
428 "apll2_d2",
429 "apll2_d4",
430 "apll2_d8",
431 "clk26m_ck",
432 "sys_26m_d2",
433 "msdcpll_ck",
434 "msdcpll_d2",
435 "dsppll_ck",
436 "dsppll_d2",
437 "dsppll_d4",
438 "dsppll_d8",
439 "apupll_ck",
440 "mpll_d2",
441 "mpll_d4",
442 "clk26m_d52",
443 "axi_sel",
444 "mem_sel",
445 "mm_sel",
446 "scp_sel",
447 "mfg_sel",
448 "atb_sel",
449 "camtg_sel",
450 "camtg1_sel",
451 "uart_sel",
452 "spi_sel",
453 "msdc50_0_hc_sel",
454 "msdc2_2_hc_sel",
455 "msdc50_0_sel",
456 "msdc50_2_sel",
457 "msdc30_1_sel",
458 "audio_sel",
459 "aud_intbus_sel",
460 "aud_1_sel",
461 "aud_2_sel",
462 "aud_engen1_sel",
463 "aud_engen2_sel",
464 "aud_spdif_sel",
465 "disp_pwm_sel",
466 "dxcc_sel",
467 "ssusb_sys_sel",
468 "ssusb_xhci_sel",
469 "spm_sel",
470 "i2c_sel",
471 "pwm_sel",
472 "senif_sel",
473 "aes_fde_sel",
474 "camtm_sel",
475 "dpi0_sel",
476 "dpi1_sel",
477 "dsp_sel",
478 "nfi2x_sel",
479 "nfiecc_sel",
480 "ecc_sel",
481 "eth_sel",
482 "gcpu_sel",
483 "gcpu_cpm_sel",
484 "apu_sel",
485 "apu_if_sel",
486 "mbist_diag_sel",
487 "apll_i2s0_sel",
488 "apll_i2s1_sel",
489 "apll_i2s2_sel",
490 "apll_i2s3_sel",
491 "apll_tdmout_sel",
492 "apll_tdmin_sel",
493 "apll_spdif_sel",
494 "apll12_ck_div0",
495 "apll12_ck_div1",
496 "apll12_ck_div2",
497 "apll12_ck_div3",
498 "apll12_ck_div4",
499 "apll12_ck_div4b",
500 "apll12_ck_div5",
501 "apll12_ck_div5b",
502 "apll12_ck_div6",
503 "aud_i2s0_m_ck",
504 "aud_i2s1_m_ck",
505 "aud_i2s2_m_ck",
506 "aud_i2s3_m_ck",
507 "aud_tdmout_m_ck",
508 "aud_tdmout_b_ck",
509 "aud_tdmin_m_ck",
510 "aud_tdmin_b_ck",
511 "aud_spdif_m_ck",
512 "usb20_48m_en",
513 "univpll_48m_en",
514 "lvdstx_dig_en",
515 "vpll_dpix_en",
516 "ssusb_top_ck_en",
517 "ssusb_phy_ck_en",
518 "conn_32k",
519 "conn_26m",
520 "dsp_32k",
521 "dsp_26m",
522 "ifr_pmic_tmr",
523 "ifr_pmic_ap",
524 "ifr_pmic_md",
525 "ifr_pmic_conn",
526 "ifr_sej",
527 "ifr_apxgpt",
528 "ifr_icusb",
529 "ifr_gce",
530 "ifr_therm",
531 "ifr_pwm_hclk",
532 "ifr_pwm1",
533 "ifr_pwm2",
534 "ifr_pwm3",
535 "ifr_pwm4",
536 "ifr_pwm5",
537 "ifr_pwm",
538 "ifr_uart0",
539 "ifr_uart1",
540 "ifr_gce_26m",
541 "ifr_cq_dma_fpc",
542 "ifr_btif",
543 "ifr_spi0",
544 "ifr_msdc",
545 "ifr_msdc1",
546 "ifr_dvfsrc",
547 "ifr_gcpu",
548 "ifr_trng",
549 "ifr_auxadc",
550 "ifr_auxadc_md",
551 "ifr_ap_dma",
552 "ifr_device_apc",
553 "ifr_debugsys",
554 "ifr_audio",
555 "ifr_dramc_f26m",
556 "ifr_pwm_fbclk6",
557 "ifr_disp_pwm",
558 "ifr_aud_26m_bk",
559 "ifr_cq_dma",
560 "ifr_msdc0_sf",
561 "ifr_msdc1_sf",
562 "ifr_msdc2_sf",
563 "ifr_ap_msdc0",
564 "ifr_md_msdc0",
565 "ifr_msdc0_src",
566 "ifr_msdc1_src",
567 "ifr_msdc2_src",
568 "ifr_pwrap_tmr",
569 "ifr_pwrap_spi",
570 "ifr_pwrap_sys",
571 "ifr_sej_f13m",
572 "ifr_mcu_pm_bk",
573 "ifr_irrx_26m",
574 "ifr_irrx_32k",
575 "ifr_i2c0_axi",
576 "ifr_i2c1_axi",
577 "ifr_i2c2_axi",
578 "ifr_i2c3_axi",
579 "ifr_nic_axi",
580 "ifr_nic_slv_axi",
581 "ifr_apu_axi",
582 "ifr_nfiecc",
583 "ifr_nfiecc_bk",
584 "ifr_nfi1x_bk",
585 "ifr_nfi_bk",
586 "ifr_msdc2_ap_bk",
587 "ifr_msdc2_md_bk",
588 "ifr_msdc2_bk",
589 "ifr_susb_133_bk",
590 "ifr_susb_66_bk",
591 "ifr_ssusb_sys",
592 "ifr_ssusb_ref",
593 "ifr_ssusb_xhci",
594 "armpll",
595 "mainpll",
596 "univpll",
597 "mfgpll",
598 "msdcpll",
599 "mmpll",
600 "apll1",
601 "apll2",
602 "mpll",
603 "lvdspll",
604 "dsppll",
605 "apupll",
606 "mfg_bg3d",
607 "mfg_mbist_diag",
608 "mm_mdp_rdma0",
609 "mm_mdp_ccorr0",
610 "mm_mdp_rsz0",
611 "mm_mdp_rsz1",
612 "mm_mdp_tdshp0",
613 "mm_mdp_wrot0",
614 "mm_mdp_wdma0",
615 "mm_disp_ovl0",
616 "mm_disp_ovl0_21",
617 "mm_disp_rsz0",
618 "mm_disp_rdma0",
619 "mm_disp_wdma0",
620 "mm_disp_color0",
621 "mm_disp_ccorr0",
622 "mm_disp_aal0",
623 "mm_disp_gamma0",
624 "mm_disp_dither0",
625 "mm_dsi0",
626 "mm_disp_rdma1",
627 "mm_mdp_rdma1",
628 "mm_dpi0_dpi0",
629 "mm_fake",
630 "mm_smi_common",
631 "mm_smi_larb0",
632 "mm_smi_comm0",
633 "mm_smi_comm1",
634 "mm_cam_mdp",
635 "mm_smi_img",
636 "mm_smi_cam",
637 "mm_dl_relay",
638 "mm_dl_async_top",
639 "mm_dsi0_dig_dsi",
640 "mm_f26m_hrtwt",
641 "mm_dpi0",
642 "mm_flvdstx_pxl",
643 "mm_flvdstx_cts",
644 "cam_larb2",
645 "cam",
646 "camtg",
647 "cam_senif",
648 "camsv0",
649 "camsv1",
650 "cam_fdvt",
651 "cam_wpe",
652 "vdec_fvdec_ck",
653 "vdec_flarb1_ck",
654 "venc_fvenc_ck",
655 "venc_jpgenc_ck",
656 /* end */
657 NULL
658 };
659
660 return clks;
661}
662
663/*
664 * clkdbg pwr_status
665 */
666
667static const char * const *get_pwr_names(void)
668{
669 static const char * const pwr_names[] = {
670 [0] = "",
671 [1] = "CONN",
672 [2] = "DDRPHY",
673 [3] = "DISP",
674 [4] = "MFG",
675 [5] = "",
676 [6] = "INFRA",
677 [7] = "",
678 [8] = "MP0_CPUTOP",
679 [9] = "MP0_CPU0",
680 [10] = "MP0_CPU1",
681 [11] = "MP0_CPU2",
682 [12] = "MP0_CPU3",
683 [13] = "",
684 [14] = "MCUSYS",
685 [15] = "",
686 [16] = "APU",
687 [17] = "DSP",
688 [18] = "",
689 [19] = "",
690 [20] = "",
691 [21] = "VENC",
692 [22] = "",
693 [23] = "",
694 [24] = "AUDIO",
695 [25] = "CAM",
696 [26] = "",
697 [27] = "",
698 [28] = "",
699 [29] = "",
700 [30] = "",
701 [31] = "VDEC",
702 };
703
704 return pwr_names;
705}
706
707/*
708 * clkdbg dump_clks
709 */
710
711static void setup_provider_clk(struct provider_clk *pvdck)
712{
713 static const struct {
714 const char *pvdname;
715 u32 pwr_mask;
716 } pvd_pwr_mask[] = {
717 };
718
719 size_t i;
720 const char *pvdname = pvdck->provider_name;
721
722 if (pvdname == NULL)
723 return;
724
725 for (i = 0; i < ARRAY_SIZE(pvd_pwr_mask); i++) {
726 if (strcmp(pvdname, pvd_pwr_mask[i].pvdname) == 0) {
727 pvdck->pwr_mask = pvd_pwr_mask[i].pwr_mask;
728 return;
729 }
730 }
731}
732
733/*
734 * init functions
735 */
736
737static struct clkdbg_ops clkdbg_mt8168_ops = {
738 .get_all_fmeter_clks = get_all_fmeter_clks,
739 .fmeter_freq = fmeter_freq_op,
740 .get_all_regnames = get_all_regnames,
741 .get_all_clk_names = get_all_clk_names,
742 .get_pwr_names = get_pwr_names,
743 .setup_provider_clk = setup_provider_clk,
744};
745
746static void __init init_custom_cmds(void)
747{
748 static const struct cmd_fn cmds[] = {
749 {}
750 };
751
752 set_custom_cmds(cmds);
753}
754
755static int __init clkdbg_mt8168_init(void)
756{
757 if (of_machine_is_compatible("mediatek,mt8168") == 0)
758 return -ENODEV;
759
760 init_regbase();
761
762 init_custom_cmds();
763 set_clkdbg_ops(&clkdbg_mt8168_ops);
764
765#if DUMP_INIT_STATE
766 print_regs();
767 print_fmeter_all();
768#endif /* DUMP_INIT_STATE */
769
770 return 0;
771}
772device_initcall(clkdbg_mt8168_init);