| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * R-Car Gen2 Clock Pulse Generator |
| 3 | * |
| 4 | * Copyright (C) 2016 Cogent Embedded Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published |
| 8 | * by the Free Software Foundation; version 2 of the License. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__ |
| 12 | #define __CLK_RENESAS_RCAR_GEN2_CPG_H__ |
| 13 | |
| 14 | enum rcar_gen2_clk_types { |
| 15 | CLK_TYPE_GEN2_MAIN = CLK_TYPE_CUSTOM, |
| 16 | CLK_TYPE_GEN2_PLL0, |
| 17 | CLK_TYPE_GEN2_PLL1, |
| 18 | CLK_TYPE_GEN2_PLL3, |
| 19 | CLK_TYPE_GEN2_Z, |
| 20 | CLK_TYPE_GEN2_LB, |
| 21 | CLK_TYPE_GEN2_ADSP, |
| 22 | CLK_TYPE_GEN2_SDH, |
| 23 | CLK_TYPE_GEN2_SD0, |
| 24 | CLK_TYPE_GEN2_SD1, |
| 25 | CLK_TYPE_GEN2_QSPI, |
| 26 | CLK_TYPE_GEN2_RCAN, |
| 27 | }; |
| 28 | |
| 29 | struct rcar_gen2_cpg_pll_config { |
| 30 | unsigned int extal_div; |
| 31 | unsigned int pll1_mult; |
| 32 | unsigned int pll3_mult; |
| 33 | unsigned int pll0_mult; /* leave as zero if PLL0CR exists */ |
| 34 | }; |
| 35 | |
| 36 | struct clk *rcar_gen2_cpg_clk_register(struct device *dev, |
| 37 | const struct cpg_core_clk *core, const struct cpg_mssr_info *info, |
| 38 | struct clk **clks, void __iomem *base, |
| 39 | struct raw_notifier_head *notifiers); |
| 40 | int rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config, |
| 41 | unsigned int pll0_div, u32 mode); |
| 42 | |
| 43 | #endif |