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192.168.1.100 / T800 / 0b39b87cb0cd96fd68f16a6d004c85c06a954fb2 / . / src / kernel / linux / v4.19 / drivers / irqchip / irq-xtensa-mx.c
blob: e539500752d463f6051fce31085866dbd4abc853 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1/*
2 * Xtensa MX interrupt distributor
3 *
4 * Copyright (C) 2002 - 2013 Tensilica, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/interrupt.h>
12#include <linux/irqdomain.h>
13#include <linux/irq.h>
14#include <linux/irqchip.h>
15#include <linux/of.h>
16
17#include <asm/mxregs.h>
18
19#define HW_IRQ_IPI_COUNT 2
20#define HW_IRQ_MX_BASE 2
21#define HW_IRQ_EXTERN_BASE 3
22
23static DEFINE_PER_CPU(unsigned int, cached_irq_mask);
24
25static int xtensa_mx_irq_map(struct irq_domain *d, unsigned int irq,
26 irq_hw_number_t hw)
27{
28 if (hw < HW_IRQ_IPI_COUNT) {
29 struct irq_chip *irq_chip = d->host_data;
30 irq_set_chip_and_handler_name(irq, irq_chip,
31 handle_percpu_irq, "ipi");
32 irq_set_status_flags(irq, IRQ_LEVEL);
33 return 0;
34 }
35 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
36 return xtensa_irq_map(d, irq, hw);
37}
38
39/*
40 * Device Tree IRQ specifier translation function which works with one or
41 * two cell bindings. First cell value maps directly to the hwirq number.
42 * Second cell if present specifies whether hwirq number is external (1) or
43 * internal (0).
44 */
45static int xtensa_mx_irq_domain_xlate(struct irq_domain *d,
46 struct device_node *ctrlr,
47 const u32 *intspec, unsigned int intsize,
48 unsigned long *out_hwirq, unsigned int *out_type)
49{
50 return xtensa_irq_domain_xlate(intspec, intsize,
51 intspec[0], intspec[0] + HW_IRQ_EXTERN_BASE,
52 out_hwirq, out_type);
53}
54
55static const struct irq_domain_ops xtensa_mx_irq_domain_ops = {
56 .xlate = xtensa_mx_irq_domain_xlate,
57 .map = xtensa_mx_irq_map,
58};
59
60void secondary_init_irq(void)
61{
62 __this_cpu_write(cached_irq_mask,
63 XCHAL_INTTYPE_MASK_EXTERN_EDGE |
64 XCHAL_INTTYPE_MASK_EXTERN_LEVEL);
65 set_sr(XCHAL_INTTYPE_MASK_EXTERN_EDGE |
66 XCHAL_INTTYPE_MASK_EXTERN_LEVEL, intenable);
67}
68
69static void xtensa_mx_irq_mask(struct irq_data *d)
70{
71 unsigned int mask = 1u << d->hwirq;
72
73 if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
74 XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
75 set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) -
76 HW_IRQ_MX_BASE), MIENG);
77 } else {
78 mask = __this_cpu_read(cached_irq_mask) & ~mask;
79 __this_cpu_write(cached_irq_mask, mask);
80 set_sr(mask, intenable);
81 }
82}
83
84static void xtensa_mx_irq_unmask(struct irq_data *d)
85{
86 unsigned int mask = 1u << d->hwirq;
87
88 if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
89 XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
90 set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) -
91 HW_IRQ_MX_BASE), MIENGSET);
92 } else {
93 mask |= __this_cpu_read(cached_irq_mask);
94 __this_cpu_write(cached_irq_mask, mask);
95 set_sr(mask, intenable);
96 }
97}
98
99static void xtensa_mx_irq_enable(struct irq_data *d)
100{
101 xtensa_mx_irq_unmask(d);
102}
103
104static void xtensa_mx_irq_disable(struct irq_data *d)
105{
106 xtensa_mx_irq_mask(d);
107}
108
109static void xtensa_mx_irq_ack(struct irq_data *d)
110{
111 set_sr(1 << d->hwirq, intclear);
112}
113
114static int xtensa_mx_irq_retrigger(struct irq_data *d)
115{
116 set_sr(1 << d->hwirq, intset);
117 return 1;
118}
119
120static int xtensa_mx_irq_set_affinity(struct irq_data *d,
121 const struct cpumask *dest, bool force)
122{
123 int cpu = cpumask_any_and(dest, cpu_online_mask);
124 unsigned mask = 1u << cpu;
125
126 set_er(mask, MIROUT(d->hwirq - HW_IRQ_MX_BASE));
127 irq_data_update_effective_affinity(d, cpumask_of(cpu));
128
129 return 0;
130
131}
132
133static struct irq_chip xtensa_mx_irq_chip = {
134 .name = "xtensa-mx",
135 .irq_enable = xtensa_mx_irq_enable,
136 .irq_disable = xtensa_mx_irq_disable,
137 .irq_mask = xtensa_mx_irq_mask,
138 .irq_unmask = xtensa_mx_irq_unmask,
139 .irq_ack = xtensa_mx_irq_ack,
140 .irq_retrigger = xtensa_mx_irq_retrigger,
141 .irq_set_affinity = xtensa_mx_irq_set_affinity,
142};
143
144int __init xtensa_mx_init_legacy(struct device_node *interrupt_parent)
145{
146 struct irq_domain *root_domain =
147 irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
148 &xtensa_mx_irq_domain_ops,
149 &xtensa_mx_irq_chip);
150 irq_set_default_host(root_domain);
151 secondary_init_irq();
152 return 0;
153}
154
155static int __init xtensa_mx_init(struct device_node *np,
156 struct device_node *interrupt_parent)
157{
158 struct irq_domain *root_domain =
159 irq_domain_add_linear(np, NR_IRQS, &xtensa_mx_irq_domain_ops,
160 &xtensa_mx_irq_chip);
161 irq_set_default_host(root_domain);
162 secondary_init_irq();
163 return 0;
164}
165IRQCHIP_DECLARE(xtensa_mx_irq_chip, "cdns,xtensa-mx", xtensa_mx_init);