| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014 MediaTek Inc. |
| 3 | * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #ifndef __PINCTRL_MTK_COMMON_H |
| 16 | #define __PINCTRL_MTK_COMMON_H |
| 17 | |
| 18 | #include <linux/pinctrl/pinctrl.h> |
| 19 | #include <linux/regmap.h> |
| 20 | #include <linux/pinctrl/pinconf-generic.h> |
| 21 | |
| 22 | #include "mtk-eint.h" |
| 23 | |
| 24 | #define NO_EINT_SUPPORT 255 |
| 25 | #define MT_EDGE_SENSITIVE 0 |
| 26 | #define MT_LEVEL_SENSITIVE 1 |
| 27 | #define EINT_DBNC_SET_DBNC_BITS 4 |
| 28 | #define EINT_DBNC_RST_BIT (0x1 << 1) |
| 29 | #define EINT_DBNC_SET_EN (0x1 << 0) |
| 30 | |
| 31 | #define MTK_PINCTRL_NOT_SUPPORT (0xffff) |
| 32 | |
| 33 | struct mtk_desc_function { |
| 34 | const char *name; |
| 35 | unsigned char muxval; |
| 36 | }; |
| 37 | |
| 38 | struct mtk_desc_eint { |
| 39 | unsigned char eintmux; |
| 40 | unsigned char eintnum; |
| 41 | }; |
| 42 | |
| 43 | struct mtk_desc_pin { |
| 44 | struct pinctrl_pin_desc pin; |
| 45 | const struct mtk_desc_eint eint; |
| 46 | const struct mtk_desc_function *functions; |
| 47 | }; |
| 48 | |
| 49 | #define MTK_PIN(_pin, _pad, _chip, _eint, ...) \ |
| 50 | { \ |
| 51 | .pin = _pin, \ |
| 52 | .eint = _eint, \ |
| 53 | .functions = (struct mtk_desc_function[]){ \ |
| 54 | __VA_ARGS__, { } }, \ |
| 55 | } |
| 56 | |
| 57 | #define MTK_EINT_FUNCTION(_eintmux, _eintnum) \ |
| 58 | { \ |
| 59 | .eintmux = _eintmux, \ |
| 60 | .eintnum = _eintnum, \ |
| 61 | } |
| 62 | |
| 63 | #define MTK_FUNCTION(_val, _name) \ |
| 64 | { \ |
| 65 | .muxval = _val, \ |
| 66 | .name = _name, \ |
| 67 | } |
| 68 | |
| 69 | #define SET_ADDR(x, y) (x + (y->devdata->port_align)) |
| 70 | #define CLR_ADDR(x, y) (x + (y->devdata->port_align << 1)) |
| 71 | |
| 72 | struct mtk_pinctrl_group { |
| 73 | const char *name; |
| 74 | unsigned long config; |
| 75 | unsigned pin; |
| 76 | }; |
| 77 | |
| 78 | /** |
| 79 | * struct mtk_drv_group_desc - Provide driving group data. |
| 80 | * @max_drv: The maximum current of this group. |
| 81 | * @min_drv: The minimum current of this group. |
| 82 | * @low_bit: The lowest bit of this group. |
| 83 | * @high_bit: The highest bit of this group. |
| 84 | * @step: The step current of this group. |
| 85 | */ |
| 86 | struct mtk_drv_group_desc { |
| 87 | unsigned char min_drv; |
| 88 | unsigned char max_drv; |
| 89 | unsigned char low_bit; |
| 90 | unsigned char high_bit; |
| 91 | unsigned char step; |
| 92 | }; |
| 93 | |
| 94 | #define MTK_DRV_GRP(_min, _max, _low, _high, _step) \ |
| 95 | { \ |
| 96 | .min_drv = _min, \ |
| 97 | .max_drv = _max, \ |
| 98 | .low_bit = _low, \ |
| 99 | .high_bit = _high, \ |
| 100 | .step = _step, \ |
| 101 | } |
| 102 | |
| 103 | /** |
| 104 | * struct mtk_pin_drv_grp - Provide each pin driving info. |
| 105 | * @pin: The pin number. |
| 106 | * @offset: The offset of driving register for this pin. |
| 107 | * @bit: The bit of driving register for this pin. |
| 108 | * @grp: The group for this pin belongs to. |
| 109 | */ |
| 110 | struct mtk_pin_drv_grp { |
| 111 | unsigned short pin; |
| 112 | unsigned short offset; |
| 113 | unsigned char bit; |
| 114 | unsigned char grp; |
| 115 | }; |
| 116 | |
| 117 | #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ |
| 118 | { \ |
| 119 | .pin = _pin, \ |
| 120 | .offset = _offset, \ |
| 121 | .bit = _bit, \ |
| 122 | .grp = _grp, \ |
| 123 | } |
| 124 | |
| 125 | /** |
| 126 | * struct mtk_pin_spec_pupd_set_samereg |
| 127 | * - For special pins' pull up/down setting which resides in same register |
| 128 | * @pin: The pin number. |
| 129 | * @offset: The offset of special pull up/down setting register. |
| 130 | * @pupd_bit: The pull up/down bit in this register. |
| 131 | * @r0_bit: The r0 bit of pull resistor. |
| 132 | * @r1_bit: The r1 bit of pull resistor. |
| 133 | */ |
| 134 | struct mtk_pin_spec_pupd_set_samereg { |
| 135 | unsigned short pin; |
| 136 | unsigned short offset; |
| 137 | unsigned char pupd_bit; |
| 138 | unsigned char r1_bit; |
| 139 | unsigned char r0_bit; |
| 140 | }; |
| 141 | |
| 142 | #define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ |
| 143 | { \ |
| 144 | .pin = _pin, \ |
| 145 | .offset = _offset, \ |
| 146 | .pupd_bit = _pupd, \ |
| 147 | .r1_bit = _r1, \ |
| 148 | .r0_bit = _r0, \ |
| 149 | } |
| 150 | |
| 151 | /** |
| 152 | * struct mtk_pin_ies_set - For special pins' ies and smt setting. |
| 153 | * @start: The start pin number of those special pins. |
| 154 | * @end: The end pin number of those special pins. |
| 155 | * @offset: The offset of special setting register. |
| 156 | * @bit: The bit of special setting register. |
| 157 | */ |
| 158 | struct mtk_pin_ies_smt_set { |
| 159 | unsigned short start; |
| 160 | unsigned short end; |
| 161 | unsigned short offset; |
| 162 | unsigned char bit; |
| 163 | }; |
| 164 | |
| 165 | #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ |
| 166 | { \ |
| 167 | .start = _start, \ |
| 168 | .end = _end, \ |
| 169 | .bit = _bit, \ |
| 170 | .offset = _offset, \ |
| 171 | } |
| 172 | |
| 173 | struct mtk_eint_offsets { |
| 174 | const char *name; |
| 175 | unsigned int stat; |
| 176 | unsigned int ack; |
| 177 | unsigned int mask; |
| 178 | unsigned int mask_set; |
| 179 | unsigned int mask_clr; |
| 180 | unsigned int sens; |
| 181 | unsigned int sens_set; |
| 182 | unsigned int sens_clr; |
| 183 | unsigned int soft; |
| 184 | unsigned int soft_set; |
| 185 | unsigned int soft_clr; |
| 186 | unsigned int pol; |
| 187 | unsigned int pol_set; |
| 188 | unsigned int pol_clr; |
| 189 | unsigned int dom_en; |
| 190 | unsigned int dbnc_ctrl; |
| 191 | unsigned int dbnc_set; |
| 192 | unsigned int dbnc_clr; |
| 193 | u8 port_mask; |
| 194 | u8 ports; |
| 195 | }; |
| 196 | |
| 197 | /** |
| 198 | * struct mtk_pinctrl_devdata - Provide HW GPIO related data. |
| 199 | * @pins: An array describing all pins the pin controller affects. |
| 200 | * @npins: The number of entries in @pins. |
| 201 | * |
| 202 | * @grp_desc: The driving group info. |
| 203 | * @pin_drv_grp: The driving group for all pins. |
| 204 | * @spec_pull_set: Each SoC may have special pins for pull up/down setting, |
| 205 | * these pins' pull setting are very different, they have separate pull |
| 206 | * up/down bit, R0 and R1 resistor bit, so they need special pull setting. |
| 207 | * If special setting is success, this should return 0, otherwise it should |
| 208 | * return non-zero value. |
| 209 | * @spec_ies_smt_set: Some pins are irregular, their input enable and smt |
| 210 | * control register are discontinuous, but they are mapping together. That |
| 211 | * means when user set smt, input enable is set at the same time. So they |
| 212 | * also need special control. If special control is success, this should |
| 213 | * return 0, otherwise return non-zero value. |
| 214 | * @spec_pinmux_set: In some cases, there are two pinmux functions share |
| 215 | * the same value in the same segment of pinmux control register. If user |
| 216 | * want to use one of the two functions, they need an extra bit setting to |
| 217 | * select the right one. |
| 218 | * @spec_dir_set: In very few SoCs, direction control registers are not |
| 219 | * arranged continuously, they may be cut to parts. So they need special |
| 220 | * dir setting. |
| 221 | |
| 222 | * @dir_offset: The direction register offset. |
| 223 | * @pullen_offset: The pull-up/pull-down enable register offset. |
| 224 | * @pinmux_offset: The pinmux register offset. |
| 225 | * |
| 226 | * @type1_start: Some chips have two base addresses for pull select register, |
| 227 | * that means some pins use the first address and others use the second. This |
| 228 | * member record the start of pin number to use the second address. |
| 229 | * @type1_end: The end of pin number to use the second address. |
| 230 | * |
| 231 | * @port_shf: The shift between two registers. |
| 232 | * @port_mask: The mask of register. |
| 233 | * @port_align: Provide clear register and set register step. |
| 234 | */ |
| 235 | struct mtk_pinctrl_devdata { |
| 236 | const struct mtk_desc_pin *pins; |
| 237 | unsigned int npins; |
| 238 | const struct mtk_drv_group_desc *grp_desc; |
| 239 | unsigned int n_grp_cls; |
| 240 | const struct mtk_pin_drv_grp *pin_drv_grp; |
| 241 | unsigned int n_pin_drv_grps; |
| 242 | int (*spec_pull_set)(struct regmap *reg, unsigned int pin, |
| 243 | unsigned char align, bool isup, unsigned int arg); |
| 244 | int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin, |
| 245 | unsigned char align, int value, enum pin_config_param arg); |
| 246 | void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin, |
| 247 | unsigned int mode); |
| 248 | void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin); |
| 249 | unsigned int dir_offset; |
| 250 | unsigned int ies_offset; |
| 251 | unsigned int smt_offset; |
| 252 | unsigned int pullen_offset; |
| 253 | unsigned int pullsel_offset; |
| 254 | unsigned int drv_offset; |
| 255 | unsigned int dout_offset; |
| 256 | unsigned int din_offset; |
| 257 | unsigned int pinmux_offset; |
| 258 | unsigned short type1_start; |
| 259 | unsigned short type1_end; |
| 260 | unsigned char port_shf; |
| 261 | unsigned char port_mask; |
| 262 | unsigned char port_align; |
| 263 | struct mtk_eint_hw eint_hw; |
| 264 | struct mtk_eint_regs *eint_regs; |
| 265 | }; |
| 266 | |
| 267 | struct mtk_pinctrl { |
| 268 | struct regmap *regmap1; |
| 269 | struct regmap *regmap2; |
| 270 | struct pinctrl_desc pctl_desc; |
| 271 | struct device *dev; |
| 272 | struct gpio_chip *chip; |
| 273 | struct mtk_pinctrl_group *groups; |
| 274 | unsigned ngroups; |
| 275 | const char **grp_names; |
| 276 | struct pinctrl_dev *pctl_dev; |
| 277 | const struct mtk_pinctrl_devdata *devdata; |
| 278 | struct mtk_eint *eint; |
| 279 | }; |
| 280 | |
| 281 | int mtk_pctrl_init(struct platform_device *pdev, |
| 282 | const struct mtk_pinctrl_devdata *data, |
| 283 | struct regmap *regmap); |
| 284 | |
| 285 | int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, |
| 286 | const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, |
| 287 | unsigned int info_num, unsigned int pin, |
| 288 | unsigned char align, bool isup, unsigned int r1r0); |
| 289 | |
| 290 | int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, |
| 291 | const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, |
| 292 | unsigned int pin, unsigned char align, int value); |
| 293 | |
| 294 | extern const struct dev_pm_ops mtk_eint_pm_ops; |
| 295 | |
| 296 | #endif /* __PINCTRL_MTK_COMMON_H */ |