| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | config ARCH_HAS_RESET_CONTROLLER |
| 2 | bool |
| 3 | |
| 4 | menuconfig RESET_CONTROLLER |
| 5 | bool "Reset Controller Support" |
| 6 | default y if ARCH_HAS_RESET_CONTROLLER |
| 7 | help |
| 8 | Generic Reset Controller support. |
| 9 | |
| 10 | This framework is designed to abstract reset handling of devices |
| 11 | via GPIOs or SoC-internal reset controller modules. |
| 12 | |
| 13 | If unsure, say no. |
| 14 | |
| 15 | if RESET_CONTROLLER |
| 16 | |
| 17 | config RESET_A10SR |
| 18 | tristate "Altera Arria10 System Resource Reset" |
| 19 | depends on MFD_ALTERA_A10SR |
| 20 | help |
| 21 | This option enables support for the external reset functions for |
| 22 | peripheral PHYs on the Altera Arria10 System Resource Chip. |
| 23 | |
| 24 | config RESET_ATH79 |
| 25 | bool "AR71xx Reset Driver" if COMPILE_TEST |
| 26 | default ATH79 |
| 27 | help |
| 28 | This enables the ATH79 reset controller driver that supports the |
| 29 | AR71xx SoC reset controller. |
| 30 | |
| 31 | config RESET_AXS10X |
| 32 | bool "AXS10x Reset Driver" if COMPILE_TEST |
| 33 | default ARC_PLAT_AXS10X |
| 34 | help |
| 35 | This enables the reset controller driver for AXS10x. |
| 36 | |
| 37 | config RESET_BERLIN |
| 38 | bool "Berlin Reset Driver" if COMPILE_TEST |
| 39 | default ARCH_BERLIN |
| 40 | help |
| 41 | This enables the reset controller driver for Marvell Berlin SoCs. |
| 42 | |
| 43 | config RESET_HSDK |
| 44 | bool "Synopsys HSDK Reset Driver" |
| 45 | depends on HAS_IOMEM |
| 46 | depends on ARC_SOC_HSDK || COMPILE_TEST |
| 47 | help |
| 48 | This enables the reset controller driver for HSDK board. |
| 49 | |
| 50 | config RESET_IMX7 |
| 51 | bool "i.MX7 Reset Driver" if COMPILE_TEST |
| 52 | depends on HAS_IOMEM |
| 53 | default SOC_IMX7D |
| 54 | select MFD_SYSCON |
| 55 | help |
| 56 | This enables the reset controller driver for i.MX7 SoCs. |
| 57 | |
| 58 | config RESET_LANTIQ |
| 59 | bool "Lantiq XWAY Reset Driver" if COMPILE_TEST |
| 60 | default SOC_TYPE_XWAY |
| 61 | help |
| 62 | This enables the reset controller driver for Lantiq / Intel XWAY SoCs. |
| 63 | |
| 64 | config RESET_LPC18XX |
| 65 | bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST |
| 66 | default ARCH_LPC18XX |
| 67 | help |
| 68 | This enables the reset controller driver for NXP LPC18xx/43xx SoCs. |
| 69 | |
| 70 | config RESET_MESON |
| 71 | bool "Meson Reset Driver" if COMPILE_TEST |
| 72 | default ARCH_MESON |
| 73 | help |
| 74 | This enables the reset driver for Amlogic Meson SoCs. |
| 75 | |
| 76 | config RESET_MESON_AUDIO_ARB |
| 77 | tristate "Meson Audio Memory Arbiter Reset Driver" |
| 78 | depends on ARCH_MESON || COMPILE_TEST |
| 79 | help |
| 80 | This enables the reset driver for Audio Memory Arbiter of |
| 81 | Amlogic's A113 based SoCs |
| 82 | |
| 83 | config RESET_OXNAS |
| 84 | bool |
| 85 | |
| 86 | config RESET_PISTACHIO |
| 87 | bool "Pistachio Reset Driver" if COMPILE_TEST |
| 88 | default MACH_PISTACHIO |
| 89 | help |
| 90 | This enables the reset driver for ImgTec Pistachio SoCs. |
| 91 | |
| 92 | config RESET_QCOM_AOSS |
| 93 | bool "Qcom AOSS Reset Driver" |
| 94 | depends on ARCH_QCOM || COMPILE_TEST |
| 95 | help |
| 96 | This enables the AOSS (always on subsystem) reset driver |
| 97 | for Qualcomm SDM845 SoCs. Say Y if you want to control |
| 98 | reset signals provided by AOSS for Modem, Venus, ADSP, |
| 99 | GPU, Camera, Wireless, Display subsystem. Otherwise, say N. |
| 100 | |
| 101 | config RESET_SIMPLE |
| 102 | bool "Simple Reset Controller Driver" if COMPILE_TEST |
| 103 | default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED |
| 104 | help |
| 105 | This enables a simple reset controller driver for reset lines that |
| 106 | that can be asserted and deasserted by toggling bits in a contiguous, |
| 107 | exclusive register space. |
| 108 | |
| 109 | Currently this driver supports: |
| 110 | - Altera SoCFPGAs |
| 111 | - ASPEED BMC SoCs |
| 112 | - RCC reset controller in STM32 MCUs |
| 113 | - Allwinner SoCs |
| 114 | - ZTE's zx2967 family |
| 115 | |
| 116 | config RESET_STM32MP157 |
| 117 | bool "STM32MP157 Reset Driver" if COMPILE_TEST |
| 118 | default MACH_STM32MP157 |
| 119 | help |
| 120 | This enables the RCC reset controller driver for STM32 MPUs. |
| 121 | |
| 122 | config RESET_SUNXI |
| 123 | bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI |
| 124 | default ARCH_SUNXI |
| 125 | select RESET_SIMPLE |
| 126 | help |
| 127 | This enables the reset driver for Allwinner SoCs. |
| 128 | |
| 129 | config RESET_TI_SCI |
| 130 | tristate "TI System Control Interface (TI-SCI) reset driver" |
| 131 | depends on TI_SCI_PROTOCOL |
| 132 | help |
| 133 | This enables the reset driver support over TI System Control Interface |
| 134 | available on some new TI's SoCs. If you wish to use reset resources |
| 135 | managed by the TI System Controller, say Y here. Otherwise, say N. |
| 136 | |
| 137 | config RESET_TI_SYSCON |
| 138 | tristate "TI SYSCON Reset Driver" |
| 139 | depends on HAS_IOMEM |
| 140 | select MFD_SYSCON |
| 141 | help |
| 142 | This enables the reset driver support for TI devices with |
| 143 | memory-mapped reset registers as part of a syscon device node. If |
| 144 | you wish to use the reset framework for such memory-mapped devices, |
| 145 | say Y here. Otherwise, say N. |
| 146 | |
| 147 | config RESET_UNIPHIER |
| 148 | tristate "Reset controller driver for UniPhier SoCs" |
| 149 | depends on ARCH_UNIPHIER || COMPILE_TEST |
| 150 | depends on OF && MFD_SYSCON |
| 151 | default ARCH_UNIPHIER |
| 152 | help |
| 153 | Support for reset controllers on UniPhier SoCs. |
| 154 | Say Y if you want to control reset signals provided by System Control |
| 155 | block, Media I/O block, Peripheral Block. |
| 156 | |
| 157 | config RESET_UNIPHIER_USB3 |
| 158 | tristate "USB3 reset driver for UniPhier SoCs" |
| 159 | depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF |
| 160 | default ARCH_UNIPHIER |
| 161 | select RESET_SIMPLE |
| 162 | help |
| 163 | Support for the USB3 core reset on UniPhier SoCs. |
| 164 | Say Y if you want to control reset signals provided by |
| 165 | USB3 glue layer. |
| 166 | |
| 167 | config RESET_ZYNQ |
| 168 | bool "ZYNQ Reset Driver" if COMPILE_TEST |
| 169 | default ARCH_ZYNQ |
| 170 | help |
| 171 | This enables the reset controller driver for Xilinx Zynq SoCs. |
| 172 | |
| 173 | source "drivers/reset/sti/Kconfig" |
| 174 | source "drivers/reset/hisilicon/Kconfig" |
| 175 | source "drivers/reset/tegra/Kconfig" |
| 176 | |
| 177 | endif |