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192.168.1.100 / T800 / 0b39b87cb0cd96fd68f16a6d004c85c06a954fb2 / . / src / kernel / linux / v4.19 / drivers / soc / mediatek / mtk-pmic-wrap.c
blob: 75216f32d84266fed276b5107ef0c3c0890a1934 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author Flora Fu <flora.fu@mediatek.com>
5 */
6#include <linux/clk.h>
7#include <linux/interrupt.h>
8#include <linux/io.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/of_device.h>
12#include <linux/platform_device.h>
13#include <linux/regmap.h>
14#include <linux/reset.h>
15#include <linux/sched/clock.h>
16
17#define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4
18#define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10
19#define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14
20#define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24
21#define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28
22#define PWRAP_MT8135_BRIDGE_INT_EN 0x38
23#define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48
24#define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50
25#define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54
26
27/* macro for wrapper status */
28#define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)
29#define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)
30#define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)
31#define PWRAP_STATE_SYNC_IDLE0 (1 << 20)
32#define PWRAP_STATE_INIT_DONE0 (1 << 22)
33
34/* macro for WACS FSM */
35#define PWRAP_WACS_FSM_IDLE 0x00
36#define PWRAP_WACS_FSM_REQ 0x02
37#define PWRAP_WACS_FSM_WFDLE 0x04
38#define PWRAP_WACS_FSM_WFVLDCLR 0x06
39#define PWRAP_WACS_INIT_DONE 0x01
40#define PWRAP_WACS_WACS_SYNC_IDLE 0x01
41#define PWRAP_WACS_SYNC_BUSY 0x00
42
43/* macro for device wrapper default value */
44#define PWRAP_DEW_READ_TEST_VAL 0x5aa5
45#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
46
47/* macro for manual command */
48#define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14)
49#define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
50#define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
51#define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
52#define PWRAP_MAN_CMD_OP_CK (0x2 << 8)
53#define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8)
54#define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8)
55#define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
56
57/* macro for Watch Dog Timer Source */
58#define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25)
59#define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20)
60#define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6)
61#define PWRAP_WDT_SRC_MASK_ALL 0xffffffff
62#define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \
63 PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
64 PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
65
66/* Group of bits used for shown slave capability */
67#define PWRAP_SLV_CAP_SPI BIT(0)
68#define PWRAP_SLV_CAP_DUALIO BIT(1)
69#define PWRAP_SLV_CAP_SECURITY BIT(2)
70#define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x))
71
72/* Group of bits used for shown pwrap capability */
73#define PWRAP_CAP_BRIDGE BIT(0)
74#define PWRAP_CAP_RESET BIT(1)
75#define PWRAP_CAP_DCM BIT(2)
76#define PWRAP_CAP_PRIORITY_SEL BIT(3)
77#define PWRAP_CAP_INT1_EN BIT(4)
78#define PWRAP_CAP_MONITOR_V1 BIT(5)
79#define PWRAP_CAP_MONITOR_V2 BIT(6)
80#define PWRAP_CAP_ULPOSC_CLK BIT(7)
81
82/* defines for slave device wrapper registers */
83enum dew_regs {
84 PWRAP_DEW_BASE,
85 PWRAP_DEW_DIO_EN,
86 PWRAP_DEW_READ_TEST,
87 PWRAP_DEW_WRITE_TEST,
88 PWRAP_DEW_CRC_EN,
89 PWRAP_DEW_CRC_VAL,
90 PWRAP_DEW_MON_GRP_SEL,
91 PWRAP_DEW_CIPHER_KEY_SEL,
92 PWRAP_DEW_CIPHER_IV_SEL,
93 PWRAP_DEW_CIPHER_RDY,
94 PWRAP_DEW_CIPHER_MODE,
95 PWRAP_DEW_CIPHER_SWRST,
96
97 /* MT6397 only regs */
98 PWRAP_DEW_EVENT_OUT_EN,
99 PWRAP_DEW_EVENT_SRC_EN,
100 PWRAP_DEW_EVENT_SRC,
101 PWRAP_DEW_EVENT_FLAG,
102 PWRAP_DEW_MON_FLAG_SEL,
103 PWRAP_DEW_EVENT_TEST,
104 PWRAP_DEW_CIPHER_LOAD,
105 PWRAP_DEW_CIPHER_START,
106
107 /* MT6323 only regs */
108 PWRAP_DEW_CIPHER_EN,
109 PWRAP_DEW_RDDMY_NO,
110};
111
112static const u32 mt6323_regs[] = {
113 [PWRAP_DEW_BASE] = 0x0000,
114 [PWRAP_DEW_DIO_EN] = 0x018a,
115 [PWRAP_DEW_READ_TEST] = 0x018c,
116 [PWRAP_DEW_WRITE_TEST] = 0x018e,
117 [PWRAP_DEW_CRC_EN] = 0x0192,
118 [PWRAP_DEW_CRC_VAL] = 0x0194,
119 [PWRAP_DEW_MON_GRP_SEL] = 0x0196,
120 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198,
121 [PWRAP_DEW_CIPHER_IV_SEL] = 0x019a,
122 [PWRAP_DEW_CIPHER_EN] = 0x019c,
123 [PWRAP_DEW_CIPHER_RDY] = 0x019e,
124 [PWRAP_DEW_CIPHER_MODE] = 0x01a0,
125 [PWRAP_DEW_CIPHER_SWRST] = 0x01a2,
126 [PWRAP_DEW_RDDMY_NO] = 0x01a4,
127};
128
129static const u32 mt6397_regs[] = {
130 [PWRAP_DEW_BASE] = 0xbc00,
131 [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
132 [PWRAP_DEW_DIO_EN] = 0xbc02,
133 [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04,
134 [PWRAP_DEW_EVENT_SRC] = 0xbc06,
135 [PWRAP_DEW_EVENT_FLAG] = 0xbc08,
136 [PWRAP_DEW_READ_TEST] = 0xbc0a,
137 [PWRAP_DEW_WRITE_TEST] = 0xbc0c,
138 [PWRAP_DEW_CRC_EN] = 0xbc0e,
139 [PWRAP_DEW_CRC_VAL] = 0xbc10,
140 [PWRAP_DEW_MON_GRP_SEL] = 0xbc12,
141 [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14,
142 [PWRAP_DEW_EVENT_TEST] = 0xbc16,
143 [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18,
144 [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a,
145 [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c,
146 [PWRAP_DEW_CIPHER_START] = 0xbc1e,
147 [PWRAP_DEW_CIPHER_RDY] = 0xbc20,
148 [PWRAP_DEW_CIPHER_MODE] = 0xbc22,
149 [PWRAP_DEW_CIPHER_SWRST] = 0xbc24,
150};
151
152static const u32 mt6351_regs[] = {
153 [PWRAP_DEW_DIO_EN] = 0x02F2,
154 [PWRAP_DEW_READ_TEST] = 0x02F4,
155 [PWRAP_DEW_WRITE_TEST] = 0x02F6,
156 [PWRAP_DEW_CRC_EN] = 0x02FA,
157 [PWRAP_DEW_CRC_VAL] = 0x02FC,
158 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0300,
159 [PWRAP_DEW_CIPHER_IV_SEL] = 0x0302,
160 [PWRAP_DEW_CIPHER_EN] = 0x0304,
161 [PWRAP_DEW_CIPHER_RDY] = 0x0306,
162 [PWRAP_DEW_CIPHER_MODE] = 0x0308,
163 [PWRAP_DEW_CIPHER_SWRST] = 0x030A,
164 [PWRAP_DEW_RDDMY_NO] = 0x030C,
165};
166
167static const u32 mt6359_regs[] = {
168 [PWRAP_DEW_DIO_EN] = 0x040c,
169 [PWRAP_DEW_READ_TEST] = 0x040e,
170 [PWRAP_DEW_WRITE_TEST] = 0x0410,
171 [PWRAP_DEW_CRC_EN] = 0x0414,
172 [PWRAP_DEW_CRC_VAL] = 0x0416,
173 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,
174 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041a,
175 [PWRAP_DEW_CIPHER_EN] = 0x041c,
176 [PWRAP_DEW_CIPHER_RDY] = 0x041e,
177 [PWRAP_DEW_CIPHER_MODE] = 0x0420,
178 [PWRAP_DEW_CIPHER_SWRST] = 0x0422,
179 [PWRAP_DEW_RDDMY_NO] = 0x0424,
180};
181
182enum pwrap_regs {
183 PWRAP_MUX_SEL,
184 PWRAP_WRAP_EN,
185 PWRAP_DIO_EN,
186 PWRAP_SIDLY,
187 PWRAP_CSHEXT_WRITE,
188 PWRAP_CSHEXT_READ,
189 PWRAP_CSLEXT_START,
190 PWRAP_CSLEXT_END,
191 PWRAP_STAUPD_PRD,
192 PWRAP_STAUPD_GRPEN,
193 PWRAP_STAUPD_MAN_TRIG,
194 PWRAP_STAUPD_STA,
195 PWRAP_WRAP_STA,
196 PWRAP_HARB_INIT,
197 PWRAP_HARB_HPRIO,
198 PWRAP_HIPRIO_ARB_EN,
199 PWRAP_HARB_STA0,
200 PWRAP_HARB_STA1,
201 PWRAP_MAN_EN,
202 PWRAP_MAN_CMD,
203 PWRAP_MAN_RDATA,
204 PWRAP_MAN_VLDCLR,
205 PWRAP_WACS0_EN,
206 PWRAP_INIT_DONE0,
207 PWRAP_WACS0_CMD,
208 PWRAP_WACS0_RDATA,
209 PWRAP_WACS0_VLDCLR,
210 PWRAP_WACS1_EN,
211 PWRAP_INIT_DONE1,
212 PWRAP_WACS1_CMD,
213 PWRAP_WACS1_RDATA,
214 PWRAP_WACS1_VLDCLR,
215 PWRAP_WACS2_EN,
216 PWRAP_INIT_DONE2,
217 PWRAP_WACS2_CMD,
218 PWRAP_WACS2_RDATA,
219 PWRAP_WACS2_VLDCLR,
220 PWRAP_WACS3_EN,
221 PWRAP_INIT_DONE3,
222 PWRAP_WACS3_CMD,
223 PWRAP_WACS3_RDATA,
224 PWRAP_WACS3_VLDCLR,
225 PWRAP_INT_EN,
226 PWRAP_INT_FLG_RAW,
227 PWRAP_INT_FLG,
228 PWRAP_INT_CLR,
229 PWRAP_SIG_ADR,
230 PWRAP_SIG_MODE,
231 PWRAP_SIG_VALUE,
232 PWRAP_SIG_ERRVAL,
233 PWRAP_CRC_EN,
234 PWRAP_TIMER_EN,
235 PWRAP_TIMER_STA,
236 PWRAP_WDT_UNIT,
237 PWRAP_WDT_SRC_EN,
238 PWRAP_WDT_FLG,
239 PWRAP_DEBUG_INT_SEL,
240 PWRAP_CIPHER_KEY_SEL,
241 PWRAP_CIPHER_IV_SEL,
242 PWRAP_CIPHER_RDY,
243 PWRAP_CIPHER_MODE,
244 PWRAP_CIPHER_SWRST,
245 PWRAP_DCM_EN,
246 PWRAP_DCM_DBC_PRD,
247
248 /* MT2701 only regs */
249 PWRAP_ADC_CMD_ADDR,
250 PWRAP_PWRAP_ADC_CMD,
251 PWRAP_ADC_RDY_ADDR,
252 PWRAP_ADC_RDATA_ADDR1,
253 PWRAP_ADC_RDATA_ADDR2,
254
255 /* MT6779 only regs */
256 PWRAP_CSLEXT_WRITE,
257 PWRAP_CSLEXT_READ,
258 PWRAP_STAUPD_CTRL,
259 PWRAP_EXT_CK_WRITE,
260 PWRAP_INT0_FLG_RAW,
261 PWRAP_INT0_FLG,
262 PWRAP_INT0_CLR,
263 PWRAP_INT1_EN,
264 PWRAP_INT1_FLG_RAW,
265 PWRAP_INT1_FLG,
266 PWRAP_INT1_CLR,
267 PWRAP_TIMER_CTRL,
268 PWRAP_WDT_CTRL,
269 PWRAP_WDT_SRC_EN_1,
270 PWRAP_WDT_FLG_1,
271 PWRAP_EINT_STA0_ADR,
272 PWRAP_EINT_STA1_ADR,
273 PWRAP_EINT_STA,
274 PWRAP_EINT_CLR,
275 PWRAP_HPRIO_ARB_EN,
276
277 /* MT7622 only regs */
278 PWRAP_STA,
279 PWRAP_CLR,
280 PWRAP_DVFS_ADR8,
281 PWRAP_DVFS_WDATA8,
282 PWRAP_DVFS_ADR9,
283 PWRAP_DVFS_WDATA9,
284 PWRAP_DVFS_ADR10,
285 PWRAP_DVFS_WDATA10,
286 PWRAP_DVFS_ADR11,
287 PWRAP_DVFS_WDATA11,
288 PWRAP_DVFS_ADR12,
289 PWRAP_DVFS_WDATA12,
290 PWRAP_DVFS_ADR13,
291 PWRAP_DVFS_WDATA13,
292 PWRAP_DVFS_ADR14,
293 PWRAP_DVFS_WDATA14,
294 PWRAP_DVFS_ADR15,
295 PWRAP_DVFS_WDATA15,
296 PWRAP_EXT_CK,
297 PWRAP_ADC_RDATA_ADDR,
298 PWRAP_GPS_STA,
299 PWRAP_SW_RST,
300 PWRAP_DVFS_STEP_CTRL0,
301 PWRAP_DVFS_STEP_CTRL1,
302 PWRAP_DVFS_STEP_CTRL2,
303 PWRAP_SPI2_CTRL,
304
305 /* MT8135 only regs */
306 PWRAP_CSHEXT,
307 PWRAP_EVENT_IN_EN,
308 PWRAP_EVENT_DST_EN,
309 PWRAP_RRARB_INIT,
310 PWRAP_RRARB_EN,
311 PWRAP_RRARB_STA0,
312 PWRAP_RRARB_STA1,
313 PWRAP_EVENT_STA,
314 PWRAP_EVENT_STACLR,
315 PWRAP_CIPHER_LOAD,
316 PWRAP_CIPHER_START,
317
318 /* MT8173 only regs */
319 PWRAP_RDDMY,
320 PWRAP_SI_CK_CON,
321 PWRAP_DVFS_ADR0,
322 PWRAP_DVFS_WDATA0,
323 PWRAP_DVFS_ADR1,
324 PWRAP_DVFS_WDATA1,
325 PWRAP_DVFS_ADR2,
326 PWRAP_DVFS_WDATA2,
327 PWRAP_DVFS_ADR3,
328 PWRAP_DVFS_WDATA3,
329 PWRAP_DVFS_ADR4,
330 PWRAP_DVFS_WDATA4,
331 PWRAP_DVFS_ADR5,
332 PWRAP_DVFS_WDATA5,
333 PWRAP_DVFS_ADR6,
334 PWRAP_DVFS_WDATA6,
335 PWRAP_DVFS_ADR7,
336 PWRAP_DVFS_WDATA7,
337 PWRAP_SPMINF_STA,
338 PWRAP_CIPHER_EN,
339};
340
341static int mt2701_regs[] = {
342 [PWRAP_MUX_SEL] = 0x0,
343 [PWRAP_WRAP_EN] = 0x4,
344 [PWRAP_DIO_EN] = 0x8,
345 [PWRAP_SIDLY] = 0xc,
346 [PWRAP_RDDMY] = 0x18,
347 [PWRAP_SI_CK_CON] = 0x1c,
348 [PWRAP_CSHEXT_WRITE] = 0x20,
349 [PWRAP_CSHEXT_READ] = 0x24,
350 [PWRAP_CSLEXT_START] = 0x28,
351 [PWRAP_CSLEXT_END] = 0x2c,
352 [PWRAP_STAUPD_PRD] = 0x30,
353 [PWRAP_STAUPD_GRPEN] = 0x34,
354 [PWRAP_STAUPD_MAN_TRIG] = 0x38,
355 [PWRAP_STAUPD_STA] = 0x3c,
356 [PWRAP_WRAP_STA] = 0x44,
357 [PWRAP_HARB_INIT] = 0x48,
358 [PWRAP_HARB_HPRIO] = 0x4c,
359 [PWRAP_HIPRIO_ARB_EN] = 0x50,
360 [PWRAP_HARB_STA0] = 0x54,
361 [PWRAP_HARB_STA1] = 0x58,
362 [PWRAP_MAN_EN] = 0x5c,
363 [PWRAP_MAN_CMD] = 0x60,
364 [PWRAP_MAN_RDATA] = 0x64,
365 [PWRAP_MAN_VLDCLR] = 0x68,
366 [PWRAP_WACS0_EN] = 0x6c,
367 [PWRAP_INIT_DONE0] = 0x70,
368 [PWRAP_WACS0_CMD] = 0x74,
369 [PWRAP_WACS0_RDATA] = 0x78,
370 [PWRAP_WACS0_VLDCLR] = 0x7c,
371 [PWRAP_WACS1_EN] = 0x80,
372 [PWRAP_INIT_DONE1] = 0x84,
373 [PWRAP_WACS1_CMD] = 0x88,
374 [PWRAP_WACS1_RDATA] = 0x8c,
375 [PWRAP_WACS1_VLDCLR] = 0x90,
376 [PWRAP_WACS2_EN] = 0x94,
377 [PWRAP_INIT_DONE2] = 0x98,
378 [PWRAP_WACS2_CMD] = 0x9c,
379 [PWRAP_WACS2_RDATA] = 0xa0,
380 [PWRAP_WACS2_VLDCLR] = 0xa4,
381 [PWRAP_INT_EN] = 0xa8,
382 [PWRAP_INT_FLG_RAW] = 0xac,
383 [PWRAP_INT_FLG] = 0xb0,
384 [PWRAP_INT_CLR] = 0xb4,
385 [PWRAP_SIG_ADR] = 0xb8,
386 [PWRAP_SIG_MODE] = 0xbc,
387 [PWRAP_SIG_VALUE] = 0xc0,
388 [PWRAP_SIG_ERRVAL] = 0xc4,
389 [PWRAP_CRC_EN] = 0xc8,
390 [PWRAP_TIMER_EN] = 0xcc,
391 [PWRAP_TIMER_STA] = 0xd0,
392 [PWRAP_WDT_UNIT] = 0xd4,
393 [PWRAP_WDT_SRC_EN] = 0xd8,
394 [PWRAP_WDT_FLG] = 0xdc,
395 [PWRAP_DEBUG_INT_SEL] = 0xe0,
396 [PWRAP_DVFS_ADR0] = 0xe4,
397 [PWRAP_DVFS_WDATA0] = 0xe8,
398 [PWRAP_DVFS_ADR1] = 0xec,
399 [PWRAP_DVFS_WDATA1] = 0xf0,
400 [PWRAP_DVFS_ADR2] = 0xf4,
401 [PWRAP_DVFS_WDATA2] = 0xf8,
402 [PWRAP_DVFS_ADR3] = 0xfc,
403 [PWRAP_DVFS_WDATA3] = 0x100,
404 [PWRAP_DVFS_ADR4] = 0x104,
405 [PWRAP_DVFS_WDATA4] = 0x108,
406 [PWRAP_DVFS_ADR5] = 0x10c,
407 [PWRAP_DVFS_WDATA5] = 0x110,
408 [PWRAP_DVFS_ADR6] = 0x114,
409 [PWRAP_DVFS_WDATA6] = 0x118,
410 [PWRAP_DVFS_ADR7] = 0x11c,
411 [PWRAP_DVFS_WDATA7] = 0x120,
412 [PWRAP_CIPHER_KEY_SEL] = 0x124,
413 [PWRAP_CIPHER_IV_SEL] = 0x128,
414 [PWRAP_CIPHER_EN] = 0x12c,
415 [PWRAP_CIPHER_RDY] = 0x130,
416 [PWRAP_CIPHER_MODE] = 0x134,
417 [PWRAP_CIPHER_SWRST] = 0x138,
418 [PWRAP_DCM_EN] = 0x13c,
419 [PWRAP_DCM_DBC_PRD] = 0x140,
420 [PWRAP_ADC_CMD_ADDR] = 0x144,
421 [PWRAP_PWRAP_ADC_CMD] = 0x148,
422 [PWRAP_ADC_RDY_ADDR] = 0x14c,
423 [PWRAP_ADC_RDATA_ADDR1] = 0x150,
424 [PWRAP_ADC_RDATA_ADDR2] = 0x154,
425};
426
427static int mt6779_regs[] = {
428 [PWRAP_MUX_SEL] = 0x0,
429 [PWRAP_WRAP_EN] = 0x4,
430 [PWRAP_DIO_EN] = 0x8,
431 [PWRAP_RDDMY] = 0x20,
432 [PWRAP_CSHEXT_WRITE] = 0x24,
433 [PWRAP_CSHEXT_READ] = 0x28,
434 [PWRAP_CSLEXT_WRITE] = 0x2C,
435 [PWRAP_CSLEXT_READ] = 0x30,
436 [PWRAP_EXT_CK_WRITE] = 0x34,
437 [PWRAP_STAUPD_CTRL] = 0x3C,
438 [PWRAP_STAUPD_GRPEN] = 0x40,
439 [PWRAP_EINT_STA0_ADR] = 0x44,
440 [PWRAP_EINT_STA1_ADR] = 0x48,
441 [PWRAP_EINT_STA] = 0x4C,
442 [PWRAP_EINT_CLR] = 0x50,
443 [PWRAP_HPRIO_ARB_EN] = 0x6C,
444 [PWRAP_MAN_EN] = 0x7C,
445 [PWRAP_MAN_CMD] = 0x80,
446 [PWRAP_WACS0_EN] = 0x8C,
447 [PWRAP_WACS1_EN] = 0x94,
448 [PWRAP_WACS2_EN] = 0x9C,
449 [PWRAP_WACS3_EN] = 0xA4,
450 [PWRAP_INIT_DONE0] = 0x90,
451 [PWRAP_INIT_DONE1] = 0x98,
452 [PWRAP_INIT_DONE2] = 0xA0,
453 [PWRAP_INIT_DONE3] = 0xA8,
454 [PWRAP_INT_EN] = 0xBC,
455 [PWRAP_INT0_FLG_RAW] = 0xC0,
456 [PWRAP_INT0_FLG] = 0xC4,
457 [PWRAP_INT0_CLR] = 0xC8,
458 [PWRAP_INT1_EN] = 0xCC,
459 [PWRAP_INT1_FLG_RAW] = 0xD0,
460 [PWRAP_INT1_FLG] = 0xD4,
461 [PWRAP_INT1_CLR] = 0xD8,
462 [PWRAP_TIMER_CTRL] = 0xF0,
463 [PWRAP_WDT_CTRL] = 0xF8,
464 [PWRAP_WDT_SRC_EN] = 0xFC,
465 [PWRAP_WDT_SRC_EN_1] = 0x100,
466 [PWRAP_WDT_FLG] = 0x104,
467 [PWRAP_WDT_FLG_1] = 0x108,
468 [PWRAP_WACS0_CMD] = 0xC00,
469 [PWRAP_WACS0_RDATA] = 0xC04,
470 [PWRAP_WACS0_VLDCLR] = 0xC08,
471 [PWRAP_WACS1_CMD] = 0xC10,
472 [PWRAP_WACS1_RDATA] = 0xC14,
473 [PWRAP_WACS1_VLDCLR] = 0xC18,
474 [PWRAP_WACS2_CMD] = 0xC20,
475 [PWRAP_WACS2_RDATA] = 0xC24,
476 [PWRAP_WACS2_VLDCLR] = 0xC28,
477 [PWRAP_WACS3_CMD] = 0xC30,
478 [PWRAP_WACS3_RDATA] = 0xC34,
479 [PWRAP_WACS3_VLDCLR] = 0xC38,
480};
481
482static int mt6797_regs[] = {
483 [PWRAP_MUX_SEL] = 0x0,
484 [PWRAP_WRAP_EN] = 0x4,
485 [PWRAP_DIO_EN] = 0x8,
486 [PWRAP_SIDLY] = 0xC,
487 [PWRAP_RDDMY] = 0x10,
488 [PWRAP_CSHEXT_WRITE] = 0x18,
489 [PWRAP_CSHEXT_READ] = 0x1C,
490 [PWRAP_CSLEXT_START] = 0x20,
491 [PWRAP_CSLEXT_END] = 0x24,
492 [PWRAP_STAUPD_PRD] = 0x28,
493 [PWRAP_HARB_HPRIO] = 0x50,
494 [PWRAP_HIPRIO_ARB_EN] = 0x54,
495 [PWRAP_MAN_EN] = 0x60,
496 [PWRAP_MAN_CMD] = 0x64,
497 [PWRAP_WACS0_EN] = 0x70,
498 [PWRAP_WACS1_EN] = 0x84,
499 [PWRAP_WACS2_EN] = 0x98,
500 [PWRAP_INIT_DONE2] = 0x9C,
501 [PWRAP_WACS2_CMD] = 0xA0,
502 [PWRAP_WACS2_RDATA] = 0xA4,
503 [PWRAP_WACS2_VLDCLR] = 0xA8,
504 [PWRAP_INT_EN] = 0xC0,
505 [PWRAP_INT_FLG_RAW] = 0xC4,
506 [PWRAP_INT_FLG] = 0xC8,
507 [PWRAP_INT_CLR] = 0xCC,
508 [PWRAP_TIMER_EN] = 0xF4,
509 [PWRAP_WDT_UNIT] = 0xFC,
510 [PWRAP_WDT_SRC_EN] = 0x100,
511 [PWRAP_DCM_EN] = 0x1CC,
512 [PWRAP_DCM_DBC_PRD] = 0x1D4,
513};
514
515static int mt7622_regs[] = {
516 [PWRAP_MUX_SEL] = 0x0,
517 [PWRAP_WRAP_EN] = 0x4,
518 [PWRAP_DIO_EN] = 0x8,
519 [PWRAP_SIDLY] = 0xC,
520 [PWRAP_RDDMY] = 0x10,
521 [PWRAP_SI_CK_CON] = 0x14,
522 [PWRAP_CSHEXT_WRITE] = 0x18,
523 [PWRAP_CSHEXT_READ] = 0x1C,
524 [PWRAP_CSLEXT_START] = 0x20,
525 [PWRAP_CSLEXT_END] = 0x24,
526 [PWRAP_STAUPD_PRD] = 0x28,
527 [PWRAP_STAUPD_GRPEN] = 0x2C,
528 [PWRAP_EINT_STA0_ADR] = 0x30,
529 [PWRAP_EINT_STA1_ADR] = 0x34,
530 [PWRAP_STA] = 0x38,
531 [PWRAP_CLR] = 0x3C,
532 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
533 [PWRAP_STAUPD_STA] = 0x44,
534 [PWRAP_WRAP_STA] = 0x48,
535 [PWRAP_HARB_INIT] = 0x4C,
536 [PWRAP_HARB_HPRIO] = 0x50,
537 [PWRAP_HIPRIO_ARB_EN] = 0x54,
538 [PWRAP_HARB_STA0] = 0x58,
539 [PWRAP_HARB_STA1] = 0x5C,
540 [PWRAP_MAN_EN] = 0x60,
541 [PWRAP_MAN_CMD] = 0x64,
542 [PWRAP_MAN_RDATA] = 0x68,
543 [PWRAP_MAN_VLDCLR] = 0x6C,
544 [PWRAP_WACS0_EN] = 0x70,
545 [PWRAP_INIT_DONE0] = 0x74,
546 [PWRAP_WACS0_CMD] = 0x78,
547 [PWRAP_WACS0_RDATA] = 0x7C,
548 [PWRAP_WACS0_VLDCLR] = 0x80,
549 [PWRAP_WACS1_EN] = 0x84,
550 [PWRAP_INIT_DONE1] = 0x88,
551 [PWRAP_WACS1_CMD] = 0x8C,
552 [PWRAP_WACS1_RDATA] = 0x90,
553 [PWRAP_WACS1_VLDCLR] = 0x94,
554 [PWRAP_WACS2_EN] = 0x98,
555 [PWRAP_INIT_DONE2] = 0x9C,
556 [PWRAP_WACS2_CMD] = 0xA0,
557 [PWRAP_WACS2_RDATA] = 0xA4,
558 [PWRAP_WACS2_VLDCLR] = 0xA8,
559 [PWRAP_INT_EN] = 0xAC,
560 [PWRAP_INT_FLG_RAW] = 0xB0,
561 [PWRAP_INT_FLG] = 0xB4,
562 [PWRAP_INT_CLR] = 0xB8,
563 [PWRAP_SIG_ADR] = 0xBC,
564 [PWRAP_SIG_MODE] = 0xC0,
565 [PWRAP_SIG_VALUE] = 0xC4,
566 [PWRAP_SIG_ERRVAL] = 0xC8,
567 [PWRAP_CRC_EN] = 0xCC,
568 [PWRAP_TIMER_EN] = 0xD0,
569 [PWRAP_TIMER_STA] = 0xD4,
570 [PWRAP_WDT_UNIT] = 0xD8,
571 [PWRAP_WDT_SRC_EN] = 0xDC,
572 [PWRAP_WDT_FLG] = 0xE0,
573 [PWRAP_DEBUG_INT_SEL] = 0xE4,
574 [PWRAP_DVFS_ADR0] = 0xE8,
575 [PWRAP_DVFS_WDATA0] = 0xEC,
576 [PWRAP_DVFS_ADR1] = 0xF0,
577 [PWRAP_DVFS_WDATA1] = 0xF4,
578 [PWRAP_DVFS_ADR2] = 0xF8,
579 [PWRAP_DVFS_WDATA2] = 0xFC,
580 [PWRAP_DVFS_ADR3] = 0x100,
581 [PWRAP_DVFS_WDATA3] = 0x104,
582 [PWRAP_DVFS_ADR4] = 0x108,
583 [PWRAP_DVFS_WDATA4] = 0x10C,
584 [PWRAP_DVFS_ADR5] = 0x110,
585 [PWRAP_DVFS_WDATA5] = 0x114,
586 [PWRAP_DVFS_ADR6] = 0x118,
587 [PWRAP_DVFS_WDATA6] = 0x11C,
588 [PWRAP_DVFS_ADR7] = 0x120,
589 [PWRAP_DVFS_WDATA7] = 0x124,
590 [PWRAP_DVFS_ADR8] = 0x128,
591 [PWRAP_DVFS_WDATA8] = 0x12C,
592 [PWRAP_DVFS_ADR9] = 0x130,
593 [PWRAP_DVFS_WDATA9] = 0x134,
594 [PWRAP_DVFS_ADR10] = 0x138,
595 [PWRAP_DVFS_WDATA10] = 0x13C,
596 [PWRAP_DVFS_ADR11] = 0x140,
597 [PWRAP_DVFS_WDATA11] = 0x144,
598 [PWRAP_DVFS_ADR12] = 0x148,
599 [PWRAP_DVFS_WDATA12] = 0x14C,
600 [PWRAP_DVFS_ADR13] = 0x150,
601 [PWRAP_DVFS_WDATA13] = 0x154,
602 [PWRAP_DVFS_ADR14] = 0x158,
603 [PWRAP_DVFS_WDATA14] = 0x15C,
604 [PWRAP_DVFS_ADR15] = 0x160,
605 [PWRAP_DVFS_WDATA15] = 0x164,
606 [PWRAP_SPMINF_STA] = 0x168,
607 [PWRAP_CIPHER_KEY_SEL] = 0x16C,
608 [PWRAP_CIPHER_IV_SEL] = 0x170,
609 [PWRAP_CIPHER_EN] = 0x174,
610 [PWRAP_CIPHER_RDY] = 0x178,
611 [PWRAP_CIPHER_MODE] = 0x17C,
612 [PWRAP_CIPHER_SWRST] = 0x180,
613 [PWRAP_DCM_EN] = 0x184,
614 [PWRAP_DCM_DBC_PRD] = 0x188,
615 [PWRAP_EXT_CK] = 0x18C,
616 [PWRAP_ADC_CMD_ADDR] = 0x190,
617 [PWRAP_PWRAP_ADC_CMD] = 0x194,
618 [PWRAP_ADC_RDATA_ADDR] = 0x198,
619 [PWRAP_GPS_STA] = 0x19C,
620 [PWRAP_SW_RST] = 0x1A0,
621 [PWRAP_DVFS_STEP_CTRL0] = 0x238,
622 [PWRAP_DVFS_STEP_CTRL1] = 0x23C,
623 [PWRAP_DVFS_STEP_CTRL2] = 0x240,
624 [PWRAP_SPI2_CTRL] = 0x244,
625};
626
627static int mt8173_regs[] = {
628 [PWRAP_MUX_SEL] = 0x0,
629 [PWRAP_WRAP_EN] = 0x4,
630 [PWRAP_DIO_EN] = 0x8,
631 [PWRAP_SIDLY] = 0xc,
632 [PWRAP_RDDMY] = 0x10,
633 [PWRAP_SI_CK_CON] = 0x14,
634 [PWRAP_CSHEXT_WRITE] = 0x18,
635 [PWRAP_CSHEXT_READ] = 0x1c,
636 [PWRAP_CSLEXT_START] = 0x20,
637 [PWRAP_CSLEXT_END] = 0x24,
638 [PWRAP_STAUPD_PRD] = 0x28,
639 [PWRAP_STAUPD_GRPEN] = 0x2c,
640 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
641 [PWRAP_STAUPD_STA] = 0x44,
642 [PWRAP_WRAP_STA] = 0x48,
643 [PWRAP_HARB_INIT] = 0x4c,
644 [PWRAP_HARB_HPRIO] = 0x50,
645 [PWRAP_HIPRIO_ARB_EN] = 0x54,
646 [PWRAP_HARB_STA0] = 0x58,
647 [PWRAP_HARB_STA1] = 0x5c,
648 [PWRAP_MAN_EN] = 0x60,
649 [PWRAP_MAN_CMD] = 0x64,
650 [PWRAP_MAN_RDATA] = 0x68,
651 [PWRAP_MAN_VLDCLR] = 0x6c,
652 [PWRAP_WACS0_EN] = 0x70,
653 [PWRAP_INIT_DONE0] = 0x74,
654 [PWRAP_WACS0_CMD] = 0x78,
655 [PWRAP_WACS0_RDATA] = 0x7c,
656 [PWRAP_WACS0_VLDCLR] = 0x80,
657 [PWRAP_WACS1_EN] = 0x84,
658 [PWRAP_INIT_DONE1] = 0x88,
659 [PWRAP_WACS1_CMD] = 0x8c,
660 [PWRAP_WACS1_RDATA] = 0x90,
661 [PWRAP_WACS1_VLDCLR] = 0x94,
662 [PWRAP_WACS2_EN] = 0x98,
663 [PWRAP_INIT_DONE2] = 0x9c,
664 [PWRAP_WACS2_CMD] = 0xa0,
665 [PWRAP_WACS2_RDATA] = 0xa4,
666 [PWRAP_WACS2_VLDCLR] = 0xa8,
667 [PWRAP_INT_EN] = 0xac,
668 [PWRAP_INT_FLG_RAW] = 0xb0,
669 [PWRAP_INT_FLG] = 0xb4,
670 [PWRAP_INT_CLR] = 0xb8,
671 [PWRAP_SIG_ADR] = 0xbc,
672 [PWRAP_SIG_MODE] = 0xc0,
673 [PWRAP_SIG_VALUE] = 0xc4,
674 [PWRAP_SIG_ERRVAL] = 0xc8,
675 [PWRAP_CRC_EN] = 0xcc,
676 [PWRAP_TIMER_EN] = 0xd0,
677 [PWRAP_TIMER_STA] = 0xd4,
678 [PWRAP_WDT_UNIT] = 0xd8,
679 [PWRAP_WDT_SRC_EN] = 0xdc,
680 [PWRAP_WDT_FLG] = 0xe0,
681 [PWRAP_DEBUG_INT_SEL] = 0xe4,
682 [PWRAP_DVFS_ADR0] = 0xe8,
683 [PWRAP_DVFS_WDATA0] = 0xec,
684 [PWRAP_DVFS_ADR1] = 0xf0,
685 [PWRAP_DVFS_WDATA1] = 0xf4,
686 [PWRAP_DVFS_ADR2] = 0xf8,
687 [PWRAP_DVFS_WDATA2] = 0xfc,
688 [PWRAP_DVFS_ADR3] = 0x100,
689 [PWRAP_DVFS_WDATA3] = 0x104,
690 [PWRAP_DVFS_ADR4] = 0x108,
691 [PWRAP_DVFS_WDATA4] = 0x10c,
692 [PWRAP_DVFS_ADR5] = 0x110,
693 [PWRAP_DVFS_WDATA5] = 0x114,
694 [PWRAP_DVFS_ADR6] = 0x118,
695 [PWRAP_DVFS_WDATA6] = 0x11c,
696 [PWRAP_DVFS_ADR7] = 0x120,
697 [PWRAP_DVFS_WDATA7] = 0x124,
698 [PWRAP_SPMINF_STA] = 0x128,
699 [PWRAP_CIPHER_KEY_SEL] = 0x12c,
700 [PWRAP_CIPHER_IV_SEL] = 0x130,
701 [PWRAP_CIPHER_EN] = 0x134,
702 [PWRAP_CIPHER_RDY] = 0x138,
703 [PWRAP_CIPHER_MODE] = 0x13c,
704 [PWRAP_CIPHER_SWRST] = 0x140,
705 [PWRAP_DCM_EN] = 0x144,
706 [PWRAP_DCM_DBC_PRD] = 0x148,
707};
708
709static int mt8135_regs[] = {
710 [PWRAP_MUX_SEL] = 0x0,
711 [PWRAP_WRAP_EN] = 0x4,
712 [PWRAP_DIO_EN] = 0x8,
713 [PWRAP_SIDLY] = 0xc,
714 [PWRAP_CSHEXT] = 0x10,
715 [PWRAP_CSHEXT_WRITE] = 0x14,
716 [PWRAP_CSHEXT_READ] = 0x18,
717 [PWRAP_CSLEXT_START] = 0x1c,
718 [PWRAP_CSLEXT_END] = 0x20,
719 [PWRAP_STAUPD_PRD] = 0x24,
720 [PWRAP_STAUPD_GRPEN] = 0x28,
721 [PWRAP_STAUPD_MAN_TRIG] = 0x2c,
722 [PWRAP_STAUPD_STA] = 0x30,
723 [PWRAP_EVENT_IN_EN] = 0x34,
724 [PWRAP_EVENT_DST_EN] = 0x38,
725 [PWRAP_WRAP_STA] = 0x3c,
726 [PWRAP_RRARB_INIT] = 0x40,
727 [PWRAP_RRARB_EN] = 0x44,
728 [PWRAP_RRARB_STA0] = 0x48,
729 [PWRAP_RRARB_STA1] = 0x4c,
730 [PWRAP_HARB_INIT] = 0x50,
731 [PWRAP_HARB_HPRIO] = 0x54,
732 [PWRAP_HIPRIO_ARB_EN] = 0x58,
733 [PWRAP_HARB_STA0] = 0x5c,
734 [PWRAP_HARB_STA1] = 0x60,
735 [PWRAP_MAN_EN] = 0x64,
736 [PWRAP_MAN_CMD] = 0x68,
737 [PWRAP_MAN_RDATA] = 0x6c,
738 [PWRAP_MAN_VLDCLR] = 0x70,
739 [PWRAP_WACS0_EN] = 0x74,
740 [PWRAP_INIT_DONE0] = 0x78,
741 [PWRAP_WACS0_CMD] = 0x7c,
742 [PWRAP_WACS0_RDATA] = 0x80,
743 [PWRAP_WACS0_VLDCLR] = 0x84,
744 [PWRAP_WACS1_EN] = 0x88,
745 [PWRAP_INIT_DONE1] = 0x8c,
746 [PWRAP_WACS1_CMD] = 0x90,
747 [PWRAP_WACS1_RDATA] = 0x94,
748 [PWRAP_WACS1_VLDCLR] = 0x98,
749 [PWRAP_WACS2_EN] = 0x9c,
750 [PWRAP_INIT_DONE2] = 0xa0,
751 [PWRAP_WACS2_CMD] = 0xa4,
752 [PWRAP_WACS2_RDATA] = 0xa8,
753 [PWRAP_WACS2_VLDCLR] = 0xac,
754 [PWRAP_INT_EN] = 0xb0,
755 [PWRAP_INT_FLG_RAW] = 0xb4,
756 [PWRAP_INT_FLG] = 0xb8,
757 [PWRAP_INT_CLR] = 0xbc,
758 [PWRAP_SIG_ADR] = 0xc0,
759 [PWRAP_SIG_MODE] = 0xc4,
760 [PWRAP_SIG_VALUE] = 0xc8,
761 [PWRAP_SIG_ERRVAL] = 0xcc,
762 [PWRAP_CRC_EN] = 0xd0,
763 [PWRAP_EVENT_STA] = 0xd4,
764 [PWRAP_EVENT_STACLR] = 0xd8,
765 [PWRAP_TIMER_EN] = 0xdc,
766 [PWRAP_TIMER_STA] = 0xe0,
767 [PWRAP_WDT_UNIT] = 0xe4,
768 [PWRAP_WDT_SRC_EN] = 0xe8,
769 [PWRAP_WDT_FLG] = 0xec,
770 [PWRAP_DEBUG_INT_SEL] = 0xf0,
771 [PWRAP_CIPHER_KEY_SEL] = 0x134,
772 [PWRAP_CIPHER_IV_SEL] = 0x138,
773 [PWRAP_CIPHER_LOAD] = 0x13c,
774 [PWRAP_CIPHER_START] = 0x140,
775 [PWRAP_CIPHER_RDY] = 0x144,
776 [PWRAP_CIPHER_MODE] = 0x148,
777 [PWRAP_CIPHER_SWRST] = 0x14c,
778 [PWRAP_DCM_EN] = 0x15c,
779 [PWRAP_DCM_DBC_PRD] = 0x160,
780};
781
782enum pmic_type {
783 PMIC_MT6323,
784 PMIC_MT6351,
785 PMIC_MT6359,
786 PMIC_MT6380,
787 PMIC_MT6397,
788};
789
790enum pwrap_type {
791 PWRAP_MT2701,
792 PWRAP_MT6779,
793 PWRAP_MT6797,
794 PWRAP_MT7622,
795 PWRAP_MT8135,
796 PWRAP_MT8173,
797};
798
799struct pmic_wrapper;
800struct pwrap_slv_type {
801 const u32 *dew_regs;
802 enum pmic_type type;
803 const struct regmap_config *regmap;
804 /* Flags indicating the capability for the target slave */
805 u32 caps;
806 /*
807 * pwrap operations are highly associated with the PMIC types,
808 * so the pointers added increases flexibility allowing determination
809 * which type is used by the detection through device tree.
810 */
811 int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
812 int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
813};
814
815struct pmic_wrapper {
816 struct device *dev;
817 void __iomem *base;
818 struct regmap *regmap;
819 const struct pmic_wrapper_type *master;
820 const struct pwrap_slv_type *slave;
821 struct clk *clk_spi;
822 struct clk *clk_wrap;
823 struct clk *clk_ulposc;
824 struct reset_control *rstc;
825
826 struct reset_control *rstc_bridge;
827 void __iomem *bridge_base;
828};
829
830struct pmic_wrapper_type {
831 int *regs;
832 enum pwrap_type type;
833 u32 arb_en_all;
834 u32 int_en_all;
835 u32 int1_en_all;
836 u32 spi_w;
837 u32 wdt_src;
838 u32 caps;
839 unsigned int has_bridge:1;
840 int slv_switch:1;
841 int (*init_reg_clock)(struct pmic_wrapper *wrp);
842 int (*init_soc_specific)(struct pmic_wrapper *wrp);
843};
844
845static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg);
846static void pwrap_writel(struct pmic_wrapper *wrp, u32 val,
847 enum pwrap_regs reg);
848static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
849static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
850
851static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
852{
853 return readl(wrp->base + wrp->master->regs[reg]);
854}
855
856static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
857{
858 writel(val, wrp->base + wrp->master->regs[reg]);
859}
860
861static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
862{
863 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
864
865 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE;
866}
867
868static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
869{
870 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
871
872 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
873}
874
875/*
876 * Timeout issue sometimes caused by the last read command
877 * failed because pmic wrap could not got the FSM_VLDCLR
878 * in time after finishing WACS2_CMD. It made state machine
879 * still on FSM_VLDCLR and timeout next time.
880 * Check the status of FSM and clear the vldclr to recovery the
881 * error.
882 */
883static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)
884{
885 if (pwrap_is_fsm_vldclr(wrp))
886 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
887}
888
889static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
890{
891 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
892}
893
894static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
895{
896 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
897
898 return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
899 (val & PWRAP_STATE_SYNC_IDLE0);
900}
901
902static int pwrap_timeout_ns(unsigned long long start_time_ns,
903 unsigned long long timeout_time_ns, struct pmic_wrapper *wrp)
904{
905 unsigned long long cur_time;
906 unsigned long long elapse_time;
907
908 /* get current tick */
909 cur_time = sched_clock(); /* ns */
910
911 elapse_time = cur_time - start_time_ns;
912
913 /* check if timeout */
914 if (timeout_time_ns <= elapse_time) {
915 dev_dbg(wrp->dev,
916 "[PWRAP] Timeout start time: %lld\n", start_time_ns);
917 dev_dbg(wrp->dev,
918 "[PWRAP] Timeout cur time: %lld\n", cur_time);
919 dev_dbg(wrp->dev,
920 "[PWRAP] Timeout elapse time: %lld\n", elapse_time);
921 dev_dbg(wrp->dev,
922 "[PWRAP] Timeout set timeout: %lld\n", timeout_time_ns);
923 return 1;
924 }
925 return 0;
926}
927
928static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
929 bool (*fp)(struct pmic_wrapper *))
930{
931 unsigned long long start_time_ns, timeout_ns;
932
933 start_time_ns = sched_clock();
934 timeout_ns = 10000 * 1000; /* 10000us */
935
936 do {
937 if (fp(wrp))
938 return 0;
939 if (pwrap_timeout_ns(start_time_ns, timeout_ns, wrp)) {
940 if (fp(wrp) == 0) {
941 dev_dbg(wrp->dev, "[PWRAP] FSM Timeout\n");
942 return -ETIMEDOUT;
943 }
944 }
945
946 } while (1);
947}
948
949static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
950{
951 int ret;
952
953 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
954 if (ret) {
955 pwrap_leave_fsm_vldclr(wrp);
956 return ret;
957 }
958
959 pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
960
961 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
962 if (ret)
963 return ret;
964
965 *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
966
967 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
968
969 return 0;
970}
971
972static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
973{
974 int ret, msb;
975
976 *rdata = 0;
977 for (msb = 0; msb < 2; msb++) {
978 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
979 if (ret) {
980 pwrap_leave_fsm_vldclr(wrp);
981 return ret;
982 }
983
984 pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
985 PWRAP_WACS2_CMD);
986
987 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
988 if (ret)
989 return ret;
990
991 *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
992 PWRAP_WACS2_RDATA)) << (16 * msb));
993
994 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
995 }
996
997 return 0;
998}
999
1000static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1001{
1002 return wrp->slave->pwrap_read(wrp, adr, rdata);
1003}
1004
1005static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1006{
1007 int ret;
1008
1009 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1010 if (ret) {
1011 pwrap_leave_fsm_vldclr(wrp);
1012 return ret;
1013 }
1014
1015 pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
1016 PWRAP_WACS2_CMD);
1017
1018 return 0;
1019}
1020
1021static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1022{
1023 int ret, msb, rdata;
1024
1025 for (msb = 0; msb < 2; msb++) {
1026 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1027 if (ret) {
1028 pwrap_leave_fsm_vldclr(wrp);
1029 return ret;
1030 }
1031
1032 pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
1033 ((wdata >> (msb * 16)) & 0xffff),
1034 PWRAP_WACS2_CMD);
1035
1036 /*
1037 * The pwrap_read operation is the requirement of hardware used
1038 * for the synchronization between two successive 16-bit
1039 * pwrap_writel operations composing one 32-bit bus writing.
1040 * Otherwise, we'll find the result fails on the lower 16-bit
1041 * pwrap writing.
1042 */
1043 if (!msb)
1044 pwrap_read(wrp, adr, &rdata);
1045 }
1046
1047 return 0;
1048}
1049
1050static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1051{
1052 return wrp->slave->pwrap_write(wrp, adr, wdata);
1053}
1054
1055static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
1056{
1057 return pwrap_read(context, adr, rdata);
1058}
1059
1060static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
1061{
1062 return pwrap_write(context, adr, wdata);
1063}
1064
1065static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
1066{
1067 int ret, i;
1068
1069 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
1070 pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
1071 pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
1072 pwrap_writel(wrp, 1, PWRAP_MAN_EN);
1073 pwrap_writel(wrp, 0, PWRAP_DIO_EN);
1074
1075 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,
1076 PWRAP_MAN_CMD);
1077 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1078 PWRAP_MAN_CMD);
1079 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,
1080 PWRAP_MAN_CMD);
1081
1082 for (i = 0; i < 4; i++)
1083 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1084 PWRAP_MAN_CMD);
1085
1086 ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
1087 if (ret) {
1088 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1089 return ret;
1090 }
1091
1092 pwrap_writel(wrp, 0, PWRAP_MAN_EN);
1093 pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
1094
1095 return 0;
1096}
1097
1098/*
1099 * pwrap_init_sidly - configure serial input delay
1100 *
1101 * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
1102 * delay. Do a read test with all possible values and chose the best delay.
1103 */
1104static int pwrap_init_sidly(struct pmic_wrapper *wrp)
1105{
1106 u32 i;
1107 u32 pass = 0, rdata = 0;
1108 signed char dly[16] = {
1109 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
1110 };
1111
1112 for (i = 0; i < 4; i++) {
1113 pwrap_writel(wrp, i, PWRAP_SIDLY);
1114 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
1115 &rdata);
1116 if (rdata == PWRAP_DEW_READ_TEST_VAL) {
1117 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
1118 pass |= 1 << i;
1119 }
1120 }
1121
1122 if (dly[pass] < 0) {
1123 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
1124 pass);
1125 return -EIO;
1126 }
1127
1128 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
1129
1130 return 0;
1131}
1132
1133static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
1134{
1135 int ret;
1136 u32 rdata = 0;
1137
1138 /* Enable dual IO mode */
1139 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
1140
1141 /* Check IDLE & INIT_DONE in advance */
1142 ret = pwrap_wait_for_state(wrp,
1143 pwrap_is_fsm_idle_and_sync_idle);
1144 if (ret) {
1145 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1146 return ret;
1147 }
1148
1149 pwrap_writel(wrp, 1, PWRAP_DIO_EN);
1150
1151 /* Read Test */
1152 pwrap_read(wrp,
1153 wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
1154 if (rdata != PWRAP_DEW_READ_TEST_VAL) {
1155 dev_err(wrp->dev,
1156 "Read failed on DIO mode: 0x%04x!=0x%04x\n",
1157 PWRAP_DEW_READ_TEST_VAL, rdata);
1158 return -EFAULT;
1159 }
1160
1161 return 0;
1162}
1163
1164/*
1165 * pwrap_init_chip_select_ext is used to configure CS extension time for each
1166 * phase during data transactions on the pwrap bus.
1167 */
1168static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
1169 u8 hext_read, u8 lext_start,
1170 u8 lext_end)
1171{
1172 /*
1173 * After finishing a write and read transaction, extends CS high time
1174 * to be at least xT of BUS CLK as hext_write and hext_read specifies
1175 * respectively.
1176 */
1177 pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
1178 pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
1179
1180 /*
1181 * Extends CS low time after CSL and before CSH command to be at
1182 * least xT of BUS CLK as lext_start and lext_end specifies
1183 * respectively.
1184 */
1185 pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
1186 pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
1187}
1188
1189static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
1190{
1191 switch (wrp->master->type) {
1192 case PWRAP_MT6779:
1193 pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
1194 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], 0x8);
1195 pwrap_init_chip_select_ext(wrp, 0x88, 0x55, 3, 0);
1196 break;
1197 case PWRAP_MT8173:
1198 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
1199 break;
1200 case PWRAP_MT8135:
1201 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
1202 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
1203 break;
1204 default:
1205 break;
1206 }
1207
1208 return 0;
1209}
1210
1211static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
1212{
1213 switch (wrp->slave->type) {
1214 case PMIC_MT6397:
1215 pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
1216 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
1217 break;
1218
1219 case PMIC_MT6323:
1220 pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
1221 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], 0x8);
1222 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
1223 break;
1224 default:
1225 break;
1226 }
1227
1228 return 0;
1229}
1230
1231static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
1232{
1233 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
1234}
1235
1236static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
1237{
1238 int ret;
1239 u32 rdata = 0;
1240
1241 ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
1242 &rdata);
1243 if (ret)
1244 return 0;
1245
1246 return rdata == 1;
1247}
1248
1249static int pwrap_init_cipher(struct pmic_wrapper *wrp)
1250{
1251 int ret;
1252 u32 rdata = 0;
1253
1254 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
1255 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
1256 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
1257 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
1258
1259 switch (wrp->master->type) {
1260 case PWRAP_MT8135:
1261 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
1262 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
1263 break;
1264 case PWRAP_MT2701:
1265 case PWRAP_MT6779:
1266 case PWRAP_MT6797:
1267 case PWRAP_MT8173:
1268 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
1269 break;
1270 case PWRAP_MT7622:
1271 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
1272 break;
1273 default:
1274 break;
1275 }
1276
1277 /* Config cipher mode @PMIC */
1278 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
1279 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
1280 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
1281 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
1282
1283 switch (wrp->slave->type) {
1284 case PMIC_MT6397:
1285 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],
1286 0x1);
1287 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],
1288 0x1);
1289 break;
1290 case PMIC_MT6323:
1291 case PMIC_MT6351:
1292 case PMIC_MT6359:
1293 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
1294 0x1);
1295 break;
1296 default:
1297 break;
1298 }
1299
1300 /* wait for cipher data ready@AP */
1301 ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
1302 if (ret) {
1303 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
1304 return ret;
1305 }
1306
1307 /* wait for cipher data ready@PMIC */
1308 ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
1309 if (ret) {
1310 dev_err(wrp->dev,
1311 "timeout waiting for cipher data ready@PMIC\n");
1312 return ret;
1313 }
1314
1315 /* wait for cipher mode idle */
1316 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
1317 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
1318 if (ret) {
1319 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
1320 return ret;
1321 }
1322
1323 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
1324
1325 /* Write Test */
1326 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1327 PWRAP_DEW_WRITE_TEST_VAL) ||
1328 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1329 &rdata) ||
1330 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
1331 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
1332 return -EFAULT;
1333 }
1334
1335 return 0;
1336}
1337
1338static int pwrap_init_security(struct pmic_wrapper *wrp)
1339{
1340 int ret;
1341
1342 /* Enable encryption */
1343 ret = pwrap_init_cipher(wrp);
1344 if (ret)
1345 return ret;
1346
1347 /* Signature checking - using CRC */
1348 if (pwrap_write(wrp,
1349 wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
1350 return -EFAULT;
1351
1352 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
1353 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
1354 pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
1355 PWRAP_SIG_ADR);
1356 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1357
1358 return 0;
1359}
1360
1361static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
1362{
1363 /* enable pwrap events and pwrap bridge in AP side */
1364 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
1365 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
1366 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
1367 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
1368 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
1369 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
1370 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
1371 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
1372 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
1373
1374 /* enable PMIC event out and sources */
1375 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1376 0x1) ||
1377 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1378 0xffff)) {
1379 dev_err(wrp->dev, "enable dewrap fail\n");
1380 return -EFAULT;
1381 }
1382
1383 return 0;
1384}
1385
1386static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
1387{
1388 /* PMIC_DEWRAP enables */
1389 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1390 0x1) ||
1391 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1392 0xffff)) {
1393 dev_err(wrp->dev, "enable dewrap fail\n");
1394 return -EFAULT;
1395 }
1396
1397 return 0;
1398}
1399
1400static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
1401{
1402 /* GPS_INTF initialization */
1403 switch (wrp->slave->type) {
1404 case PMIC_MT6323:
1405 pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
1406 pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
1407 pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
1408 pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
1409 pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
1410 break;
1411 default:
1412 break;
1413 }
1414
1415 return 0;
1416}
1417
1418static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
1419{
1420 pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
1421 /* enable 2wire SPI master */
1422 pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
1423
1424 return 0;
1425}
1426
1427static int pwrap_init(struct pmic_wrapper *wrp)
1428{
1429 int ret;
1430
1431 reset_control_reset(wrp->rstc);
1432 if (wrp->rstc_bridge)
1433 reset_control_reset(wrp->rstc_bridge);
1434
1435 if (wrp->master->type == PWRAP_MT8173) {
1436 /* Enable DCM */
1437 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
1438 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
1439 }
1440
1441 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1442 /* Reset SPI slave */
1443 ret = pwrap_reset_spislave(wrp);
1444 if (ret)
1445 return ret;
1446 }
1447
1448 pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
1449
1450 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1451
1452 pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
1453
1454 ret = wrp->master->init_reg_clock(wrp);
1455 if (ret)
1456 return ret;
1457
1458 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1459 /* Setup serial input delay */
1460 ret = pwrap_init_sidly(wrp);
1461 if (ret)
1462 return ret;
1463 }
1464
1465 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
1466 /* Enable dual I/O mode */
1467 ret = pwrap_init_dual_io(wrp);
1468 if (ret)
1469 return ret;
1470 }
1471
1472 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
1473 /* Enable security on bus */
1474 ret = pwrap_init_security(wrp);
1475 if (ret)
1476 return ret;
1477 }
1478
1479 if (wrp->master->type == PWRAP_MT8135)
1480 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
1481
1482 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
1483 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
1484 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
1485 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_MONITOR_V2))
1486 pwrap_writel(wrp, 0x1, PWRAP_WACS3_EN);
1487
1488 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
1489 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
1490
1491 if (wrp->master->init_soc_specific) {
1492 ret = wrp->master->init_soc_specific(wrp);
1493 if (ret)
1494 return ret;
1495 }
1496
1497 /* Setup the init done registers */
1498 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
1499 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
1500 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
1501 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_MONITOR_V2))
1502 pwrap_writel(wrp, 1, PWRAP_INIT_DONE3);
1503
1504 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
1505 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
1506 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
1507 }
1508
1509 return 0;
1510}
1511
1512static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
1513{
1514 u32 rdata, int0_flg, int1_flg;
1515 struct pmic_wrapper *wrp = dev_id;
1516
1517 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
1518 int0_flg = pwrap_readl(wrp, PWRAP_INT0_FLG);
1519 if (int0_flg) {
1520 dev_notice(wrp->dev,
1521 "[PWRAP] INT0 error:0x%x\n", int0_flg);
1522 pwrap_writel(wrp, int0_flg, PWRAP_INT0_CLR);
1523 }
1524 int1_flg = pwrap_readl(wrp, PWRAP_INT1_FLG);
1525 if (int1_flg) {
1526 dev_notice(wrp->dev,
1527 "[PWRAP] INT1 error:0x%x\n", int1_flg);
1528 pwrap_writel(wrp, int1_flg, PWRAP_INT1_CLR);
1529 }
1530 } else {
1531 rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
1532 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
1533 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
1534 }
1535
1536 return IRQ_HANDLED;
1537}
1538
1539static const struct regmap_config pwrap_regmap_config16 = {
1540 .reg_bits = 16,
1541 .val_bits = 16,
1542 .reg_stride = 2,
1543 .reg_read = pwrap_regmap_read,
1544 .reg_write = pwrap_regmap_write,
1545 .max_register = 0xffff,
1546};
1547
1548static const struct regmap_config pwrap_regmap_config32 = {
1549 .reg_bits = 32,
1550 .val_bits = 32,
1551 .reg_stride = 4,
1552 .reg_read = pwrap_regmap_read,
1553 .reg_write = pwrap_regmap_write,
1554 .max_register = 0xffff,
1555};
1556
1557static const struct pwrap_slv_type pmic_mt6323 = {
1558 .dew_regs = mt6323_regs,
1559 .type = PMIC_MT6323,
1560 .regmap = &pwrap_regmap_config16,
1561 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
1562 PWRAP_SLV_CAP_SECURITY,
1563 .pwrap_read = pwrap_read16,
1564 .pwrap_write = pwrap_write16,
1565};
1566
1567static const struct pwrap_slv_type pmic_mt6380 = {
1568 .dew_regs = NULL,
1569 .type = PMIC_MT6380,
1570 .regmap = &pwrap_regmap_config32,
1571 .caps = 0,
1572 .pwrap_read = pwrap_read32,
1573 .pwrap_write = pwrap_write32,
1574};
1575
1576static const struct pwrap_slv_type pmic_mt6397 = {
1577 .dew_regs = mt6397_regs,
1578 .type = PMIC_MT6397,
1579 .regmap = &pwrap_regmap_config16,
1580 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
1581 PWRAP_SLV_CAP_SECURITY,
1582 .pwrap_read = pwrap_read16,
1583 .pwrap_write = pwrap_write16,
1584};
1585
1586static const struct pwrap_slv_type pmic_mt6351 = {
1587 .dew_regs = mt6351_regs,
1588 .type = PMIC_MT6351,
1589 .regmap = &pwrap_regmap_config16,
1590 .caps = 0,
1591 .pwrap_read = pwrap_read16,
1592 .pwrap_write = pwrap_write16,
1593};
1594
1595static const struct pwrap_slv_type pmic_mt6359 = {
1596 .dew_regs = mt6359_regs,
1597 .type = PMIC_MT6359,
1598 .regmap = &pwrap_regmap_config16,
1599 .caps = 0,
1600 .pwrap_read = pwrap_read16,
1601 .pwrap_write = pwrap_write16,
1602};
1603
1604static const struct of_device_id of_slave_match_tbl[] = {
1605 {
1606 .compatible = "mediatek,mt6323",
1607 .data = &pmic_mt6323,
1608 }, {
1609 /* The MT6380 PMIC only implements a regulator, so we bind it
1610 * directly instead of using a MFD.
1611 */
1612 .compatible = "mediatek,mt6380-regulator",
1613 .data = &pmic_mt6380,
1614 }, {
1615 .compatible = "mediatek,mt6397",
1616 .data = &pmic_mt6397,
1617 }, {
1618 .compatible = "mediatek,mt6351",
1619 .data = &pmic_mt6351,
1620 }, {
1621 .compatible = "mediatek,mt6359",
1622 .data = &pmic_mt6359,
1623 }, {
1624 /* sentinel */
1625 }
1626};
1627MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
1628
1629static const struct pmic_wrapper_type pwrap_mt2701 = {
1630 .regs = mt2701_regs,
1631 .type = PWRAP_MT2701,
1632 .arb_en_all = 0x3f,
1633 .int_en_all = ~(u32)(BIT(31) | BIT(2)),
1634 .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
1635 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1636 .has_bridge = 0,
1637 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1638 .slv_switch = 1,
1639 .init_reg_clock = pwrap_mt2701_init_reg_clock,
1640 .init_soc_specific = pwrap_mt2701_init_soc_specific,
1641};
1642
1643static const struct pmic_wrapper_type pwrap_mt6779 = {
1644 .regs = mt6779_regs,
1645 .type = PWRAP_MT6779,
1646 .arb_en_all = 0xfbb7f,
1647 .int_en_all = 0xffffffff,
1648 .int1_en_all = 0x000017ff,
1649 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1650 .wdt_src = 0x4000, /* only for MD DVFS HW */
1651 .has_bridge = 0,
1652 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_MONITOR_V2 | PWRAP_CAP_ULPOSC_CLK,
1653 .slv_switch = 0,
1654 .init_reg_clock = pwrap_common_init_reg_clock,
1655 .init_soc_specific = NULL,
1656};
1657
1658static const struct pmic_wrapper_type pwrap_mt6797 = {
1659 .regs = mt6797_regs,
1660 .type = PWRAP_MT6797,
1661 .arb_en_all = 0x01fff,
1662 .int_en_all = 0xffffffc6,
1663 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1664 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1665 .has_bridge = 0,
1666 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1667 .init_reg_clock = pwrap_common_init_reg_clock,
1668 .init_soc_specific = NULL,
1669};
1670
1671static const struct pmic_wrapper_type pwrap_mt7622 = {
1672 .regs = mt7622_regs,
1673 .type = PWRAP_MT7622,
1674 .arb_en_all = 0xff,
1675 .int_en_all = ~(u32)BIT(31),
1676 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1677 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1678 .has_bridge = 0,
1679 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1680 .init_reg_clock = pwrap_common_init_reg_clock,
1681 .init_soc_specific = pwrap_mt7622_init_soc_specific,
1682};
1683
1684static const struct pmic_wrapper_type pwrap_mt8135 = {
1685 .regs = mt8135_regs,
1686 .type = PWRAP_MT8135,
1687 .arb_en_all = 0x1ff,
1688 .int_en_all = ~(u32)(BIT(31) | BIT(1)),
1689 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1690 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1691 .has_bridge = 1,
1692 .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1693 .slv_switch = 0,
1694 .init_reg_clock = pwrap_common_init_reg_clock,
1695 .init_soc_specific = pwrap_mt8135_init_soc_specific,
1696};
1697
1698static const struct pmic_wrapper_type pwrap_mt8173 = {
1699 .regs = mt8173_regs,
1700 .type = PWRAP_MT8173,
1701 .arb_en_all = 0x3f,
1702 .int_en_all = ~(u32)(BIT(31) | BIT(1)),
1703 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1704 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
1705 .has_bridge = 0,
1706 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1707 .slv_switch = 0,
1708 .init_reg_clock = pwrap_common_init_reg_clock,
1709 .init_soc_specific = pwrap_mt8173_init_soc_specific,
1710};
1711
1712static const struct of_device_id of_pwrap_match_tbl[] = {
1713 {
1714 .compatible = "mediatek,mt2701-pwrap",
1715 .data = &pwrap_mt2701,
1716 }, {
1717 .compatible = "mediatek,mt6779-pwrap",
1718 .data = &pwrap_mt6779,
1719 }, {
1720 .compatible = "mediatek,mt6797-pwrap",
1721 .data = &pwrap_mt6797,
1722 }, {
1723 .compatible = "mediatek,mt7622-pwrap",
1724 .data = &pwrap_mt7622,
1725 }, {
1726 .compatible = "mediatek,mt8135-pwrap",
1727 .data = &pwrap_mt8135,
1728 }, {
1729 .compatible = "mediatek,mt8173-pwrap",
1730 .data = &pwrap_mt8173,
1731 }, {
1732 /* sentinel */
1733 }
1734};
1735MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
1736
1737static int pwrap_probe(struct platform_device *pdev)
1738{
1739 int ret, irq;
1740 u32 rdata;
1741 struct pmic_wrapper *wrp;
1742 struct device_node *np = pdev->dev.of_node;
1743 const struct of_device_id *of_slave_id = NULL;
1744 struct resource *res;
1745
1746 if (np->child)
1747 of_slave_id = of_match_node(of_slave_match_tbl, np->child);
1748
1749 if (!of_slave_id) {
1750 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
1751 return -EINVAL;
1752 }
1753
1754 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
1755 if (!wrp)
1756 return -ENOMEM;
1757
1758 platform_set_drvdata(pdev, wrp);
1759
1760 wrp->master = of_device_get_match_data(&pdev->dev);
1761 wrp->slave = of_slave_id->data;
1762 wrp->dev = &pdev->dev;
1763
1764 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
1765 wrp->base = devm_ioremap_resource(wrp->dev, res);
1766 if (IS_ERR(wrp->base))
1767 return PTR_ERR(wrp->base);
1768
1769 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {
1770 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
1771 if (IS_ERR(wrp->rstc)) {
1772 ret = PTR_ERR(wrp->rstc);
1773 dev_dbg(wrp->dev,
1774 "cannot get pwrap reset: %d\n", ret);
1775 return ret;
1776 }
1777 }
1778
1779 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
1780 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1781 "pwrap-bridge");
1782 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
1783 if (IS_ERR(wrp->bridge_base))
1784 return PTR_ERR(wrp->bridge_base);
1785
1786 wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
1787 "pwrap-bridge");
1788 if (IS_ERR(wrp->rstc_bridge)) {
1789 ret = PTR_ERR(wrp->rstc_bridge);
1790 dev_dbg(wrp->dev,
1791 "cannot get pwrap-bridge reset: %d\n", ret);
1792 return ret;
1793 }
1794 }
1795
1796 wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
1797 if (IS_ERR(wrp->clk_spi)) {
1798 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
1799 PTR_ERR(wrp->clk_spi));
1800 return PTR_ERR(wrp->clk_spi);
1801 }
1802
1803 wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
1804 if (IS_ERR(wrp->clk_wrap)) {
1805 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
1806 PTR_ERR(wrp->clk_wrap));
1807 return PTR_ERR(wrp->clk_wrap);
1808 }
1809
1810 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ULPOSC_CLK)) {
1811 wrp->clk_ulposc = devm_clk_get(wrp->dev, "ulposc");
1812 if (IS_ERR(wrp->clk_ulposc)) {
1813 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
1814 PTR_ERR(wrp->clk_ulposc));
1815 return PTR_ERR(wrp->clk_ulposc);
1816 }
1817 }
1818
1819 ret = clk_prepare_enable(wrp->clk_spi);
1820 if (ret)
1821 return ret;
1822
1823 ret = clk_prepare_enable(wrp->clk_wrap);
1824 if (ret)
1825 goto err_out1;
1826
1827 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ULPOSC_CLK)) {
1828 ret = clk_prepare_enable(wrp->clk_ulposc);
1829 if (ret)
1830 goto err_out2;
1831 }
1832
1833 /* Enable internal dynamic clock */
1834 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {
1835 pwrap_writel(wrp, 1, PWRAP_DCM_EN);
1836 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
1837 }
1838
1839 /*
1840 * The PMIC could already be initialized by the bootloader.
1841 * Skip initialization here in this case.
1842 */
1843 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
1844 ret = pwrap_init(wrp);
1845 if (ret) {
1846 dev_dbg(wrp->dev, "init failed with %d\n", ret);
1847 goto err_out2;
1848 }
1849 }
1850
1851 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) {
1852 dev_dbg(wrp->dev, "initialization isn't finished\n");
1853 ret = -ENODEV;
1854 goto err_out2;
1855 }
1856
1857 /* Initialize watchdog, may not be done by the bootloader */
1858 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_MONITOR_V2))
1859 pwrap_writel(wrp, 0x3f, PWRAP_WDT_CTRL);
1860 else
1861 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
1862
1863 /*
1864 * Since STAUPD was not used on mt8173 platform,
1865 * so STAUPD of WDT_SRC which should be turned off
1866 */
1867 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
1868
1869 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_MONITOR_V2))
1870 pwrap_writel(wrp, 0x1, PWRAP_TIMER_CTRL);
1871 else
1872 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
1873
1874 pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
1875
1876 /*
1877 * We add INT1 interrupt to handle starvation and request exception
1878 * If we support it, we should enable them here.
1879 */
1880 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
1881 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
1882
1883 irq = platform_get_irq(pdev, 0);
1884 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
1885 IRQF_TRIGGER_HIGH, "mt-pmic-pwrap", wrp);
1886 if (ret)
1887 goto err_out2;
1888
1889 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap);
1890 if (IS_ERR(wrp->regmap)) {
1891 ret = PTR_ERR(wrp->regmap);
1892 goto err_out2;
1893 }
1894
1895 /* Write Test */
1896 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_MONITOR_V2)) {
1897 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1898 PWRAP_DEW_WRITE_TEST_VAL) ||
1899 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1900 &rdata) ||
1901 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
1902 dev_notice(wrp->dev,
1903 "[PWRAP] Write Test fail, rdata=0x%x\n", rdata);
1904 goto err_out2;
1905 } else {
1906 dev_notice(wrp->dev, "[PWRAP] Write Test pass\n");
1907 }
1908 }
1909
1910 ret = of_platform_populate(np, NULL, NULL, wrp->dev);
1911 if (ret) {
1912 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n",
1913 np);
1914 goto err_out2;
1915 }
1916
1917 return 0;
1918
1919err_out2:
1920 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ULPOSC_CLK))
1921 clk_disable_unprepare(wrp->clk_ulposc);
1922 clk_disable_unprepare(wrp->clk_wrap);
1923err_out1:
1924 clk_disable_unprepare(wrp->clk_spi);
1925
1926 return ret;
1927}
1928
1929static struct platform_driver pwrap_drv = {
1930 .driver = {
1931 .name = "mt-pmic-pwrap",
1932 .of_match_table = of_match_ptr(of_pwrap_match_tbl),
1933 },
1934 .probe = pwrap_probe,
1935};
1936
1937module_platform_driver(pwrap_drv);
1938
1939MODULE_AUTHOR("Flora Fu, MediaTek");
1940MODULE_DESCRIPTION("MediaTek PMIC Wrapper Driver");
1941MODULE_LICENSE("GPL v2");