| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2018 MediaTek Inc. |
| 4 | * Author: Owen Chen <owen.chen@mediatek.com> |
| 5 | */ |
| 6 | #ifndef __DRV_CLK_MTK_MUX_H |
| 7 | #define __DRV_CLK_MTK_MUX_H |
| 8 | #include <linux/clk-provider.h> |
| 9 | struct mtk_clk_mux { |
| 10 | struct clk_hw hw; |
| 11 | struct regmap *regmap; |
| 12 | const char *name; |
| 13 | u32 mux_ofs; |
| 14 | u32 set_ofs; |
| 15 | u32 clr_ofs; |
| 16 | u32 upd_ofs; |
| 17 | s8 mux_shift; |
| 18 | s8 mux_width; |
| 19 | s8 gate_shift; |
| 20 | s8 upd_shift; |
| 21 | spinlock_t *lock; |
| 22 | }; |
| 23 | struct mtk_mux { |
| 24 | int id; |
| 25 | const char *name; |
| 26 | const char * const *parent_names; |
| 27 | unsigned int flags; |
| 28 | u32 mux_ofs; |
| 29 | u32 set_ofs; |
| 30 | u32 clr_ofs; |
| 31 | u32 upd_ofs; |
| 32 | s8 mux_shift; |
| 33 | s8 mux_width; |
| 34 | s8 gate_shift; |
| 35 | s8 upd_shift; |
| 36 | const struct clk_ops *ops; |
| 37 | s8 num_parents; |
| 38 | }; |
| 39 | extern const struct clk_ops mtk_mux_ops; |
| 40 | extern const struct clk_ops mtk_mux_clr_set_upd_ops; |
| 41 | extern const struct clk_ops mtk_mux_gate_ops; |
| 42 | extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops; |
| 43 | #define CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ |
| 44 | _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ |
| 45 | _gate, _upd_ofs, _upd, _flags, _ops) { \ |
| 46 | .id = _id, \ |
| 47 | .name = _name, \ |
| 48 | .mux_ofs = _mux_ofs, \ |
| 49 | .set_ofs = _mux_set_ofs, \ |
| 50 | .clr_ofs = _mux_clr_ofs, \ |
| 51 | .upd_ofs = _upd_ofs, \ |
| 52 | .mux_shift = _shift, \ |
| 53 | .mux_width = _width, \ |
| 54 | .gate_shift = _gate, \ |
| 55 | .upd_shift = _upd, \ |
| 56 | .parent_names = _parents, \ |
| 57 | .num_parents = ARRAY_SIZE(_parents), \ |
| 58 | .flags = _flags, \ |
| 59 | .ops = &_ops, \ |
| 60 | } |
| 61 | #define MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ |
| 62 | _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ |
| 63 | _gate, _upd_ofs, _upd, _flags) \ |
| 64 | CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ |
| 65 | _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ |
| 66 | _gate, _upd_ofs, _upd, _flags, \ |
| 67 | mtk_mux_gate_clr_set_upd_ops) |
| 68 | #define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ |
| 69 | _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ |
| 70 | _gate, _upd_ofs, _upd) \ |
| 71 | MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ |
| 72 | _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \ |
| 73 | _width, _gate, _upd_ofs, _upd, \ |
| 74 | CLK_SET_RATE_PARENT) |
| 75 | struct clk *mtk_clk_register_mux(const struct mtk_mux *mux, |
| 76 | struct regmap *regmap, |
| 77 | spinlock_t *lock); |
| 78 | int mtk_clk_register_muxes(const struct mtk_mux *muxes, |
| 79 | int num, struct device_node *node, |
| 80 | spinlock_t *lock, |
| 81 | struct clk_onecell_data *clk_data); |
| 82 | #endif /* __DRV_CLK_MTK_MUX_H */ |