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192.168.1.100 / T800 / 0d39e2882fcbf0ce09515d03111a6fe9e7fd5fe2 / . / src / kernel / linux / v4.19 / sound / soc / codecs / mt6359.c
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xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2//
3// mt6359.c -- mt6359 ALSA SoC audio codec driver
4//
5// Copyright (c) 2018 MediaTek Inc.
6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7#include <linux/platform_device.h>
8#include <linux/module.h>
9#include <linux/of_device.h>
10#include <linux/delay.h>
11#include <linux/debugfs.h>
12#include <linux/kthread.h>
13#include <linux/sched.h>
14
15#include <linux/mfd/mt6397/core.h>
16#include <linux/regulator/consumer.h>
17#include <sound/tlv.h>
18#include <sound/soc.h>
19#include "mt6359.h"
20
21enum {
22 MT6359_AIF_1 = 0, /* dl: hp, rcv, hp+lo */
23 MT6359_AIF_2, /* dl: lo only */
24 MT6359_AIF_VOW,
25 MT6359_AIF_NUM,
26};
27
28enum {
29 AUDIO_ANALOG_VOLUME_HSOUTL,
30 AUDIO_ANALOG_VOLUME_HSOUTR,
31 AUDIO_ANALOG_VOLUME_HPOUTL,
32 AUDIO_ANALOG_VOLUME_HPOUTR,
33 AUDIO_ANALOG_VOLUME_LINEOUTL,
34 AUDIO_ANALOG_VOLUME_LINEOUTR,
35 AUDIO_ANALOG_VOLUME_MICAMP1,
36 AUDIO_ANALOG_VOLUME_MICAMP2,
37 AUDIO_ANALOG_VOLUME_MICAMP3,
38 AUDIO_ANALOG_VOLUME_TYPE_MAX
39};
40
41enum {
42 MUX_MIC_TYPE_0, /* ain0, micbias 0 */
43 MUX_MIC_TYPE_1, /* ain1, micbias 1 */
44 MUX_MIC_TYPE_2, /* ain2/3, micbias 2 */
45 MUX_PGA_L,
46 MUX_PGA_R,
47 MUX_PGA_3,
48 MUX_HP_L,
49 MUX_HP_R,
50 MUX_NUM,
51};
52
53enum {
54 DEVICE_HP,
55 DEVICE_LO,
56 DEVICE_RCV,
57 DEVICE_MIC1,
58 DEVICE_MIC2,
59 DEVICE_NUM
60};
61
62enum {
63 HP_GAIN_CTL_ZCD = 0,
64 HP_GAIN_CTL_NLE,
65 HP_GAIN_CTL_NUM,
66};
67
68/* Supply widget subseq */
69enum {
70 /* common */
71 SUPPLY_SEQ_CLK_BUF,
72 SUPPLY_SEQ_LDO_VAUD18,
73 SUPPLY_SEQ_AUD_GLB,
74 SUPPLY_SEQ_AUD_GLB_VOW,
75 SUPPLY_SEQ_DL_GPIO,
76 SUPPLY_SEQ_UL_GPIO,
77 SUPPLY_SEQ_HP_PULL_DOWN,
78 SUPPLY_SEQ_CLKSQ,
79 SUPPLY_SEQ_ADC_CLKGEN,
80 SUPPLY_SEQ_VOW_AUD_LPW,
81 SUPPLY_SEQ_AUD_VOW,
82 SUPPLY_SEQ_VOW_CLK,
83 SUPPLY_SEQ_VOW_LDO,
84 SUPPLY_SEQ_TOP_CK,
85 SUPPLY_SEQ_TOP_CK_LAST,
86 SUPPLY_SEQ_DCC_CLK,
87 SUPPLY_SEQ_MIC_BIAS,
88 SUPPLY_SEQ_DMIC,
89 SUPPLY_SEQ_VOW_DIG_CFG,
90 SUPPLY_SEQ_VOW_PERIODIC_CFG,
91 SUPPLY_SEQ_AUD_TOP,
92 SUPPLY_SEQ_AUD_TOP_LAST,
93 SUPPLY_SEQ_DL_SDM_FIFO_CLK,
94 SUPPLY_SEQ_DL_SDM,
95 SUPPLY_SEQ_DL_NCP,
96 SUPPLY_SEQ_AFE,
97 /* playback */
98 SUPPLY_SEQ_DL_SRC,
99 SUPPLY_SEQ_DL_ESD_RESIST,
100 SUPPLY_SEQ_HP_DAMPING_OFF_RESET_CMFB,
101 SUPPLY_SEQ_HP_MUTE,
102 SUPPLY_SEQ_DL_LDO_REMOTE_SENSE,
103 SUPPLY_SEQ_DL_LDO,
104 SUPPLY_SEQ_DL_NV,
105 SUPPLY_SEQ_HP_ANA_TRIM,
106 SUPPLY_SEQ_DL_IBIST,
107 /* capture */
108 SUPPLY_SEQ_UL_PGA,
109 SUPPLY_SEQ_UL_ADC,
110 SUPPLY_SEQ_UL_MTKAIF,
111 SUPPLY_SEQ_UL_SRC_DMIC,
112 SUPPLY_SEQ_UL_SRC,
113};
114
115enum {
116 CH_L = 0,
117 CH_R,
118 NUM_CH,
119};
120
121/* dl bias */
122#define DRBIAS_MASK 0x7
123#define DRBIAS_HP_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 0)
124#define DRBIAS_HP_MASK_SFT (DRBIAS_MASK << DRBIAS_HP_SFT)
125#define DRBIAS_HS_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 3)
126#define DRBIAS_HS_MASK_SFT (DRBIAS_MASK << DRBIAS_HS_SFT)
127#define DRBIAS_LO_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 6)
128#define DRBIAS_LO_MASK_SFT (DRBIAS_MASK << DRBIAS_LO_SFT)
129
130enum {
131 DRBIAS_4UA = 0,
132 DRBIAS_5UA,
133 DRBIAS_6UA,
134 DRBIAS_7UA,
135 DRBIAS_8UA,
136 DRBIAS_9UA,
137 DRBIAS_10UA,
138 DRBIAS_11UA,
139};
140
141#define IBIAS_MASK 0x3
142#define IBIAS_HP_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 0)
143#define IBIAS_HP_MASK_SFT (IBIAS_MASK << IBIAS_HP_SFT)
144#define IBIAS_HS_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 2)
145#define IBIAS_HS_MASK_SFT (IBIAS_MASK << IBIAS_HS_SFT)
146#define IBIAS_LO_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 4)
147#define IBIAS_LO_MASK_SFT (IBIAS_MASK << IBIAS_LO_SFT)
148#define IBIAS_ZCD_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 6)
149#define IBIAS_ZCD_MASK_SFT (IBIAS_MASK << IBIAS_ZCD_SFT)
150
151enum {
152 IBIAS_4UA = 0,
153 IBIAS_5UA,
154 IBIAS_6UA,
155 IBIAS_7UA,
156};
157
158enum {
159 IBIAS_ZCD_3UA = 0,
160 IBIAS_ZCD_4UA,
161 IBIAS_ZCD_5UA,
162 IBIAS_ZCD_6UA,
163};
164
165enum {
166 MIC_BIAS_1P7 = 0,
167 MIC_BIAS_1P8,
168 MIC_BIAS_1P9,
169 MIC_BIAS_2P0,
170 MIC_BIAS_2P1,
171 MIC_BIAS_2P5,
172 MIC_BIAS_2P6,
173 MIC_BIAS_2P7,
174};
175
176struct mt6359_vow_periodic_on_off_data {
177 unsigned long long pga_on;
178 unsigned long long precg_on;
179 unsigned long long adc_on;
180 unsigned long long micbias0_on;
181 unsigned long long micbias1_on;
182 unsigned long long dcxo_on;
183 unsigned long long audglb_on;
184 unsigned long long vow_on;
185 unsigned long long pga_off;
186 unsigned long long precg_off;
187 unsigned long long adc_off;
188 unsigned long long micbias0_off;
189 unsigned long long micbias1_off;
190 unsigned long long dcxo_off;
191 unsigned long long audglb_off;
192 unsigned long long vow_off;
193};
194
195struct mt6359_priv {
196 struct device *dev;
197 struct regmap *regmap;
198
199 unsigned int dl_rate[MT6359_AIF_NUM];
200 unsigned int ul_rate[MT6359_AIF_NUM];
201
202 int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
203 unsigned int mux_select[MUX_NUM];
204
205 int dev_counter[DEVICE_NUM];
206
207 int hp_gain_ctl;
208 int hp_hifi_mode;
209
210 int hp_plugged;
211
212 int mtkaif_protocol;
213
214 struct regulator *avdd_reg;
215 struct dentry *debugfs;
216
217 /* vow control */
218 int vow_enable;
219 int reg_afe_vow_vad_cfg0;
220 int reg_afe_vow_vad_cfg1;
221 int reg_afe_vow_vad_cfg2;
222 int reg_afe_vow_vad_cfg3;
223 int reg_afe_vow_vad_cfg4;
224 int reg_afe_vow_vad_cfg5;
225 int reg_afe_vow_periodic;
226 unsigned int vow_channel;
227 struct mt6359_vow_periodic_on_off_data vow_periodic_param;
228};
229
230/* static function declaration */
231int mt6359_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
232 int mtkaif_protocol)
233{
234 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
235
236 priv->mtkaif_protocol = mtkaif_protocol;
237 return 0;
238}
239EXPORT_SYMBOL_GPL(mt6359_set_mtkaif_protocol);
240
241static void playback_gpio_set(struct mt6359_priv *priv)
242{
243 /* set gpio mosi mode, clk / data mosi */
244 regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ffe);
245 regmap_write(priv->regmap, MT6359_GPIO_MODE2_SET, 0x0249);
246 regmap_write(priv->regmap, MT6359_GPIO_MODE2, 0x0249);
247
248 /* sync mosi */
249 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x6);
250 regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x1);
251 regmap_update_bits(priv->regmap, MT6359_GPIO_MODE3,
252 0x7, 0x1);
253}
254
255static void playback_gpio_reset(struct mt6359_priv *priv)
256{
257 /* set pad_aud_*_mosi to GPIO mode and dir input
258 * reason:
259 * pad_aud_dat_mosi*, because the pin is used as boot strap
260 * don't clean clk/sync, for mtkaif protocol 2
261 */
262 regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ff8);
263 regmap_update_bits(priv->regmap, MT6359_GPIO_MODE2,
264 0x0ff8, 0x0000);
265 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0,
266 0x7 << 9, 0x0);
267}
268
269static void capture_gpio_set(struct mt6359_priv *priv)
270{
271 /* set gpio miso mode */
272 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00);
273 regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x0200);
274 regmap_update_bits(priv->regmap, MT6359_GPIO_MODE3,
275 0x0e00, 0x0200);
276
277 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f);
278 regmap_write(priv->regmap, MT6359_GPIO_MODE4_SET, 0x0009);
279 regmap_update_bits(priv->regmap, MT6359_GPIO_MODE4,
280 0x03f, 0x0009);
281}
282
283static void capture_gpio_reset(struct mt6359_priv *priv)
284{
285 /* set pad_aud_*_miso to GPIO mode and dir input
286 * reason:
287 * pad_aud_clk_miso, because when playback only the miso_clk
288 * will also have 26m, so will have power leak
289 * pad_aud_dat_miso*, because the pin is used as boot strap
290 */
291 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00);
292 regmap_update_bits(priv->regmap, MT6359_GPIO_MODE3,
293 0x0e00, 0x0000);
294
295 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f);
296 regmap_update_bits(priv->regmap, MT6359_GPIO_MODE4,
297 0x003f, 0x0000);
298
299 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0,
300 0x7 << 13, 0x0);
301 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR1,
302 0x3 << 0, 0x0);
303}
304
305static void vow_gpio_set(struct mt6359_priv *priv)
306{
307 /* vow gpio set (data) */
308 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00);
309 regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x0800);
310 regmap_update_bits(priv->regmap, MT6359_GPIO_MODE3,
311 0x0e00, 0x0800);
312 /* vow gpio set (clock) */
313 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x0007);
314 regmap_write(priv->regmap, MT6359_GPIO_MODE4_SET, 0x0004);
315 regmap_update_bits(priv->regmap, MT6359_GPIO_MODE4,
316 0x0007, 0x0004);
317}
318
319static void vow_gpio_reset(struct mt6359_priv *priv)
320{
321 /* set pad_aud_*_miso to GPIO mode and dir input
322 * reason:
323 * pad_aud_clk_miso, because when playback only the miso_clk
324 * will also have 26m, so will have power leak
325 * pad_aud_dat_miso*, because the pin is used as boot strap
326 */
327 /* vow gpio clear (data) */
328 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00);
329 regmap_update_bits(priv->regmap, MT6359_GPIO_MODE3,
330 0x0e00, 0x0000);
331 /* vow gpio clear (clock) */
332 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x0007);
333 regmap_update_bits(priv->regmap, MT6359_GPIO_MODE4,
334 0x0007, 0x0000);
335 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0,
336 0x1 << 15, 0x0);
337 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR1,
338 0x1 << 0, 0x0);
339}
340
341/* use only when not govern by DAPM */
342static int mt6359_set_dcxo(struct mt6359_priv *priv, bool enable)
343{
344 regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
345 0x1 << RG_XO_AUDIO_EN_M_SFT,
346 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
347 return 0;
348}
349
350/* use only when not govern by DAPM */
351static int mt6359_set_clksq(struct mt6359_priv *priv, bool enable)
352{
353 /* audio clk source from internal dcxo */
354 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
355 RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
356 0x0);
357
358 /* Enable/disable CLKSQ 26MHz */
359 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
360 RG_CLKSQ_EN_MASK_SFT,
361 (enable ? 1 : 0) << RG_CLKSQ_EN_SFT);
362 return 0;
363}
364
365/* use only when not govern by DAPM */
366static int mt6359_set_aud_global_bias(struct mt6359_priv *priv, bool enable)
367{
368 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
369 RG_AUDGLB_PWRDN_VA32_MASK_SFT,
370 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA32_SFT);
371 return 0;
372}
373
374/* use only when not govern by DAPM */
375static int mt6359_set_topck(struct mt6359_priv *priv, bool enable)
376{
377 regmap_update_bits(priv->regmap, MT6359_AUD_TOP_CKPDN_CON0,
378 0x0066, enable ? 0x0 : 0x66);
379 return 0;
380}
381
382static int mt6359_set_decoder_clk(struct mt6359_priv *priv, bool enable)
383{
384 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
385 RG_RSTB_DECODER_VA32_MASK_SFT,
386 (enable ? 1 : 0) << RG_RSTB_DECODER_VA32_SFT);
387 return 0;
388}
389
390static int mt6359_mtkaif_tx_enable(struct mt6359_priv *priv)
391{
392 switch (priv->mtkaif_protocol) {
393 case MT6359_MTKAIF_PROTOCOL_2_CLK_P2:
394 /* MTKAIF TX format setting */
395 regmap_update_bits(priv->regmap,
396 MT6359_AFE_ADDA_MTKAIF_CFG0,
397 0xffff, 0x0210);
398 /* enable aud_pad TX fifos */
399 regmap_update_bits(priv->regmap,
400 MT6359_AFE_AUD_PAD_TOP,
401 0xff00, 0x3800);
402 regmap_update_bits(priv->regmap,
403 MT6359_AFE_AUD_PAD_TOP,
404 0xff00, 0x3900);
405 break;
406 case MT6359_MTKAIF_PROTOCOL_2:
407 /* MTKAIF TX format setting */
408 regmap_update_bits(priv->regmap,
409 MT6359_AFE_ADDA_MTKAIF_CFG0,
410 0xffff, 0x0210);
411 /* enable aud_pad TX fifos */
412 regmap_update_bits(priv->regmap,
413 MT6359_AFE_AUD_PAD_TOP,
414 0xff00, 0x3100);
415 break;
416 case MT6359_MTKAIF_PROTOCOL_1:
417 default:
418 /* MTKAIF TX format setting */
419 regmap_update_bits(priv->regmap,
420 MT6359_AFE_ADDA_MTKAIF_CFG0,
421 0xffff, 0x0000);
422 /* enable aud_pad TX fifos */
423 regmap_update_bits(priv->regmap,
424 MT6359_AFE_AUD_PAD_TOP,
425 0xff00, 0x3100);
426 break;
427 }
428 return 0;
429}
430
431static int mt6359_mtkaif_tx_disable(struct mt6359_priv *priv)
432{
433 /* disable aud_pad TX fifos */
434 regmap_update_bits(priv->regmap, MT6359_AFE_AUD_PAD_TOP,
435 0xff00, 0x3000);
436 return 0;
437}
438
439int mt6359_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
440{
441 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
442
443 playback_gpio_set(priv);
444 capture_gpio_set(priv);
445 mt6359_mtkaif_tx_enable(priv);
446
447 mt6359_set_dcxo(priv, true);
448 mt6359_set_aud_global_bias(priv, true);
449 mt6359_set_clksq(priv, true);
450 mt6359_set_topck(priv, true);
451
452 /* set dat_miso_loopback on */
453 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
454 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
455 1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
456 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
457 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
458 1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
459 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
460 RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT,
461 1 << RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT);
462 return 0;
463}
464EXPORT_SYMBOL_GPL(mt6359_mtkaif_calibration_enable);
465
466int mt6359_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
467{
468 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
469
470 /* set dat_miso_loopback off */
471 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
472 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
473 0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
474 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
475 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
476 0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
477 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
478 RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT,
479 0 << RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT);
480
481 mt6359_set_topck(priv, false);
482 mt6359_set_clksq(priv, false);
483 mt6359_set_aud_global_bias(priv, false);
484 mt6359_set_dcxo(priv, false);
485
486 mt6359_mtkaif_tx_disable(priv);
487 playback_gpio_reset(priv);
488 capture_gpio_reset(priv);
489 return 0;
490}
491EXPORT_SYMBOL_GPL(mt6359_mtkaif_calibration_disable);
492
493int mt6359_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
494 int phase_1, int phase_2, int phase_3)
495{
496 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
497
498 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
499 RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT,
500 phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT);
501 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
502 RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT,
503 phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT);
504 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
505 RG_AUD_PAD_TOP_PHASE_MODE3_MASK_SFT,
506 phase_3 << RG_AUD_PAD_TOP_PHASE_MODE3_SFT);
507 return 0;
508}
509EXPORT_SYMBOL_GPL(mt6359_set_mtkaif_calibration_phase);
510
511/* dl pga gain */
512enum {
513 DL_GAIN_8DB = 0,
514 DL_GAIN_0DB = 8,
515 DL_GAIN_N_1DB = 9,
516 DL_GAIN_N_10DB = 18,
517 DL_GAIN_N_22DB = 30,
518 DL_GAIN_N_40DB = 0x1f,
519};
520#define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
521#define DL_GAIN_N_22DB_REG (DL_GAIN_N_22DB << 7 | DL_GAIN_N_22DB)
522#define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
523#define DL_GAIN_REG_MASK 0x0f9f
524
525/* reg idx for -40dB*/
526#define PGA_MINUS_40_DB_REG_VAL 0x1f
527#define HP_PGA_MINUS_40_DB_REG_VAL 0x3f
528static const char *const dl_pga_gain[] = {
529 "8Db", "7Db", "6Db", "5Db", "4Db",
530 "3Db", "2Db", "1Db", "0Db", "-1Db",
531 "-2Db", "-3Db", "-4Db", "-5Db", "-6Db",
532 "-7Db", "-8Db", "-9Db", "-10Db", "-40Db"
533};
534
535static const char *const hp_dl_pga_gain[] = {
536 "8Db", "7Db", "6Db", "5Db", "4Db",
537 "3Db", "2Db", "1Db", "0Db", "-1Db",
538 "-2Db", "-3Db", "-4Db", "-5Db", "-6Db",
539 "-7Db", "-8Db", "-9Db", "-10Db", "-11Db",
540 "-12Db", "-13Db", "-14Db", "-15Db", "-16Db",
541 "-17Db", "-18Db", "-19Db", "-20Db", "-21Db",
542 "-22Db", "-40Db"
543};
544
545static void zcd_disable(struct mt6359_priv *priv)
546{
547 regmap_write(priv->regmap, MT6359_ZCD_CON0, 0x0000);
548}
549
550static void hp_main_output_ramp(struct mt6359_priv *priv, bool up)
551{
552 int i = 0, stage = 0;
553 int target = 7;
554
555 /* Enable/Reduce HPL/R main output stage step by step */
556 for (i = 0; i <= target; i++) {
557 stage = up ? i : target - i;
558 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
559 RG_HPLOUTSTGCTRL_VAUDP32_MASK_SFT,
560 stage << RG_HPLOUTSTGCTRL_VAUDP32_SFT);
561 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
562 RG_HPROUTSTGCTRL_VAUDP32_MASK_SFT,
563 stage << RG_HPROUTSTGCTRL_VAUDP32_SFT);
564 usleep_range(600, 650);
565 }
566}
567
568static void hp_aux_feedback_loop_gain_ramp(struct mt6359_priv *priv, bool up)
569{
570 int i = 0, stage = 0;
571
572 /* Reduce HP aux feedback loop gain step by step */
573 for (i = 0; i <= 0xf; i++) {
574 stage = up ? i : 0xf - i;
575 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON9,
576 0xf << 12, stage << 12);
577 usleep_range(600, 650);
578 }
579}
580
581static void hp_in_pair_current(struct mt6359_priv *priv, bool increase)
582{
583 int i = 0, stage = 0;
584 int target = 0x3;
585
586 /* Set input diff pair bias select (Hi-Fi mode) */
587 if (priv->hp_hifi_mode) {
588 /* Reduce HP aux feedback loop gain step by step */
589 for (i = 0; i <= target; i++) {
590 stage = increase ? i : target - i;
591 regmap_update_bits(priv->regmap,
592 MT6359_AUDDEC_ANA_CON10,
593 0x3 << 3, stage << 3);
594 usleep_range(100, 150);
595 }
596 }
597}
598
599static void hp_pull_down(struct mt6359_priv *priv, bool enable)
600{
601 int i;
602
603 if (enable) {
604 for (i = 0x0; i <= 0x7; i++) {
605 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
606 RG_HPPSHORT2VCM_VAUDP32_MASK_SFT,
607 i << RG_HPPSHORT2VCM_VAUDP32_SFT);
608 usleep_range(100, 150);
609 }
610 } else {
611 for (i = 0x7; i >= 0x0; i--) {
612 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
613 RG_HPPSHORT2VCM_VAUDP32_MASK_SFT,
614 i << RG_HPPSHORT2VCM_VAUDP32_SFT);
615 usleep_range(100, 150);
616 }
617 }
618}
619
620static int hp_gain_ctl_select(struct mt6359_priv *priv,
621 unsigned int hp_gain_ctl)
622{
623 if (hp_gain_ctl >= HP_GAIN_CTL_NUM) {
624 dev_warn(priv->dev, "%s(), hp_gain_ctl %d invalid\n",
625 __func__, hp_gain_ctl);
626 return -EINVAL;
627 }
628
629 priv->hp_gain_ctl = hp_gain_ctl;
630 regmap_update_bits(priv->regmap, MT6359_AFE_DL_NLE_CFG,
631 NLE_LCH_HPGAIN_SEL_MASK_SFT,
632 hp_gain_ctl << NLE_LCH_HPGAIN_SEL_SFT);
633 regmap_update_bits(priv->regmap, MT6359_AFE_DL_NLE_CFG,
634 NLE_RCH_HPGAIN_SEL_MASK_SFT,
635 hp_gain_ctl << NLE_RCH_HPGAIN_SEL_SFT);
636
637 return 0;
638}
639
640static bool is_valid_hp_pga_idx(int reg_idx)
641{
642 return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_22DB) ||
643 reg_idx == DL_GAIN_N_40DB;
644}
645
646static void headset_volume_ramp(struct mt6359_priv *priv,
647 int from, int to)
648{
649 int offset = 0, count = 1, reg_idx;
650
651 if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to))
652 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n",
653 __func__, from, to);
654
655 dev_info(priv->dev, "%s(), from %d, to %d\n",
656 __func__, from, to);
657
658 if (to > from)
659 offset = to - from;
660 else
661 offset = from - to;
662
663 while (offset > 0) {
664 if (to > from)
665 reg_idx = from + count;
666 else
667 reg_idx = from - count;
668
669 if (is_valid_hp_pga_idx(reg_idx)) {
670 regmap_update_bits(priv->regmap,
671 MT6359_ZCD_CON2,
672 DL_GAIN_REG_MASK,
673 (reg_idx << 7) | reg_idx);
674 usleep_range(600, 650);
675 }
676 offset--;
677 count++;
678 }
679}
680
681#define MT_SOC_ENUM_EXT_ID(xname, xenum, xhandler_get, xhandler_put, id) \
682{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .device = id,\
683 .info = snd_soc_info_enum_double, \
684 .get = xhandler_get, .put = xhandler_put, \
685 .private_value = (unsigned long)&xenum }
686
687/* Mic Type MUX */
688enum {
689 MIC_TYPE_MUX_IDLE = 0,
690 MIC_TYPE_MUX_ACC,
691 MIC_TYPE_MUX_DMIC,
692 MIC_TYPE_MUX_DCC,
693 MIC_TYPE_MUX_DCC_ECM_DIFF,
694 MIC_TYPE_MUX_DCC_ECM_SINGLE,
695 MIC_TYPE_MUX_VOW_ACC,
696 MIC_TYPE_MUX_VOW_DMIC,
697 MIC_TYPE_MUX_VOW_DMIC_LP,
698 MIC_TYPE_MUX_VOW_DCC,
699 MIC_TYPE_MUX_VOW_DCC_ECM_DIFF,
700 MIC_TYPE_MUX_VOW_DCC_ECM_SINGLE,
701};
702
703#define IS_VOW_DCC_BASE(x) (x == MIC_TYPE_MUX_VOW_DCC || \
704 x == MIC_TYPE_MUX_VOW_DCC_ECM_DIFF || \
705 x == MIC_TYPE_MUX_VOW_DCC_ECM_SINGLE)
706
707#define IS_DCC_BASE(x) (x == MIC_TYPE_MUX_DCC || \
708 x == MIC_TYPE_MUX_DCC_ECM_DIFF || \
709 x == MIC_TYPE_MUX_DCC_ECM_SINGLE || \
710 IS_VOW_DCC_BASE(x))
711
712#define IS_VOW_AMIC_BASE(x) (x == MIC_TYPE_MUX_VOW_ACC || IS_VOW_DCC_BASE(x))
713
714#define IS_VOW_BASE(x) (x == MIC_TYPE_MUX_VOW_DMIC || \
715 x == MIC_TYPE_MUX_VOW_DMIC_LP || \
716 IS_VOW_AMIC_BASE(x))
717
718static const char *const mic_type_mux_map[] = {
719 "Idle",
720 "ACC",
721 "DMIC",
722 "DCC",
723 "DCC_ECM_DIFF",
724 "DCC_ECM_SINGLE",
725 "VOW_ACC",
726 "VOW_DMIC",
727 "VOW_DMIC_LP",
728 "VOW_DCC",
729 "VOW_DCC_ECM_DIFF",
730 "VOW_DCC_ECM_SINGLE"
731};
732
733static const struct soc_enum mic_type_mux_enum[] = {
734 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mic_type_mux_map), mic_type_mux_map),
735};
736
737static int mic_type_get(struct snd_kcontrol *kcontrol,
738 struct snd_ctl_elem_value *ucontrol)
739{
740 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
741 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
742
743 ucontrol->value.integer.value[0] =
744 priv->mux_select[kcontrol->id.device];
745 return 0;
746}
747
748static int mic_type_set(struct snd_kcontrol *kcontrol,
749 struct snd_ctl_elem_value *ucontrol)
750{
751 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
752 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
753 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
754 int index = ucontrol->value.integer.value[0];
755 unsigned int id = kcontrol->id.device;
756
757 if (ucontrol->value.enumerated.item[0] >= e->items)
758 return -EINVAL;
759
760 priv->mux_select[id] = index;
761 return 0;
762}
763
764static int mt6359_put_volsw(struct snd_kcontrol *kcontrol,
765 struct snd_ctl_elem_value *ucontrol)
766{
767 struct snd_soc_component *component =
768 snd_soc_kcontrol_component(kcontrol);
769 struct mt6359_priv *priv = snd_soc_component_get_drvdata(component);
770 struct soc_mixer_control *mc =
771 (struct soc_mixer_control *)kcontrol->private_value;
772 unsigned int reg;
773 int index = ucontrol->value.integer.value[0];
774 int ret;
775
776 ret = snd_soc_put_volsw(kcontrol, ucontrol);
777 if (ret < 0)
778 return ret;
779
780 switch (mc->reg) {
781 case MT6359_ZCD_CON2:
782 regmap_read(priv->regmap, MT6359_ZCD_CON2, &reg);
783 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] =
784 (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK;
785 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] =
786 (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK;
787 break;
788 case MT6359_ZCD_CON1:
789 regmap_read(priv->regmap, MT6359_ZCD_CON1, &reg);
790 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] =
791 (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK;
792 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] =
793 (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK;
794 break;
795 case MT6359_ZCD_CON3:
796 regmap_read(priv->regmap, MT6359_ZCD_CON3, &reg);
797 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] =
798 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
799 break;
800 case MT6359_AUDENC_ANA_CON0:
801 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON0, &reg);
802 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] =
803 (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK;
804 break;
805 case MT6359_AUDENC_ANA_CON1:
806 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON1, &reg);
807 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] =
808 (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK;
809 break;
810 case MT6359_AUDENC_ANA_CON2:
811 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON2, &reg);
812 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3] =
813 (reg >> RG_AUDPREAMP3GAIN_SFT) & RG_AUDPREAMP3GAIN_MASK;
814
815 break;
816 }
817
818 dev_info(priv->dev, "%s(), name %s, reg(0x%x) = 0x%x, set index = %x\n",
819 __func__, kcontrol->id.name, mc->reg, reg, index);
820
821 return ret;
822}
823
824static const DECLARE_TLV_DB_SCALE(hp_playback_tlv, -2200, 100, 0);
825static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
826static const DECLARE_TLV_DB_SCALE(capture_tlv, 0, 600, 0);
827
828static const struct snd_kcontrol_new mt6359_snd_controls[] = {
829 /* dl pga gain */
830 SOC_SINGLE_EXT_TLV("HeadsetL Volume",
831 MT6359_ZCD_CON2, 0, 0x1E, 0,
832 snd_soc_get_volsw, mt6359_put_volsw,
833 hp_playback_tlv),
834 SOC_SINGLE_EXT_TLV("HeadsetR Volume",
835 MT6359_ZCD_CON2, 7, 0x1E, 0,
836 snd_soc_get_volsw, mt6359_put_volsw,
837 hp_playback_tlv),
838 SOC_SINGLE_EXT_TLV("LineoutL Volume",
839 MT6359_ZCD_CON1, 0, 0x12, 0,
840 snd_soc_get_volsw, mt6359_put_volsw, playback_tlv),
841 SOC_SINGLE_EXT_TLV("LineoutR Volume",
842 MT6359_ZCD_CON1, 7, 0x12, 0,
843 snd_soc_get_volsw, mt6359_put_volsw, playback_tlv),
844 SOC_SINGLE_EXT_TLV("Handset Volume",
845 MT6359_ZCD_CON3, 0, 0x12, 0,
846 snd_soc_get_volsw, mt6359_put_volsw, playback_tlv),
847
848 /* ul pga gain */
849 SOC_SINGLE_EXT_TLV("PGAL Volume",
850 MT6359_AUDENC_ANA_CON0, RG_AUDPREAMPLGAIN_SFT, 4, 0,
851 snd_soc_get_volsw, mt6359_put_volsw, capture_tlv),
852 SOC_SINGLE_EXT_TLV("PGAR Volume",
853 MT6359_AUDENC_ANA_CON1, RG_AUDPREAMPRGAIN_SFT, 4, 0,
854 snd_soc_get_volsw, mt6359_put_volsw, capture_tlv),
855 SOC_SINGLE_EXT_TLV("PGA3 Volume",
856 MT6359_AUDENC_ANA_CON2, RG_AUDPREAMP3GAIN_SFT, 4, 0,
857 snd_soc_get_volsw, mt6359_put_volsw, capture_tlv),
858
859 /* mix type mux */
860 MT_SOC_ENUM_EXT_ID("Mic_Type_Mux_0", mic_type_mux_enum[0],
861 mic_type_get, mic_type_set,
862 MUX_MIC_TYPE_0),
863 MT_SOC_ENUM_EXT_ID("Mic_Type_Mux_1", mic_type_mux_enum[0],
864 mic_type_get, mic_type_set,
865 MUX_MIC_TYPE_1),
866 MT_SOC_ENUM_EXT_ID("Mic_Type_Mux_2", mic_type_mux_enum[0],
867 mic_type_get, mic_type_set,
868 MUX_MIC_TYPE_2),
869};
870
871/* MUX */
872
873/* LOL MUX */
874enum {
875 LO_MUX_OPEN = 0,
876 LO_MUX_L_DAC,
877 LO_MUX_3RD_DAC,
878 LO_MUX_TEST_MODE,
879 LO_MUX_MASK = 0x3,
880};
881
882static const char * const lo_in_mux_map[] = {
883 "Open", "Playback_L_DAC", "Playback", "Test Mode"
884};
885
886static int lo_in_mux_map_value[] = {
887 0x0, 0x1, 0x2, 0x3,
888};
889
890static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
891 SND_SOC_NOPM,
892 0,
893 LO_MUX_MASK,
894 lo_in_mux_map,
895 lo_in_mux_map_value);
896
897static const struct snd_kcontrol_new lo_in_mux_control =
898 SOC_DAPM_ENUM("LO Select", lo_in_mux_map_enum);
899
900/*HP MUX */
901enum {
902 HP_MUX_OPEN = 0,
903 HP_MUX_HPSPK,
904 HP_MUX_HP,
905 HP_MUX_TEST_MODE,
906 HP_MUX_HP_IMPEDANCE,
907 HP_MUX_MASK = 0x7,
908};
909
910static const char * const hp_in_mux_map[] = {
911 "Open",
912 "LoudSPK Playback",
913 "Audio Playback",
914 "Test Mode",
915 "HP Impedance",
916 "undefined1",
917 "undefined2",
918 "undefined3",
919};
920
921static int hp_in_mux_map_value[] = {
922 HP_MUX_OPEN,
923 HP_MUX_HPSPK,
924 HP_MUX_HP,
925 HP_MUX_TEST_MODE,
926 HP_MUX_HP_IMPEDANCE,
927 HP_MUX_OPEN,
928 HP_MUX_OPEN,
929 HP_MUX_OPEN,
930};
931
932static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
933 SND_SOC_NOPM,
934 0,
935 HP_MUX_MASK,
936 hp_in_mux_map,
937 hp_in_mux_map_value);
938
939static const struct snd_kcontrol_new hpl_in_mux_control =
940 SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
941
942static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
943 SND_SOC_NOPM,
944 0,
945 HP_MUX_MASK,
946 hp_in_mux_map,
947 hp_in_mux_map_value);
948
949static const struct snd_kcontrol_new hpr_in_mux_control =
950 SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
951
952/* RCV MUX */
953enum {
954 RCV_MUX_OPEN = 0,
955 RCV_MUX_MUTE,
956 RCV_MUX_VOICE_PLAYBACK,
957 RCV_MUX_TEST_MODE,
958 RCV_MUX_MASK = 0x3,
959};
960
961static const char * const rcv_in_mux_map[] = {
962 "Open", "Mute", "Voice Playback", "Test Mode"
963};
964
965static int rcv_in_mux_map_value[] = {
966 RCV_MUX_OPEN,
967 RCV_MUX_MUTE,
968 RCV_MUX_VOICE_PLAYBACK,
969 RCV_MUX_TEST_MODE,
970};
971
972static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
973 SND_SOC_NOPM,
974 0,
975 RCV_MUX_MASK,
976 rcv_in_mux_map,
977 rcv_in_mux_map_value);
978
979static const struct snd_kcontrol_new rcv_in_mux_control =
980 SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
981
982/* DAC In MUX */
983static const char * const dac_in_mux_map[] = {
984 "Normal Path", "Sgen"
985};
986
987static int dac_in_mux_map_value[] = {
988 0x0, 0x1,
989};
990
991static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
992 MT6359_AFE_TOP_CON0,
993 DL_SINE_ON_SFT,
994 DL_SINE_ON_MASK,
995 dac_in_mux_map,
996 dac_in_mux_map_value);
997
998static const struct snd_kcontrol_new dac_in_mux_control =
999 SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
1000
1001/* AIF Out MUX */
1002static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
1003 MT6359_AFE_TOP_CON0,
1004 UL_SINE_ON_SFT,
1005 UL_SINE_ON_MASK,
1006 dac_in_mux_map,
1007 dac_in_mux_map_value);
1008
1009static const struct snd_kcontrol_new aif_out_mux_control =
1010 SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
1011
1012static SOC_VALUE_ENUM_SINGLE_DECL(aif2_out_mux_map_enum,
1013 MT6359_AFE_TOP_CON0,
1014 ADDA6_UL_SINE_ON_SFT,
1015 ADDA6_UL_SINE_ON_MASK,
1016 dac_in_mux_map,
1017 dac_in_mux_map_value);
1018
1019static const struct snd_kcontrol_new aif2_out_mux_control =
1020 SOC_DAPM_ENUM("AIF Out Select", aif2_out_mux_map_enum);
1021
1022/* UL SRC MUX */
1023enum {
1024 UL_SRC_MUX_AMIC = 0,
1025 UL_SRC_MUX_DMIC,
1026};
1027
1028static const char * const ul_src_mux_map[] = {
1029 "AMIC",
1030 "DMIC",
1031};
1032
1033static int ul_src_mux_map_value[] = {
1034 UL_SRC_MUX_AMIC,
1035 UL_SRC_MUX_DMIC,
1036};
1037
1038static SOC_VALUE_ENUM_SINGLE_DECL(ul_src_mux_map_enum,
1039 MT6359_AFE_UL_SRC_CON0_L,
1040 UL_SDM_3_LEVEL_CTL_SFT,
1041 UL_SDM_3_LEVEL_CTL_MASK,
1042 ul_src_mux_map,
1043 ul_src_mux_map_value);
1044
1045static const struct snd_kcontrol_new ul_src_mux_control =
1046 SOC_DAPM_ENUM("UL_SRC_MUX Select", ul_src_mux_map_enum);
1047
1048static SOC_VALUE_ENUM_SINGLE_DECL(ul2_src_mux_map_enum,
1049 MT6359_AFE_ADDA6_UL_SRC_CON0_L,
1050 ADDA6_UL_SDM_3_LEVEL_CTL_SFT,
1051 ADDA6_UL_SDM_3_LEVEL_CTL_MASK,
1052 ul_src_mux_map,
1053 ul_src_mux_map_value);
1054
1055static const struct snd_kcontrol_new ul2_src_mux_control =
1056 SOC_DAPM_ENUM("UL_SRC_MUX Select", ul2_src_mux_map_enum);
1057
1058/* VOW UL SRC MUX */
1059static SOC_VALUE_ENUM_SINGLE_DECL(vow_ul_src_mux_map_enum,
1060 MT6359_AFE_VOW_TOP_CON0,
1061 VOW_SDM_3_LEVEL_SFT,
1062 VOW_SDM_3_LEVEL_MASK,
1063 ul_src_mux_map,
1064 ul_src_mux_map_value);
1065
1066static const struct snd_kcontrol_new vow_ul_src_mux_control =
1067 SOC_DAPM_ENUM("VOW_UL_SRC_MUX Select", vow_ul_src_mux_map_enum);
1068
1069/* MISO MUX */
1070enum {
1071 MISO_MUX_UL1_CH1 = 0,
1072 MISO_MUX_UL1_CH2,
1073 MISO_MUX_UL2_CH1,
1074 MISO_MUX_UL2_CH2,
1075};
1076
1077static const char * const miso_mux_map[] = {
1078 "UL1_CH1",
1079 "UL1_CH2",
1080 "UL2_CH1",
1081 "UL2_CH2",
1082};
1083
1084static int miso_mux_map_value[] = {
1085 MISO_MUX_UL1_CH1,
1086 MISO_MUX_UL1_CH2,
1087 MISO_MUX_UL2_CH1,
1088 MISO_MUX_UL2_CH2,
1089};
1090
1091static SOC_VALUE_ENUM_SINGLE_DECL(miso0_mux_map_enum,
1092 MT6359_AFE_MTKAIF_MUX_CFG,
1093 RG_ADDA_CH1_SEL_SFT,
1094 RG_ADDA_CH1_SEL_MASK,
1095 miso_mux_map,
1096 miso_mux_map_value);
1097
1098static const struct snd_kcontrol_new miso0_mux_control =
1099 SOC_DAPM_ENUM("MISO_MUX Select", miso0_mux_map_enum);
1100
1101static SOC_VALUE_ENUM_SINGLE_DECL(miso1_mux_map_enum,
1102 MT6359_AFE_MTKAIF_MUX_CFG,
1103 RG_ADDA_CH2_SEL_SFT,
1104 RG_ADDA_CH2_SEL_MASK,
1105 miso_mux_map,
1106 miso_mux_map_value);
1107
1108static const struct snd_kcontrol_new miso1_mux_control =
1109 SOC_DAPM_ENUM("MISO_MUX Select", miso1_mux_map_enum);
1110
1111static SOC_VALUE_ENUM_SINGLE_DECL(miso2_mux_map_enum,
1112 MT6359_AFE_MTKAIF_MUX_CFG,
1113 RG_ADDA6_CH1_SEL_SFT,
1114 RG_ADDA6_CH1_SEL_MASK,
1115 miso_mux_map,
1116 miso_mux_map_value);
1117
1118static const struct snd_kcontrol_new miso2_mux_control =
1119 SOC_DAPM_ENUM("MISO_MUX Select", miso2_mux_map_enum);
1120
1121/* VOW AMIC MUX */
1122enum {
1123 VOW_AMIC_MUX_ADC_L = 0,
1124 VOW_AMIC_MUX_ADC_R,
1125 VOW_AMIC_MUX_ADC_T,
1126};
1127
1128static const char * const vow_amic_mux_map[] = {
1129 "ADC_L",
1130 "ADC_R",
1131 "ADC_T",
1132};
1133
1134static int vow_amic_mux_map_value[] = {
1135 VOW_AMIC_MUX_ADC_L,
1136 VOW_AMIC_MUX_ADC_R,
1137 VOW_AMIC_MUX_ADC_T,
1138};
1139
1140/* VOW AMIC MUX */
1141static SOC_VALUE_ENUM_SINGLE_DECL(vow_amic0_mux_map_enum,
1142 MT6359_AFE_VOW_TOP_CON4,
1143 RG_VOW_AMIC_ADC1_SOURCE_SEL_SFT,
1144 RG_VOW_AMIC_ADC1_SOURCE_SEL_MASK,
1145 vow_amic_mux_map,
1146 vow_amic_mux_map_value);
1147
1148static const struct snd_kcontrol_new vow_amic0_mux_control =
1149 SOC_DAPM_ENUM("VOW_AMIC_MUX Select", vow_amic0_mux_map_enum);
1150
1151static SOC_VALUE_ENUM_SINGLE_DECL(vow_amic1_mux_map_enum,
1152 MT6359_AFE_VOW_TOP_CON4,
1153 RG_VOW_AMIC_ADC2_SOURCE_SEL_SFT,
1154 RG_VOW_AMIC_ADC2_SOURCE_SEL_MASK,
1155 vow_amic_mux_map,
1156 vow_amic_mux_map_value);
1157
1158static const struct snd_kcontrol_new vow_amic1_mux_control =
1159 SOC_DAPM_ENUM("VOW_AMIC_MUX Select", vow_amic1_mux_map_enum);
1160
1161/* DMIC MUX */
1162enum {
1163 DMIC_MUX_DMIC_DATA0 = 0,
1164 DMIC_MUX_DMIC_DATA1_L,
1165 DMIC_MUX_DMIC_DATA1_L_1,
1166 DMIC_MUX_DMIC_DATA1_R,
1167};
1168
1169static const char * const dmic_mux_map[] = {
1170 "DMIC_DATA0",
1171 "DMIC_DATA1_L",
1172 "DMIC_DATA1_L_1",
1173 "DMIC_DATA1_R",
1174};
1175
1176static int dmic_mux_map_value[] = {
1177 DMIC_MUX_DMIC_DATA0,
1178 DMIC_MUX_DMIC_DATA1_L,
1179 DMIC_MUX_DMIC_DATA1_L_1,
1180 DMIC_MUX_DMIC_DATA1_R,
1181};
1182
1183static SOC_VALUE_ENUM_SINGLE_DECL(dmic0_mux_map_enum,
1184 MT6359_AFE_MIC_ARRAY_CFG,
1185 RG_DMIC_ADC1_SOURCE_SEL_SFT,
1186 RG_DMIC_ADC1_SOURCE_SEL_MASK,
1187 dmic_mux_map,
1188 dmic_mux_map_value);
1189
1190static const struct snd_kcontrol_new dmic0_mux_control =
1191 SOC_DAPM_ENUM("DMIC_MUX Select", dmic0_mux_map_enum);
1192
1193/* ul1 ch2 use RG_DMIC_ADC3_SOURCE_SEL */
1194static SOC_VALUE_ENUM_SINGLE_DECL(dmic1_mux_map_enum,
1195 MT6359_AFE_MIC_ARRAY_CFG,
1196 RG_DMIC_ADC3_SOURCE_SEL_SFT,
1197 RG_DMIC_ADC3_SOURCE_SEL_MASK,
1198 dmic_mux_map,
1199 dmic_mux_map_value);
1200
1201static const struct snd_kcontrol_new dmic1_mux_control =
1202 SOC_DAPM_ENUM("DMIC_MUX Select", dmic1_mux_map_enum);
1203
1204/* ul2 ch1 use RG_DMIC_ADC2_SOURCE_SEL */
1205static SOC_VALUE_ENUM_SINGLE_DECL(dmic2_mux_map_enum,
1206 MT6359_AFE_MIC_ARRAY_CFG,
1207 RG_DMIC_ADC2_SOURCE_SEL_SFT,
1208 RG_DMIC_ADC2_SOURCE_SEL_MASK,
1209 dmic_mux_map,
1210 dmic_mux_map_value);
1211
1212static const struct snd_kcontrol_new dmic2_mux_control =
1213 SOC_DAPM_ENUM("DMIC_MUX Select", dmic2_mux_map_enum);
1214
1215/* ADC L MUX */
1216enum {
1217 ADC_MUX_IDLE = 0,
1218 ADC_MUX_AIN0,
1219 ADC_MUX_PREAMPLIFIER,
1220 ADC_MUX_IDLE1,
1221};
1222
1223static const char * const adc_left_mux_map[] = {
1224 "Idle", "AIN0", "Left Preamplifier", "Idle_1"
1225};
1226
1227static int adc_mux_map_value[] = {
1228 ADC_MUX_IDLE,
1229 ADC_MUX_AIN0,
1230 ADC_MUX_PREAMPLIFIER,
1231 ADC_MUX_IDLE1,
1232};
1233
1234static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
1235 MT6359_AUDENC_ANA_CON0,
1236 RG_AUDADCLINPUTSEL_SFT,
1237 RG_AUDADCLINPUTSEL_MASK,
1238 adc_left_mux_map,
1239 adc_mux_map_value);
1240
1241static const struct snd_kcontrol_new adc_left_mux_control =
1242 SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
1243
1244/* ADC R MUX */
1245static const char * const adc_right_mux_map[] = {
1246 "Idle", "AIN0", "Right Preamplifier", "Idle_1"
1247};
1248
1249static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
1250 MT6359_AUDENC_ANA_CON1,
1251 RG_AUDADCRINPUTSEL_SFT,
1252 RG_AUDADCRINPUTSEL_MASK,
1253 adc_right_mux_map,
1254 adc_mux_map_value);
1255
1256static const struct snd_kcontrol_new adc_right_mux_control =
1257 SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
1258
1259/* ADC 3 MUX */
1260static const char * const adc_3_mux_map[] = {
1261 "Idle", "AIN0", "Preamplifier", "Idle_1"
1262};
1263
1264static SOC_VALUE_ENUM_SINGLE_DECL(adc_3_mux_map_enum,
1265 MT6359_AUDENC_ANA_CON2,
1266 RG_AUDADC3INPUTSEL_SFT,
1267 RG_AUDADC3INPUTSEL_MASK,
1268 adc_3_mux_map,
1269 adc_mux_map_value);
1270
1271static const struct snd_kcontrol_new adc_3_mux_control =
1272 SOC_DAPM_ENUM("ADC 3 Select", adc_3_mux_map_enum);
1273
1274/* PGA L MUX */
1275enum {
1276 PGA_L_MUX_NONE = 0,
1277 PGA_L_MUX_AIN0,
1278 PGA_L_MUX_AIN1,
1279};
1280
1281static const char * const pga_l_mux_map[] = {
1282 "None", "AIN0", "AIN1"
1283};
1284
1285static int pga_l_mux_map_value[] = {
1286 PGA_L_MUX_NONE,
1287 PGA_L_MUX_AIN0,
1288 PGA_L_MUX_AIN1
1289};
1290
1291static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
1292 MT6359_AUDENC_ANA_CON0,
1293 RG_AUDPREAMPLINPUTSEL_SFT,
1294 RG_AUDPREAMPLINPUTSEL_MASK,
1295 pga_l_mux_map,
1296 pga_l_mux_map_value);
1297
1298static const struct snd_kcontrol_new pga_left_mux_control =
1299 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
1300
1301/* PGA R MUX */
1302enum {
1303 PGA_R_MUX_NONE = 0,
1304 PGA_R_MUX_AIN2,
1305 PGA_R_MUX_AIN3,
1306 PGA_R_MUX_AIN0,
1307};
1308
1309static const char * const pga_r_mux_map[] = {
1310 "None", "AIN2", "AIN3", "AIN0"
1311};
1312
1313static int pga_r_mux_map_value[] = {
1314 PGA_R_MUX_NONE,
1315 PGA_R_MUX_AIN2,
1316 PGA_R_MUX_AIN3,
1317 PGA_R_MUX_AIN0
1318};
1319
1320static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
1321 MT6359_AUDENC_ANA_CON1,
1322 RG_AUDPREAMPRINPUTSEL_SFT,
1323 RG_AUDPREAMPRINPUTSEL_MASK,
1324 pga_r_mux_map,
1325 pga_r_mux_map_value);
1326
1327static const struct snd_kcontrol_new pga_right_mux_control =
1328 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
1329
1330/* PGA 3 MUX */
1331enum {
1332 PGA_3_MUX_NONE = 0,
1333 PGA_3_MUX_AIN3,
1334 PGA_3_MUX_AIN2,
1335};
1336
1337static const char * const pga_3_mux_map[] = {
1338 "None", "AIN3", "AIN2"
1339};
1340
1341static int pga_3_mux_map_value[] = {
1342 PGA_3_MUX_NONE,
1343 PGA_3_MUX_AIN3,
1344 PGA_3_MUX_AIN2
1345};
1346
1347static SOC_VALUE_ENUM_SINGLE_DECL(pga_3_mux_map_enum,
1348 MT6359_AUDENC_ANA_CON2,
1349 RG_AUDPREAMP3INPUTSEL_SFT,
1350 RG_AUDPREAMP3INPUTSEL_MASK,
1351 pga_3_mux_map,
1352 pga_3_mux_map_value);
1353
1354static const struct snd_kcontrol_new pga_3_mux_control =
1355 SOC_DAPM_ENUM("PGA 3 Select", pga_3_mux_map_enum);
1356
1357static int mt_clksq_event(struct snd_soc_dapm_widget *w,
1358 struct snd_kcontrol *kcontrol,
1359 int event)
1360{
1361 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1362 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1363
1364 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1365
1366 switch (event) {
1367 case SND_SOC_DAPM_PRE_PMU:
1368 /* audio clk source from internal dcxo */
1369 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
1370 RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
1371 0x0);
1372 break;
1373 default:
1374 break;
1375 }
1376
1377 return 0;
1378}
1379
1380static int mt_sgen_event(struct snd_soc_dapm_widget *w,
1381 struct snd_kcontrol *kcontrol,
1382 int event)
1383{
1384 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1385 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1386
1387 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1388
1389 switch (event) {
1390 case SND_SOC_DAPM_PRE_PMU:
1391 /* sdm audio fifo clock power on */
1392 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0006);
1393 /* scrambler clock on enable */
1394 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xCBA1);
1395 /* sdm power on */
1396 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0003);
1397 /* sdm fifo enable */
1398 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x000B);
1399
1400 regmap_update_bits(priv->regmap, MT6359_AFE_SGEN_CFG0,
1401 0xff3f,
1402 0x0000);
1403 regmap_update_bits(priv->regmap, MT6359_AFE_SGEN_CFG1,
1404 0xffff,
1405 0x0001);
1406 break;
1407 case SND_SOC_DAPM_POST_PMD:
1408 /* DL scrambler disabling sequence */
1409 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0000);
1410 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0);
1411 break;
1412 default:
1413 break;
1414 }
1415
1416 return 0;
1417}
1418
1419static int mtk_hp_enable(struct mt6359_priv *priv)
1420{
1421 if (priv->hp_hifi_mode) {
1422 /* Set HP DR bias current optimization, 010: 6uA */
1423 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
1424 DRBIAS_HP_MASK_SFT,
1425 DRBIAS_6UA << DRBIAS_HP_SFT);
1426 /* Set HP & ZCD bias current optimization */
1427 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1428 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
1429 IBIAS_ZCD_MASK_SFT,
1430 IBIAS_ZCD_4UA << IBIAS_ZCD_SFT);
1431 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
1432 IBIAS_HP_MASK_SFT,
1433 IBIAS_5UA << IBIAS_HP_SFT);
1434 } else {
1435 /* Set HP DR bias current optimization, 001: 5uA */
1436 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
1437 DRBIAS_HP_MASK_SFT,
1438 DRBIAS_5UA << DRBIAS_HP_SFT);
1439 /* Set HP & ZCD bias current optimization */
1440 /* 00: ZCD: 3uA, HP/HS/LO: 4uA */
1441 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
1442 IBIAS_ZCD_MASK_SFT,
1443 IBIAS_ZCD_3UA << IBIAS_ZCD_SFT);
1444 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
1445 IBIAS_HP_MASK_SFT,
1446 IBIAS_4UA << IBIAS_HP_SFT);
1447 }
1448
1449 /* HP damp circuit enable */
1450 /*Enable HPRN/HPLN output 4K to VCM */
1451 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0087);
1452
1453 /* HP Feedback Cap select 2'b00: 15pF */
1454 /* for >= 96KHz sampling rate: 2'b01: 10.5pF */
1455 if (priv->dl_rate[MT6359_AIF_1] >= 96000)
1456 regmap_update_bits(priv->regmap,
1457 MT6359_AUDDEC_ANA_CON4,
1458 RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK_SFT,
1459 0x1 << RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_SFT);
1460 else
1461 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON4, 0x0000);
1462
1463
1464 /* Set HPP/N STB enhance circuits */
1465 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON2, 0xf133);
1466
1467 /* Enable HP aux output stage */
1468 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x000c);
1469 /* Enable HP aux feedback loop */
1470 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x003c);
1471 /* Enable HP aux CMFB loop */
1472 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c00);
1473 /* Enable HP driver bias circuits */
1474 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30c0);
1475 /* Enable HP driver core circuits */
1476 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30f0);
1477 /* Short HP main output to HP aux output stage */
1478 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00fc);
1479
1480 /* Increase HP input pair current to HPM step by step */
1481 hp_in_pair_current(priv, true);
1482
1483 /* Enable HP main CMFB loop */
1484 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e00);
1485 /* Disable HP aux CMFB loop */
1486 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0200);
1487
1488 /* Enable HP main output stage */
1489 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00ff);
1490 /* Enable HPR/L main output stage step by step */
1491 hp_main_output_ramp(priv, true);
1492
1493 /* Reduce HP aux feedback loop gain */
1494 hp_aux_feedback_loop_gain_ramp(priv, true);
1495 /* Disable HP aux feedback loop */
1496 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf);
1497
1498 /* apply volume setting */
1499 headset_volume_ramp(priv,
1500 DL_GAIN_N_22DB,
1501 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
1502
1503 /* Disable HP aux output stage */
1504 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3);
1505 /* Unshort HP main output to HP aux output stage */
1506 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x7703);
1507 usleep_range(100, 120);
1508
1509 /* Enable AUD_CLK */
1510 mt6359_set_decoder_clk(priv, true);
1511
1512 /* Enable Audio DAC */
1513 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30ff);
1514 if (priv->hp_hifi_mode) {
1515 /* Enable low-noise mode of DAC */
1516 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf201);
1517 } else {
1518 /* Disable low-noise mode of DAC */
1519 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf200);
1520 }
1521 usleep_range(100, 120);
1522
1523 /* Switch HPL MUX to audio DAC */
1524 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x32ff);
1525 /* Switch HPR MUX to audio DAC */
1526 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x3aff);
1527
1528 /* Disable Pull-down HPL/R to AVSS28_AUD */
1529 hp_pull_down(priv, false);
1530
1531 return 0;
1532}
1533
1534static int mtk_hp_disable(struct mt6359_priv *priv)
1535{
1536 /* Pull-down HPL/R to AVSS28_AUD */
1537 hp_pull_down(priv, true);
1538
1539 /* HPR/HPL mux to open */
1540 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1541 0x0f00, 0x0000);
1542
1543 /* Disable low-noise mode of DAC */
1544 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON9,
1545 0x0001, 0x0000);
1546
1547 /* Disable Audio DAC */
1548 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1549 0x000f, 0x0000);
1550
1551 /* Disable AUD_CLK */
1552 mt6359_set_decoder_clk(priv, false);
1553
1554 /* Short HP main output to HP aux output stage */
1555 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3);
1556 /* Enable HP aux output stage */
1557 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf);
1558
1559 /* decrease HPL/R gain to normal gain step by step */
1560 headset_volume_ramp(priv,
1561 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
1562 DL_GAIN_N_22DB);
1563
1564 /* Enable HP aux feedback loop */
1565 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77ff);
1566
1567 /* Reduce HP aux feedback loop gain */
1568 hp_aux_feedback_loop_gain_ramp(priv, false);
1569
1570 /* decrease HPR/L main output stage step by step */
1571 hp_main_output_ramp(priv, false);
1572
1573 /* Disable HP main output stage */
1574 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x3, 0x0);
1575
1576 /* Enable HP aux CMFB loop */
1577 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e01);
1578
1579 /* Disable HP main CMFB loop */
1580 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c01);
1581
1582 /* Decrease HP input pair current to 2'b00 step by step */
1583 hp_in_pair_current(priv, false);
1584
1585 /* Unshort HP main output to HP aux output stage */
1586 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
1587 0x3 << 6, 0x0);
1588
1589 /* Disable HP driver core circuits */
1590 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1591 0x3 << 4, 0x0);
1592
1593 /* Disable HP driver bias circuits */
1594 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1595 0x3 << 6, 0x0);
1596
1597 /* Disable HP aux CMFB loop */
1598 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x201);
1599
1600 /* Disable HP aux feedback loop */
1601 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
1602 0x3 << 4, 0x0);
1603
1604 /* Disable HP aux output stage */
1605 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
1606 0x3 << 2, 0x0);
1607 return 0;
1608}
1609
1610static int mt_hp_event(struct snd_soc_dapm_widget *w,
1611 struct snd_kcontrol *kcontrol,
1612 int event)
1613{
1614 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1615 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1616 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1617 int device = DEVICE_HP;
1618
1619 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
1620 __func__,
1621 event,
1622 priv->dev_counter[device],
1623 mux);
1624
1625 switch (event) {
1626 case SND_SOC_DAPM_PRE_PMU:
1627 priv->dev_counter[device]++;
1628 if (priv->dev_counter[device] > 1)
1629 break; /* already enabled, do nothing */
1630 else if (priv->dev_counter[device] <= 0)
1631 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n",
1632 __func__,
1633 priv->dev_counter[device]);
1634
1635 priv->mux_select[MUX_HP_L] = mux;
1636
1637 if (mux == HP_MUX_HP)
1638 mtk_hp_enable(priv);
1639 break;
1640 case SND_SOC_DAPM_PRE_PMD:
1641 priv->dev_counter[device]--;
1642 if (priv->dev_counter[device] > 0)
1643 break; /* still being used, don't close */
1644 else if (priv->dev_counter[device] < 0) {
1645 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n",
1646 __func__,
1647 priv->dev_counter[device]);
1648 priv->dev_counter[device] = 0;
1649 break;
1650 }
1651
1652 if (priv->mux_select[MUX_HP_L] == HP_MUX_HP)
1653 mtk_hp_disable(priv);
1654
1655 priv->mux_select[MUX_HP_L] = mux;
1656 break;
1657 default:
1658 break;
1659 }
1660
1661 return 0;
1662}
1663
1664static int mt_rcv_event(struct snd_soc_dapm_widget *w,
1665 struct snd_kcontrol *kcontrol,
1666 int event)
1667{
1668 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1669 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1670
1671 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
1672 __func__,
1673 event,
1674 dapm_kcontrol_get_value(w->kcontrols[0]));
1675
1676 switch (event) {
1677 case SND_SOC_DAPM_PRE_PMU:
1678 /* Disable handset short-circuit protection */
1679 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0010);
1680
1681 /* Set RCV DR bias current optimization, 010: 6uA */
1682 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
1683 DRBIAS_HS_MASK_SFT,
1684 DRBIAS_6UA << DRBIAS_HS_SFT);
1685 /* Set RCV & ZCD bias current optimization */
1686 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1687 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
1688 IBIAS_ZCD_MASK_SFT,
1689 IBIAS_ZCD_4UA << IBIAS_ZCD_SFT);
1690 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
1691 IBIAS_HS_MASK_SFT,
1692 IBIAS_5UA << IBIAS_HS_SFT);
1693
1694 /* Set HS STB enhance circuits */
1695 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0090);
1696
1697 /* Set HS output stage (3'b111 = 8x) */
1698 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x7000);
1699
1700 /* Enable HS driver bias circuits */
1701 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0092);
1702 /* Enable HS driver core circuits */
1703 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0093);
1704
1705 /* Set HS gain to normal gain step by step */
1706 regmap_write(priv->regmap, MT6359_ZCD_CON3,
1707 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL]);
1708
1709 /* Enable AUD_CLK */
1710 mt6359_set_decoder_clk(priv, true);
1711
1712 /* Enable Audio DAC */
1713 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x0009);
1714 /* Enable low-noise mode of DAC */
1715 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0001);
1716 /* Switch HS MUX to audio DAC */
1717 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x009b);
1718 break;
1719 case SND_SOC_DAPM_PRE_PMD:
1720 /* HS mux to open */
1721 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
1722 RG_AUDHSMUXINPUTSEL_VAUDP32_MASK_SFT,
1723 RCV_MUX_OPEN);
1724
1725 /* Disable Audio DAC */
1726 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1727 0x000f, 0x0000);
1728
1729 /* Disable AUD_CLK */
1730 mt6359_set_decoder_clk(priv, false);
1731
1732 /* decrease HS gain to minimum gain step by step */
1733 regmap_write(priv->regmap, MT6359_ZCD_CON3, DL_GAIN_N_40DB);
1734
1735 /* Disable HS driver core circuits */
1736 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
1737 RG_AUDHSPWRUP_VAUDP32_MASK_SFT, 0x0);
1738
1739 /* Disable HS driver bias circuits */
1740 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
1741 RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK_SFT, 0x0);
1742 break;
1743 default:
1744 break;
1745 }
1746
1747 return 0;
1748}
1749
1750static int mt_lo_event(struct snd_soc_dapm_widget *w,
1751 struct snd_kcontrol *kcontrol,
1752 int event)
1753{
1754 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1755 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1756
1757 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
1758 __func__,
1759 event,
1760 dapm_kcontrol_get_value(w->kcontrols[0]));
1761
1762 switch (event) {
1763 case SND_SOC_DAPM_PRE_PMU:
1764 /* Disable handset short-circuit protection */
1765 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0010);
1766
1767 /* Set LO DR bias current optimization, 010: 6uA */
1768 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
1769 DRBIAS_LO_MASK_SFT,
1770 DRBIAS_6UA << DRBIAS_LO_SFT);
1771 /* Set LO & ZCD bias current optimization */
1772 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1773 if (priv->dev_counter[DEVICE_HP] == 0)
1774 regmap_update_bits(priv->regmap,
1775 MT6359_AUDDEC_ANA_CON12,
1776 IBIAS_ZCD_MASK_SFT,
1777 IBIAS_ZCD_4UA << IBIAS_ZCD_SFT);
1778
1779 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
1780 IBIAS_LO_MASK_SFT,
1781 IBIAS_5UA << IBIAS_LO_SFT);
1782
1783 /* Set LO STB enhance circuits */
1784 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0110);
1785
1786 /* Enable LO driver bias circuits */
1787 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0112);
1788 /* Enable LO driver core circuits */
1789 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0113);
1790
1791 /* Set LO gain to normal gain step by step */
1792 regmap_write(priv->regmap, MT6359_ZCD_CON1,
1793 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]);
1794
1795 /* Enable AUD_CLK */
1796 mt6359_set_decoder_clk(priv, true);
1797
1798 /* Enable Audio DAC (3rd DAC) */
1799 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x3113);
1800 /* Enable low-noise mode of DAC */
1801 if (priv->dev_counter[DEVICE_HP] == 0)
1802 regmap_write(priv->regmap,
1803 MT6359_AUDDEC_ANA_CON9, 0x0001);
1804 /* Switch LOL MUX to audio 3rd DAC */
1805 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x311b);
1806 break;
1807 case SND_SOC_DAPM_PRE_PMD:
1808 /* Switch LOL MUX to open */
1809 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
1810 RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK_SFT,
1811 LO_MUX_OPEN);
1812
1813 /* Disable Audio DAC */
1814 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1815 0x000f, 0x0000);
1816
1817 /* Disable AUD_CLK */
1818 mt6359_set_decoder_clk(priv, false);
1819
1820 /* decrease LO gain to minimum gain step by step */
1821 regmap_write(priv->regmap, MT6359_ZCD_CON1, DL_GAIN_N_40DB);
1822
1823 /* Disable LO driver core circuits */
1824 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
1825 RG_AUDLOLPWRUP_VAUDP32_MASK_SFT, 0x0);
1826
1827 /* Disable LO driver bias circuits */
1828 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
1829 RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK_SFT, 0x0);
1830 break;
1831 default:
1832 break;
1833 }
1834
1835 return 0;
1836}
1837
1838static int mt_adc_clk_gen_event(struct snd_soc_dapm_widget *w,
1839 struct snd_kcontrol *kcontrol,
1840 int event)
1841{
1842 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1843 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1844
1845 dev_info(priv->dev, "%s(), event 0x%x, vow_enable %d\n",
1846 __func__, event, priv->vow_enable);
1847
1848 switch (event) {
1849 case SND_SOC_DAPM_POST_PMU:
1850 if (priv->vow_enable) {
1851 /* ADC CLK from CLKGEN (3.25MHz) */
1852 dev_info(priv->dev, "%s(), vow mode\n", __func__);
1853 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1854 RG_AUDADCCLKRSTB_MASK_SFT, 0x0);
1855 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1856 RG_AUDADCCLKSOURCE_MASK_SFT,
1857 0x1 << RG_AUDADCCLKSOURCE_SFT);
1858 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1859 RG_AUDADCCLKSEL_MASK_SFT,
1860 0x1 << RG_AUDADCCLKSEL_SFT);
1861 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1862 RG_AUDADCCLKGENMODE_MASK_SFT, 0x0);
1863 } else {
1864 /* ADC CLK from CLKGEN (6.5MHz) */
1865 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1866 RG_AUDADCCLKRSTB_MASK_SFT,
1867 0x1 << RG_AUDADCCLKRSTB_SFT);
1868 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1869 RG_AUDADCCLKSOURCE_MASK_SFT, 0x0);
1870 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1871 RG_AUDADCCLKSEL_MASK_SFT, 0x0);
1872 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1873 RG_AUDADCCLKGENMODE_MASK_SFT,
1874 0x1 << RG_AUDADCCLKGENMODE_SFT);
1875 }
1876 break;
1877 case SND_SOC_DAPM_PRE_PMD:
1878 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1879 RG_AUDADCCLKSOURCE_MASK_SFT, 0x0);
1880 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1881 RG_AUDADCCLKSEL_MASK_SFT, 0x0);
1882 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1883 RG_AUDADCCLKGENMODE_MASK_SFT, 0x0);
1884 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1885 RG_AUDADCCLKRSTB_MASK_SFT, 0x0);
1886 break;
1887 default:
1888 break;
1889 }
1890
1891 return 0;
1892}
1893
1894static int mt_dcc_clk_event(struct snd_soc_dapm_widget *w,
1895 struct snd_kcontrol *kcontrol,
1896 int event)
1897{
1898 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1899 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1900
1901 dev_info(priv->dev, "%s(), event 0x%x\n", __func__, event);
1902
1903 switch (event) {
1904 case SND_SOC_DAPM_PRE_PMU:
1905 /* DCC 50k CLK (from 26M) */
1906 /* MT6359_AFE_DCCLK_CFG0, bit 3 for dm ck swap */
1907 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1908 0xfff7, 0x2062);
1909 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1910 0xfff7, 0x2060);
1911 if (priv->vow_enable)
1912 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1913 0xfff7, 0x2065);
1914 else
1915 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1916 0xfff7, 0x2061);
1917
1918 regmap_write(priv->regmap, MT6359_AFE_DCCLK_CFG1, 0x0100);
1919 break;
1920 case SND_SOC_DAPM_POST_PMD:
1921 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1922 0xfff7, 0x2060);
1923 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1924 0xfff7, 0x2062);
1925 break;
1926 default:
1927 break;
1928 }
1929
1930 return 0;
1931}
1932
1933static int mt_mic_bias_0_event(struct snd_soc_dapm_widget *w,
1934 struct snd_kcontrol *kcontrol,
1935 int event)
1936{
1937 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1938 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1939 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_0];
1940
1941 dev_info(priv->dev, "%s(), event 0x%x, mic_type %d\n",
1942 __func__, event, mic_type);
1943
1944 switch (event) {
1945 case SND_SOC_DAPM_PRE_PMU:
1946 switch (mic_type) {
1947 case MIC_TYPE_MUX_DCC_ECM_DIFF:
1948 case MIC_TYPE_MUX_VOW_DCC_ECM_DIFF:
1949 regmap_update_bits(priv->regmap,
1950 MT6359_AUDENC_ANA_CON15,
1951 0xff00, 0x7700);
1952 break;
1953 case MIC_TYPE_MUX_DCC_ECM_SINGLE:
1954 case MIC_TYPE_MUX_VOW_DCC_ECM_SINGLE:
1955 regmap_update_bits(priv->regmap,
1956 MT6359_AUDENC_ANA_CON15,
1957 0xff00, 0x1100);
1958 break;
1959 default:
1960 regmap_update_bits(priv->regmap,
1961 MT6359_AUDENC_ANA_CON15,
1962 0xff00, 0x0000);
1963 break;
1964 }
1965
1966 /* MISBIAS0 = 1P9V */
1967 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON15,
1968 RG_AUDMICBIAS0VREF_MASK_SFT,
1969 MIC_BIAS_1P9 << RG_AUDMICBIAS0VREF_SFT);
1970 /* vow low power select */
1971 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON15,
1972 RG_AUDMICBIAS0LOWPEN_MASK_SFT,
1973 (IS_VOW_AMIC_BASE(mic_type) ? 1 : 0)
1974 << RG_AUDMICBIAS0LOWPEN_SFT);
1975 break;
1976 case SND_SOC_DAPM_POST_PMD:
1977 /* Disable MICBIAS0, MISBIAS0 = 1P7V */
1978 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON15, 0x0000);
1979 break;
1980 default:
1981 break;
1982 }
1983
1984 return 0;
1985}
1986
1987static int mt_mic_bias_1_event(struct snd_soc_dapm_widget *w,
1988 struct snd_kcontrol *kcontrol,
1989 int event)
1990{
1991 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1992 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1993 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_1];
1994
1995 dev_info(priv->dev, "%s(), event 0x%x, mic_type %d\n",
1996 __func__, event, mic_type);
1997
1998 switch (event) {
1999 case SND_SOC_DAPM_PRE_PMU:
2000 /* MISBIAS1 = 2P6V */
2001 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
2002 regmap_write(priv->regmap,
2003 MT6359_AUDENC_ANA_CON16, 0x0160);
2004 else
2005 regmap_write(priv->regmap,
2006 MT6359_AUDENC_ANA_CON16, 0x0060);
2007
2008 /* vow low power select */
2009 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON16,
2010 RG_AUDMICBIAS1LOWPEN_MASK_SFT,
2011 (IS_VOW_AMIC_BASE(mic_type) ? 1 : 0)
2012 << RG_AUDMICBIAS1LOWPEN_SFT);
2013 break;
2014 default:
2015 break;
2016 }
2017
2018 return 0;
2019}
2020
2021static int mt_mic_bias_2_event(struct snd_soc_dapm_widget *w,
2022 struct snd_kcontrol *kcontrol,
2023 int event)
2024{
2025 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2026 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2027 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_2];
2028
2029 dev_info(priv->dev, "%s(), event 0x%x, mic_type %d\n",
2030 __func__, event, mic_type);
2031
2032 switch (event) {
2033 case SND_SOC_DAPM_PRE_PMU:
2034 switch (mic_type) {
2035 case MIC_TYPE_MUX_DCC_ECM_DIFF:
2036 case MIC_TYPE_MUX_VOW_DCC_ECM_DIFF:
2037 regmap_update_bits(priv->regmap,
2038 MT6359_AUDENC_ANA_CON17,
2039 0xff00, 0x7700);
2040 break;
2041 case MIC_TYPE_MUX_DCC_ECM_SINGLE:
2042 case MIC_TYPE_MUX_VOW_DCC_ECM_SINGLE:
2043 regmap_update_bits(priv->regmap,
2044 MT6359_AUDENC_ANA_CON17,
2045 0xff00, 0x1100);
2046 break;
2047 default:
2048 regmap_update_bits(priv->regmap,
2049 MT6359_AUDENC_ANA_CON17,
2050 0xff00, 0x0000);
2051 break;
2052 }
2053
2054 /* MISBIAS2 = 1P9V */
2055 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON17,
2056 RG_AUDMICBIAS2VREF_MASK_SFT,
2057 MIC_BIAS_1P9 << RG_AUDMICBIAS2VREF_SFT);
2058 /* vow low power select */
2059 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON17,
2060 RG_AUDMICBIAS2LOWPEN_MASK_SFT,
2061 (IS_VOW_BASE(mic_type) ? 1 : 0)
2062 << RG_AUDMICBIAS2LOWPEN_SFT);
2063 break;
2064 case SND_SOC_DAPM_POST_PMD:
2065 /* Disable MICBIAS2, MISBIAS0 = 1P7V */
2066 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON17, 0x0000);
2067 break;
2068 default:
2069 break;
2070 }
2071
2072 return 0;
2073}
2074
2075static int mt_vow_aud_lpw_event(struct snd_soc_dapm_widget *w,
2076 struct snd_kcontrol *kcontrol,
2077 int event)
2078{
2079 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2080 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2081
2082 dev_info(priv->dev, "%s(), event 0x%x\n", __func__, event);
2083
2084 switch (event) {
2085 case SND_SOC_DAPM_PRE_PMU:
2086 /* Enable audio uplink LPW mode */
2087 /* Enable Audio ADC 1st Stage LPW */
2088 /* Enable Audio ADC 2nd & 3rd LPW */
2089 /* Enable Audio ADC flash Audio ADC flash */
2090 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON3,
2091 0x0039, 0x0039);
2092 if (priv->vow_channel == 2)
2093 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON4,
2094 0x0039, 0x0039);
2095 break;
2096 case SND_SOC_DAPM_POST_PMD:
2097 /* Disable audio uplink LPW mode */
2098 /* Disable Audio ADC 1st Stage LPW */
2099 /* Disable Audio ADC 2nd & 3rd LPW */
2100 /* Disable Audio ADC flash Audio ADC flash */
2101 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON3,
2102 0x0039, 0x0000);
2103 if (priv->vow_channel == 2)
2104 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON4,
2105 0x0039, 0x0000);
2106 break;
2107 default:
2108 break;
2109 }
2110 return 0;
2111}
2112
2113static void vow_periodic_on_off_set(struct mt6359_priv *priv)
2114{
2115 regmap_update_bits(priv->regmap,
2116 MT6359_AUD_TOP_CKPDN_CON0,
2117 RG_VOW32K_CK_PDN_MASK_SFT,
2118 0x0);
2119 /* Pre On */
2120 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG2,
2121 priv->vow_periodic_param.pga_on);
2122 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG3,
2123 priv->vow_periodic_param.precg_on);
2124 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG4,
2125 priv->vow_periodic_param.adc_on);
2126 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG7,
2127 priv->vow_periodic_param.micbias0_on);
2128 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG8,
2129 priv->vow_periodic_param.micbias1_on);
2130 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG9,
2131 priv->vow_periodic_param.dcxo_on);
2132 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG10,
2133 priv->vow_periodic_param.audglb_on);
2134 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG11,
2135 priv->vow_periodic_param.vow_on);
2136 /* Delay Off */
2137 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG13,
2138 priv->vow_periodic_param.pga_off);
2139 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG14,
2140 priv->vow_periodic_param.precg_off);
2141 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG15,
2142 priv->vow_periodic_param.adc_off);
2143 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG18,
2144 priv->vow_periodic_param.micbias0_off);
2145 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG19,
2146 priv->vow_periodic_param.micbias1_off);
2147 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG20,
2148 priv->vow_periodic_param.dcxo_off);
2149 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG21,
2150 priv->vow_periodic_param.audglb_off);
2151 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG22,
2152 priv->vow_periodic_param.vow_off);
2153
2154 if (priv->vow_channel == 2) {
2155 /* Pre On */
2156 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG24,
2157 priv->vow_periodic_param.pga_on);
2158 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG25,
2159 priv->vow_periodic_param.precg_on);
2160 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG26,
2161 priv->vow_periodic_param.adc_on);
2162 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG29,
2163 priv->vow_periodic_param.micbias1_on);
2164 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG30,
2165 priv->vow_periodic_param.vow_on);
2166 /* Delay Off */
2167 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG32,
2168 priv->vow_periodic_param.pga_off);
2169 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG33,
2170 priv->vow_periodic_param.precg_off);
2171 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG34,
2172 priv->vow_periodic_param.adc_off);
2173 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG37,
2174 priv->vow_periodic_param.micbias1_off);
2175 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG38,
2176 priv->vow_periodic_param.vow_off);
2177 }
2178 /* vow periodic enable */
2179 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG0, 0x999A);
2180}
2181
2182static void vow_periodic_on_off_reset(struct mt6359_priv *priv)
2183{
2184 regmap_update_bits(priv->regmap,
2185 MT6359_AUD_TOP_CKPDN_CON0,
2186 RG_VOW32K_CK_PDN_MASK_SFT,
2187 0x1 << RG_VOW32K_CK_PDN_SFT);
2188 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG0, 0x0);
2189 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG1, 0x0);
2190 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG2, 0x0);
2191 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG3, 0x0);
2192 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG4, 0x0);
2193 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG5, 0x0);
2194 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG6, 0x0);
2195 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG7, 0x0);
2196 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG8, 0x0);
2197 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG9, 0x0);
2198 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG10, 0x0);
2199 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG11, 0x0);
2200 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG12, 0x0);
2201 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG13, 0x8000);
2202 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG14, 0x0);
2203 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG15, 0x0);
2204 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG16, 0x0);
2205 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG17, 0x0);
2206 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG18, 0x0);
2207 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG19, 0x0);
2208 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG20, 0x0);
2209 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG21, 0x0);
2210 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG22, 0x0);
2211 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG23, 0x0);
2212 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG24, 0x0);
2213 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG25, 0x0);
2214 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG26, 0x0);
2215 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG27, 0x0);
2216 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG28, 0x0);
2217 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG29, 0x0);
2218 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG30, 0x0);
2219 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG31, 0x0);
2220 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG32, 0x0);
2221 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG33, 0x0);
2222 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG34, 0x0);
2223 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG35, 0x0);
2224 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG36, 0x0);
2225 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG37, 0x0);
2226 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG38, 0x0);
2227 regmap_write(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG39, 0x0);
2228}
2229
2230static int mt_vow_periodic_cfg_event(struct snd_soc_dapm_widget *w,
2231 struct snd_kcontrol *kcontrol,
2232 int event)
2233{
2234 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2235 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2236
2237 dev_info(priv->dev, "%s(), event 0x%x\n", __func__, event);
2238 switch (event) {
2239 case SND_SOC_DAPM_PRE_PMU:
2240 /* Periodic On/Off */
2241 if (priv->reg_afe_vow_periodic == 0)
2242 vow_periodic_on_off_reset(priv);
2243 else
2244 vow_periodic_on_off_set(priv);
2245 break;
2246 case SND_SOC_DAPM_POST_PMD:
2247 vow_periodic_on_off_reset(priv);
2248 break;
2249 default:
2250 break;
2251 }
2252 return 0;
2253}
2254
2255/* VOW MTKIF TX setting */
2256enum {
2257 VOW_MTKIF_TX_SET_MONO = 1,
2258 VOW_MTKIF_TX_SET_STEREO = 0,
2259};
2260
2261#define VOW_MCLK 13000
2262#define VOW_MTKIF_TX_MONO_CLK 650
2263#define VOW_MTKIF_TX_STEREO_CLK 1083
2264
2265static int mt_vow_digital_cfg_event(struct snd_soc_dapm_widget *w,
2266 struct snd_kcontrol *kcontrol,
2267 int event)
2268{
2269 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2270 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2271 unsigned int mic_type0 = priv->mux_select[MUX_MIC_TYPE_0];
2272 unsigned int mic_type2 = priv->mux_select[MUX_MIC_TYPE_2];
2273 unsigned int vow_ch = 0;
2274 unsigned int vow_mtkif_tx_div = 0;
2275 unsigned int vow_top_con3 = 0x0000;
2276 unsigned int is_dmic = 0;
2277
2278 dev_info(priv->dev, "%s(), event 0x%x\n", __func__, event);
2279
2280 switch (event) {
2281 case SND_SOC_DAPM_POST_PMU:
2282 /* AMIC/DMIC VOW Config Setting */
2283 if ((mic_type0 == MIC_TYPE_MUX_VOW_DMIC_LP) ||
2284 (mic_type2 == MIC_TYPE_MUX_VOW_DMIC_LP)) {
2285 /* LP DMIC settings : 812.5k */
2286 regmap_update_bits(priv->regmap,
2287 MT6359_AFE_VOW_TOP_CON0,
2288 0x7C00, 0x3800);
2289 is_dmic = 1;
2290 } else if ((mic_type0 == MIC_TYPE_MUX_VOW_DMIC) ||
2291 (mic_type2 == MIC_TYPE_MUX_VOW_DMIC)) {
2292 /* DMIC settings : 1600k */
2293 regmap_update_bits(priv->regmap,
2294 MT6359_AFE_VOW_TOP_CON0,
2295 0x7C00, 0x1000);
2296 is_dmic = 1;
2297 } else {
2298 /* AMIC settings */
2299 regmap_update_bits(priv->regmap,
2300 MT6359_AFE_VOW_TOP_CON0,
2301 0x7C00, 0x0000);
2302 is_dmic = 0;
2303 }
2304
2305 /* Enable vow cfg setting */
2306 /* VOW CH1 Config */
2307 regmap_write(priv->regmap, MT6359_AFE_VOW_VAD_CFG0,
2308 priv->reg_afe_vow_vad_cfg0);
2309 regmap_write(priv->regmap, MT6359_AFE_VOW_VAD_CFG2,
2310 priv->reg_afe_vow_vad_cfg1);
2311 regmap_write(priv->regmap, MT6359_AFE_VOW_VAD_CFG4,
2312 priv->reg_afe_vow_vad_cfg2);
2313 regmap_write(priv->regmap, MT6359_AFE_VOW_VAD_CFG6,
2314 priv->reg_afe_vow_vad_cfg3);
2315 regmap_update_bits(priv->regmap, MT6359_AFE_VOW_VAD_CFG12,
2316 K_GAMMA_CH1_MASK_SFT,
2317 priv->reg_afe_vow_vad_cfg4
2318 << K_GAMMA_CH1_SFT);
2319 regmap_write(priv->regmap, MT6359_AFE_VOW_VAD_CFG8,
2320 priv->reg_afe_vow_vad_cfg5);
2321 if (is_dmic) {
2322 /* VOW CH1 */
2323 /* VOW ADC clk gate power off */
2324 regmap_update_bits(priv->regmap,
2325 MT6359_AFE_VOW_TOP_CON1,
2326 VOW_ADC_CK_PDN_CH1_MASK_SFT,
2327 0x1 << VOW_ADC_CK_PDN_CH1_SFT);
2328 /* VOW clk gate power on */
2329 regmap_update_bits(priv->regmap,
2330 MT6359_AFE_VOW_TOP_CON1,
2331 VOW_CK_PDN_CH1_MASK_SFT,
2332 0x0);
2333 /* DMIC power on */
2334 /* DMIC select: dmic */
2335 regmap_update_bits(priv->regmap,
2336 MT6359_AFE_VOW_TOP_CON1,
2337 0x3 << VOW_DIGMIC_ON_CH1_SFT,
2338 0x1 << VOW_DIGMIC_ON_CH1_SFT);
2339 } else {
2340 /* VOW CH1 */
2341 /* VOW ADC clk gate power on */
2342 regmap_update_bits(priv->regmap,
2343 MT6359_AFE_VOW_TOP_CON1,
2344 VOW_ADC_CK_PDN_CH1_MASK_SFT,
2345 0x0);
2346 /* VOW clk gate power on */
2347 regmap_update_bits(priv->regmap,
2348 MT6359_AFE_VOW_TOP_CON1,
2349 VOW_CK_PDN_CH1_MASK_SFT,
2350 0x0);
2351 /* DMIC power off */
2352 /* DMIC select: amic */
2353 regmap_update_bits(priv->regmap,
2354 MT6359_AFE_VOW_TOP_CON1,
2355 0x3 << VOW_DIGMIC_ON_CH1_SFT,
2356 0x2 << VOW_DIGMIC_ON_CH1_SFT);
2357 }
2358 /* MTKIF TX Setting */
2359 vow_ch = VOW_MTKIF_TX_SET_MONO; /* mono */
2360 vow_mtkif_tx_div = VOW_MCLK / (VOW_MTKIF_TX_MONO_CLK * 2);
2361
2362 /* VOW CH2 Config */
2363 if (priv->vow_channel == 2) {
2364 regmap_write(priv->regmap, MT6359_AFE_VOW_VAD_CFG1,
2365 priv->reg_afe_vow_vad_cfg0);
2366 regmap_write(priv->regmap, MT6359_AFE_VOW_VAD_CFG3,
2367 priv->reg_afe_vow_vad_cfg1);
2368 regmap_write(priv->regmap, MT6359_AFE_VOW_VAD_CFG5,
2369 priv->reg_afe_vow_vad_cfg2);
2370 regmap_write(priv->regmap, MT6359_AFE_VOW_VAD_CFG7,
2371 priv->reg_afe_vow_vad_cfg3);
2372 regmap_update_bits(priv->regmap,
2373 MT6359_AFE_VOW_VAD_CFG12,
2374 K_GAMMA_CH2_MASK_SFT,
2375 priv->reg_afe_vow_vad_cfg4
2376 << K_GAMMA_CH2_SFT);
2377 regmap_write(priv->regmap, MT6359_AFE_VOW_VAD_CFG9,
2378 priv->reg_afe_vow_vad_cfg5);
2379 if (is_dmic) {
2380 /* VOW CH2 */
2381 /* VOW ADC clk gate power off */
2382 regmap_update_bits(priv->regmap,
2383 MT6359_AFE_VOW_TOP_CON2,
2384 VOW_ADC_CK_PDN_CH2_MASK_SFT,
2385 0x1 << VOW_ADC_CK_PDN_CH2_SFT);
2386 /* VOW clk gate power on */
2387 regmap_update_bits(priv->regmap,
2388 MT6359_AFE_VOW_TOP_CON2,
2389 VOW_CK_PDN_CH2_MASK_SFT,
2390 0x0);
2391 /* DMIC power on */
2392 /* DMIC select: dmic */
2393 regmap_update_bits(priv->regmap,
2394 MT6359_AFE_VOW_TOP_CON2,
2395 0x3 << VOW_DIGMIC_ON_CH2_SFT,
2396 0x1 << VOW_DIGMIC_ON_CH2_SFT);
2397 } else {
2398 /* VOW CH2 */
2399 /* VOW ADC clk gate power on */
2400 regmap_update_bits(priv->regmap,
2401 MT6359_AFE_VOW_TOP_CON2,
2402 VOW_ADC_CK_PDN_CH2_MASK_SFT,
2403 0x0);
2404 /* VOW clk gate power on */
2405 regmap_update_bits(priv->regmap,
2406 MT6359_AFE_VOW_TOP_CON2,
2407 VOW_CK_PDN_CH2_MASK_SFT,
2408 0x0);
2409 /* DMIC power off */
2410 /* DMIC select: amic */
2411 regmap_update_bits(priv->regmap,
2412 MT6359_AFE_VOW_TOP_CON2,
2413 0x3 << VOW_DIGMIC_ON_CH2_SFT,
2414 0x2 << VOW_DIGMIC_ON_CH2_SFT);
2415 }
2416 /* MTKIF TX Setting */
2417 vow_ch = VOW_MTKIF_TX_SET_STEREO; /* stereo */
2418 /* MTKIF TX DIV */
2419 vow_mtkif_tx_div = VOW_MCLK /
2420 (VOW_MTKIF_TX_STEREO_CLK * 2);
2421 }
2422 vow_top_con3 = 0x0000;
2423 /* disable SNRDET Auto power down */
2424 vow_top_con3 |= (1 << VOW_P2_SNRDET_AUTO_PDN_SFT);
2425 vow_top_con3 |= (vow_ch << VOW_TXIF_MONO_SFT);
2426 vow_top_con3 |= (vow_mtkif_tx_div << VOW_TXIF_SCK_DIV_SFT);
2427 regmap_write(priv->regmap, MT6359_AFE_VOW_TOP_CON3,
2428 vow_top_con3);
2429 break;
2430 case SND_SOC_DAPM_PRE_PMD:
2431 /* AMIC/DMIC VOW Config Setting */
2432 /* AMIC settings */
2433 regmap_update_bits(priv->regmap, MT6359_AFE_VOW_TOP_CON0,
2434 0x7C00, 0x0000);
2435 /* VOW CH1 */
2436 /* VOW ADC clk gate power off */
2437 regmap_update_bits(priv->regmap,
2438 MT6359_AFE_VOW_TOP_CON1,
2439 VOW_ADC_CK_PDN_CH1_MASK_SFT,
2440 0x1 << VOW_ADC_CK_PDN_CH1_SFT);
2441 /* VOW clk gate power off */
2442 regmap_update_bits(priv->regmap,
2443 MT6359_AFE_VOW_TOP_CON1,
2444 VOW_CK_PDN_CH1_MASK_SFT,
2445 0x1 << VOW_CK_PDN_CH1_SFT);
2446 /* DMIC power off */
2447 /* DMIC select: amic */
2448 regmap_update_bits(priv->regmap,
2449 MT6359_AFE_VOW_TOP_CON1,
2450 0x3 << VOW_DIGMIC_ON_CH1_SFT,
2451 0x2 << VOW_DIGMIC_ON_CH1_SFT);
2452 /* VOW CH2 */
2453 /* VOW ADC clk gate power off */
2454 regmap_update_bits(priv->regmap,
2455 MT6359_AFE_VOW_TOP_CON2,
2456 VOW_ADC_CK_PDN_CH2_MASK_SFT,
2457 0x1 << VOW_ADC_CK_PDN_CH2_SFT);
2458 /* VOW clk gate power off */
2459 regmap_update_bits(priv->regmap,
2460 MT6359_AFE_VOW_TOP_CON2,
2461 VOW_CK_PDN_CH2_MASK_SFT,
2462 0x1 << VOW_CK_PDN_CH2_SFT);
2463 /* DMIC power off */
2464 /* DMIC select: amic */
2465 regmap_update_bits(priv->regmap,
2466 MT6359_AFE_VOW_TOP_CON2,
2467 0x3 << VOW_DIGMIC_ON_CH2_SFT,
2468 0x2 << VOW_DIGMIC_ON_CH2_SFT);
2469 break;
2470 default:
2471 break;
2472 }
2473 return 0;
2474}
2475
2476static int mt_vow_out_event(struct snd_soc_dapm_widget *w,
2477 struct snd_kcontrol *kcontrol,
2478 int event)
2479{
2480 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2481 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2482
2483 dev_info(priv->dev, "%s(), event 0x%x\n", __func__, event);
2484
2485 switch (event) {
2486 case SND_SOC_DAPM_WILL_PMU:
2487 priv->vow_enable = 1;
2488 break;
2489 case SND_SOC_DAPM_PRE_PMU:
2490 vow_gpio_set(priv);
2491 break;
2492 case SND_SOC_DAPM_POST_PMD:
2493 vow_gpio_reset(priv);
2494 priv->vow_enable = 0;
2495 break;
2496 default:
2497 break;
2498 }
2499
2500 return 0;
2501}
2502
2503static int mt_mtkaif_tx_event(struct snd_soc_dapm_widget *w,
2504 struct snd_kcontrol *kcontrol,
2505 int event)
2506{
2507 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2508 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2509
2510 dev_info(priv->dev, "%s(), event = 0x%x\n", __func__, event);
2511
2512 switch (event) {
2513 case SND_SOC_DAPM_PRE_PMU:
2514 mt6359_mtkaif_tx_enable(priv);
2515 break;
2516 case SND_SOC_DAPM_POST_PMD:
2517 mt6359_mtkaif_tx_disable(priv);
2518 break;
2519 default:
2520 break;
2521 }
2522
2523 return 0;
2524}
2525
2526static int mt_ul_src_dmic_event(struct snd_soc_dapm_widget *w,
2527 struct snd_kcontrol *kcontrol,
2528 int event)
2529{
2530 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2531 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2532
2533 dev_info(priv->dev, "%s(), event = 0x%x\n", __func__, event);
2534
2535 switch (event) {
2536 case SND_SOC_DAPM_PRE_PMU:
2537 /* default two wire, 3.25M */
2538 regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_H, 0x0080);
2539 regmap_update_bits(priv->regmap, MT6359_AFE_UL_SRC_CON0_L,
2540 0xfffc, 0x0000);
2541 break;
2542 case SND_SOC_DAPM_POST_PMD:
2543 regmap_write(priv->regmap,
2544 MT6359_AFE_UL_SRC_CON0_H, 0x0000);
2545 break;
2546 default:
2547 break;
2548 }
2549
2550 return 0;
2551}
2552
2553static int mt_ul_src_34_dmic_event(struct snd_soc_dapm_widget *w,
2554 struct snd_kcontrol *kcontrol,
2555 int event)
2556{
2557 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2558 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2559
2560 dev_info(priv->dev, "%s(), event = 0x%x\n", __func__, event);
2561
2562 switch (event) {
2563 case SND_SOC_DAPM_PRE_PMU:
2564 /* default two wire, 3.25M */
2565 regmap_write(priv->regmap,
2566 MT6359_AFE_ADDA6_L_SRC_CON0_H, 0x0080);
2567 regmap_update_bits(priv->regmap, MT6359_AFE_ADDA6_UL_SRC_CON0_L,
2568 0xfffc, 0x0000);
2569 break;
2570 case SND_SOC_DAPM_POST_PMD:
2571 regmap_write(priv->regmap,
2572 MT6359_AFE_ADDA6_L_SRC_CON0_H, 0x0000);
2573 break;
2574 default:
2575 break;
2576 }
2577
2578 return 0;
2579}
2580
2581static int mt_adc_l_event(struct snd_soc_dapm_widget *w,
2582 struct snd_kcontrol *kcontrol,
2583 int event)
2584{
2585 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2586 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2587
2588 dev_info(priv->dev, "%s(), event = 0x%x\n", __func__, event);
2589
2590 switch (event) {
2591 case SND_SOC_DAPM_POST_PMU:
2592 usleep_range(100, 120);
2593 /* Audio L preamplifier DCC precharge off */
2594 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
2595 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT,
2596 0x0);
2597 break;
2598 default:
2599 break;
2600 }
2601
2602 return 0;
2603}
2604
2605static int mt_adc_r_event(struct snd_soc_dapm_widget *w,
2606 struct snd_kcontrol *kcontrol,
2607 int event)
2608{
2609 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2610 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2611
2612 dev_info(priv->dev, "%s(), event = 0x%x\n", __func__, event);
2613
2614 switch (event) {
2615 case SND_SOC_DAPM_POST_PMU:
2616 usleep_range(100, 120);
2617 /* Audio R preamplifier DCC precharge off */
2618 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
2619 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT,
2620 0x0);
2621 break;
2622 default:
2623 break;
2624 }
2625
2626 return 0;
2627}
2628
2629static int mt_adc_3_event(struct snd_soc_dapm_widget *w,
2630 struct snd_kcontrol *kcontrol,
2631 int event)
2632{
2633 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2634 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2635
2636 dev_info(priv->dev, "%s(), event = 0x%x\n", __func__, event);
2637
2638 switch (event) {
2639 case SND_SOC_DAPM_POST_PMU:
2640 usleep_range(100, 120);
2641 /* Audio R preamplifier DCC precharge off */
2642 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
2643 RG_AUDPREAMP3DCPRECHARGE_MASK_SFT,
2644 0x0);
2645 break;
2646 default:
2647 break;
2648 }
2649
2650 return 0;
2651}
2652
2653static int mt_pga_l_mux_event(struct snd_soc_dapm_widget *w,
2654 struct snd_kcontrol *kcontrol,
2655 int event)
2656{
2657 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2658 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2659 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
2660
2661 dev_info(priv->dev, "%s(), mux %d\n", __func__, mux);
2662 priv->mux_select[MUX_PGA_L] = mux >> RG_AUDPREAMPLINPUTSEL_SFT;
2663 return 0;
2664}
2665
2666static int mt_pga_r_mux_event(struct snd_soc_dapm_widget *w,
2667 struct snd_kcontrol *kcontrol,
2668 int event)
2669{
2670 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2671 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2672 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
2673
2674 dev_info(priv->dev, "%s(), mux %d\n", __func__, mux);
2675 priv->mux_select[MUX_PGA_R] = mux >> RG_AUDPREAMPRINPUTSEL_SFT;
2676 return 0;
2677}
2678
2679static int mt_pga_3_mux_event(struct snd_soc_dapm_widget *w,
2680 struct snd_kcontrol *kcontrol,
2681 int event)
2682{
2683 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2684 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2685 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
2686
2687 dev_info(priv->dev, "%s(), mux %d\n", __func__, mux);
2688 priv->mux_select[MUX_PGA_3] = mux >> RG_AUDPREAMP3INPUTSEL_SFT;
2689 return 0;
2690}
2691
2692static int mt_pga_l_event(struct snd_soc_dapm_widget *w,
2693 struct snd_kcontrol *kcontrol,
2694 int event)
2695{
2696 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2697 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2698 int mic_gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
2699 unsigned int mux_pga = priv->mux_select[MUX_PGA_L];
2700 unsigned int mic_type;
2701
2702 switch (mux_pga) {
2703 case PGA_L_MUX_AIN0:
2704 mic_type = priv->mux_select[MUX_MIC_TYPE_0];
2705 break;
2706 case PGA_L_MUX_AIN1:
2707 mic_type = priv->mux_select[MUX_MIC_TYPE_1];
2708 break;
2709 default:
2710 dev_err(priv->dev, "%s(), invalid pga mux %d\n",
2711 __func__, mux_pga);
2712 return -EINVAL;
2713 }
2714 /* if is VOW, then force 24dB */
2715 if (IS_VOW_BASE(mic_type))
2716 mic_gain_l = 4;
2717 dev_dbg(priv->dev, "%s(), event = 0x%x, mic_type %d, mic_gain_l %d, mux_pga %d\n",
2718 __func__, event, mic_type, mic_gain_l, mux_pga);
2719
2720 switch (event) {
2721 case SND_SOC_DAPM_PRE_PMU:
2722 if (IS_DCC_BASE(mic_type)) {
2723 /* Audio L preamplifier DCC precharge */
2724 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
2725 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT,
2726 0x1 << RG_AUDPREAMPLDCPRECHARGE_SFT);
2727 }
2728 break;
2729 case SND_SOC_DAPM_POST_PMU:
2730 /* set mic pga gain */
2731 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
2732 RG_AUDPREAMPLGAIN_MASK_SFT,
2733 mic_gain_l << RG_AUDPREAMPLGAIN_SFT);
2734
2735 if (IS_DCC_BASE(mic_type)) {
2736 /* L preamplifier DCCEN */
2737 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
2738 RG_AUDPREAMPLDCCEN_MASK_SFT,
2739 0x1 << RG_AUDPREAMPLDCCEN_SFT);
2740 }
2741 break;
2742 case SND_SOC_DAPM_POST_PMD:
2743 /* L preamplifier DCCEN */
2744 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
2745 RG_AUDPREAMPLDCCEN_MASK_SFT,
2746 0x0 << RG_AUDPREAMPLDCCEN_SFT);
2747 break;
2748 default:
2749 break;
2750 }
2751
2752 return 0;
2753}
2754
2755static int mt_pga_r_event(struct snd_soc_dapm_widget *w,
2756 struct snd_kcontrol *kcontrol,
2757 int event)
2758{
2759 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2760 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2761 int mic_gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
2762 unsigned int mux_pga = priv->mux_select[MUX_PGA_R];
2763 unsigned int mic_type;
2764
2765 switch (mux_pga) {
2766 case PGA_R_MUX_AIN0:
2767 mic_type = priv->mux_select[MUX_MIC_TYPE_0];
2768 break;
2769 case PGA_R_MUX_AIN2:
2770 case PGA_R_MUX_AIN3:
2771 mic_type = priv->mux_select[MUX_MIC_TYPE_2];
2772 break;
2773 default:
2774 dev_err(priv->dev, "%s(), invalid pga mux %d\n",
2775 __func__, mux_pga);
2776 return -EINVAL;
2777 }
2778 /* if is VOW, then force 24dB */
2779 if (IS_VOW_BASE(mic_type))
2780 mic_gain_r = 4;
2781 dev_dbg(priv->dev, "%s(), event = 0x%x, mic_type %d, mic_gain_r %d, mux_pga %d\n",
2782 __func__, event, mic_type, mic_gain_r, mux_pga);
2783
2784 switch (event) {
2785 case SND_SOC_DAPM_PRE_PMU:
2786 if (IS_DCC_BASE(mic_type)) {
2787 /* Audio R preamplifier DCC precharge */
2788 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
2789 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT,
2790 0x1 << RG_AUDPREAMPRDCPRECHARGE_SFT);
2791 }
2792 break;
2793 case SND_SOC_DAPM_POST_PMU:
2794 /* set mic pga gain */
2795 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
2796 RG_AUDPREAMPRGAIN_MASK_SFT,
2797 mic_gain_r << RG_AUDPREAMPRGAIN_SFT);
2798
2799 if (IS_DCC_BASE(mic_type)) {
2800 /* R preamplifier DCCEN */
2801 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
2802 RG_AUDPREAMPRDCCEN_MASK_SFT,
2803 0x1 << RG_AUDPREAMPRDCCEN_SFT);
2804 }
2805 break;
2806 case SND_SOC_DAPM_POST_PMD:
2807 /* R preamplifier DCCEN */
2808 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
2809 RG_AUDPREAMPRDCCEN_MASK_SFT,
2810 0x0 << RG_AUDPREAMPRDCCEN_SFT);
2811 break;
2812 default:
2813 break;
2814 }
2815
2816 return 0;
2817}
2818
2819static int mt_pga_3_event(struct snd_soc_dapm_widget *w,
2820 struct snd_kcontrol *kcontrol,
2821 int event)
2822{
2823 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2824 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2825 int mic_gain_3 = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3];
2826 unsigned int mux_pga = priv->mux_select[MUX_PGA_3];
2827 unsigned int mic_type;
2828
2829 switch (mux_pga) {
2830 case PGA_3_MUX_AIN2:
2831 case PGA_3_MUX_AIN3:
2832 mic_type = priv->mux_select[MUX_MIC_TYPE_2];
2833 break;
2834 default:
2835 dev_err(priv->dev, "%s(), invalid pga mux %d\n",
2836 __func__, mux_pga);
2837 return -EINVAL;
2838 }
2839 /* if is VOW, then force 24dB */
2840 if (IS_VOW_BASE(mic_type))
2841 mic_gain_3 = 4;
2842 dev_dbg(priv->dev, "%s(), event = 0x%x, mic_type %d, mic_gain_3 %d, mux_pga %d\n",
2843 __func__, event, mic_type, mic_gain_3, mux_pga);
2844
2845 switch (event) {
2846 case SND_SOC_DAPM_PRE_PMU:
2847 if (IS_DCC_BASE(mic_type)) {
2848 /* Audio 3 preamplifier DCC precharge */
2849 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
2850 RG_AUDPREAMP3DCPRECHARGE_MASK_SFT,
2851 0x1 << RG_AUDPREAMP3DCPRECHARGE_SFT);
2852 }
2853 break;
2854 case SND_SOC_DAPM_POST_PMU:
2855 /* set mic pga gain */
2856 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
2857 RG_AUDPREAMP3GAIN_MASK_SFT,
2858 mic_gain_3 << RG_AUDPREAMP3GAIN_SFT);
2859
2860 if (IS_DCC_BASE(mic_type)) {
2861 /* 3 preamplifier DCCEN */
2862 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
2863 RG_AUDPREAMP3DCCEN_MASK_SFT,
2864 0x1 << RG_AUDPREAMP3DCCEN_SFT);
2865 }
2866 break;
2867 case SND_SOC_DAPM_POST_PMD:
2868 /* 3 preamplifier DCCEN */
2869 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
2870 RG_AUDPREAMP3DCCEN_MASK_SFT,
2871 0x0 << RG_AUDPREAMP3DCCEN_SFT);
2872 break;
2873 default:
2874 break;
2875 }
2876
2877 return 0;
2878}
2879
2880static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
2881 struct snd_kcontrol *kcontrol,
2882 int event)
2883{
2884 switch (event) {
2885 case SND_SOC_DAPM_POST_PMU:
2886 case SND_SOC_DAPM_PRE_PMD:
2887 usleep_range(250, 270);
2888 break;
2889 default:
2890 break;
2891 }
2892
2893 return 0;
2894}
2895
2896static int mt_delay_100_event(struct snd_soc_dapm_widget *w,
2897 struct snd_kcontrol *kcontrol,
2898 int event)
2899{
2900 switch (event) {
2901 case SND_SOC_DAPM_POST_PMU:
2902 case SND_SOC_DAPM_PRE_PMD:
2903 usleep_range(100, 120);
2904 break;
2905 default:
2906 break;
2907 }
2908
2909 return 0;
2910}
2911
2912static int mt_hp_pull_down_event(struct snd_soc_dapm_widget *w,
2913 struct snd_kcontrol *kcontrol,
2914 int event)
2915{
2916 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2917 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2918
2919 switch (event) {
2920 case SND_SOC_DAPM_PRE_PMU:
2921 hp_pull_down(priv, true);
2922 break;
2923 case SND_SOC_DAPM_POST_PMD:
2924 hp_pull_down(priv, false);
2925 break;
2926 default:
2927 break;
2928 }
2929
2930 return 0;
2931}
2932
2933static int mt_hp_mute_event(struct snd_soc_dapm_widget *w,
2934 struct snd_kcontrol *kcontrol,
2935 int event)
2936{
2937 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2938 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2939
2940 switch (event) {
2941 case SND_SOC_DAPM_PRE_PMU:
2942 /* Set HPR/HPL gain to -22dB */
2943 regmap_write(priv->regmap, MT6359_ZCD_CON2, DL_GAIN_N_22DB_REG);
2944 break;
2945 case SND_SOC_DAPM_POST_PMD:
2946 /* Set HPL/HPR gain to mute */
2947 regmap_write(priv->regmap, MT6359_ZCD_CON2, DL_GAIN_N_40DB_REG);
2948 break;
2949 default:
2950 break;
2951 }
2952
2953 return 0;
2954}
2955
2956static int mt_hp_damp_event(struct snd_soc_dapm_widget *w,
2957 struct snd_kcontrol *kcontrol,
2958 int event)
2959{
2960 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2961 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2962
2963 switch (event) {
2964 case SND_SOC_DAPM_POST_PMD:
2965 /* Disable HP damping circuit & HPN 4K load */
2966 /* reset CMFB PW level */
2967 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0000);
2968 break;
2969 default:
2970 break;
2971 }
2972
2973 return 0;
2974}
2975
2976static int mt_esd_resist_event(struct snd_soc_dapm_widget *w,
2977 struct snd_kcontrol *kcontrol,
2978 int event)
2979{
2980 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2981 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2982
2983 switch (event) {
2984 case SND_SOC_DAPM_PRE_PMU:
2985 /* Reduce ESD resistance of AU_REFN */
2986 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
2987 RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT,
2988 0x1 << RG_AUDREFN_DERES_EN_VAUDP32_SFT);
2989 usleep_range(250, 270);
2990 break;
2991 case SND_SOC_DAPM_POST_PMD:
2992 /* Increase ESD resistance of AU_REFN */
2993 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
2994 RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT, 0x0);
2995 break;
2996 default:
2997 break;
2998 }
2999
3000 return 0;
3001}
3002
3003static int mt_sdm_event(struct snd_soc_dapm_widget *w,
3004 struct snd_kcontrol *kcontrol,
3005 int event)
3006{
3007 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
3008 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
3009
3010 switch (event) {
3011 case SND_SOC_DAPM_PRE_PMU:
3012 /* sdm audio fifo clock power on */
3013 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
3014 0xfffd, 0x0006);
3015 /* scrambler clock on enable */
3016 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xCBA1);
3017 /* sdm power on */
3018 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
3019 0xfffd, 0x0003);
3020 /* sdm fifo enable */
3021 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
3022 0xfffd, 0x000B);
3023 break;
3024 case SND_SOC_DAPM_POST_PMD:
3025 /* DL scrambler disabling sequence */
3026 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
3027 0xfffd, 0x0000);
3028 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0);
3029 break;
3030 default:
3031 break;
3032 }
3033 return 0;
3034}
3035
3036static int mt_sdm_3rd_event(struct snd_soc_dapm_widget *w,
3037 struct snd_kcontrol *kcontrol,
3038 int event)
3039{
3040 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
3041 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
3042
3043 switch (event) {
3044 case SND_SOC_DAPM_PRE_PMU:
3045 /* sdm audio fifo clock power on */
3046 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0006);
3047 /* scrambler clock on enable */
3048 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xCBA1);
3049 /* sdm power on */
3050 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0003);
3051 /* sdm fifo enable */
3052 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x000B);
3053 break;
3054 case SND_SOC_DAPM_POST_PMD:
3055 /* DL scrambler disabling sequence */
3056 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0000);
3057 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba0);
3058 break;
3059 default:
3060 break;
3061 }
3062 return 0;
3063}
3064
3065static int mt_ncp_event(struct snd_soc_dapm_widget *w,
3066 struct snd_kcontrol *kcontrol,
3067 int event)
3068{
3069 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
3070 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
3071
3072 switch (event) {
3073 case SND_SOC_DAPM_PRE_PMU:
3074 regmap_write(priv->regmap, MT6359_AFE_NCP_CFG0, 0xc800);
3075 break;
3076 default:
3077 break;
3078 }
3079 return 0;
3080}
3081
3082static int mt_dl_gpio_event(struct snd_soc_dapm_widget *w,
3083 struct snd_kcontrol *kcontrol,
3084 int event)
3085{
3086 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
3087 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
3088
3089 switch (event) {
3090 case SND_SOC_DAPM_PRE_PMU:
3091 playback_gpio_set(priv);
3092 break;
3093 case SND_SOC_DAPM_POST_PMD:
3094 playback_gpio_reset(priv);
3095 break;
3096 default:
3097 break;
3098 }
3099 return 0;
3100}
3101
3102static int mt_ul_gpio_event(struct snd_soc_dapm_widget *w,
3103 struct snd_kcontrol *kcontrol,
3104 int event)
3105{
3106 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
3107 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
3108
3109 switch (event) {
3110 case SND_SOC_DAPM_PRE_PMU:
3111 capture_gpio_set(priv);
3112 break;
3113 case SND_SOC_DAPM_POST_PMD:
3114 capture_gpio_reset(priv);
3115 break;
3116 default:
3117 break;
3118 }
3119 return 0;
3120}
3121
3122/* DAPM Widgets */
3123static const struct snd_soc_dapm_widget mt6359_dapm_widgets[] = {
3124 /* Global Supply*/
3125 SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
3126 MT6359_DCXO_CW12,
3127 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
3128 SND_SOC_DAPM_SUPPLY_S("LDO_VAUD18", SUPPLY_SEQ_LDO_VAUD18,
3129 MT6359_LDO_VAUD18_CON0,
3130 RG_LDO_VAUD18_EN_SFT, 0, NULL, 0),
3131 SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
3132 MT6359_AUDDEC_ANA_CON13,
3133 RG_AUDGLB_PWRDN_VA32_SFT, 1, NULL, 0),
3134 SND_SOC_DAPM_SUPPLY_S("AUDGLB_VOW", SUPPLY_SEQ_AUD_GLB_VOW,
3135 MT6359_AUDDEC_ANA_CON13,
3136 RG_AUDGLB_LP2_VOW_EN_VA32_SFT, 0, NULL, 0),
3137 SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
3138 MT6359_AUDENC_ANA_CON23,
3139 RG_CLKSQ_EN_SFT, 0,
3140 mt_clksq_event,
3141 SND_SOC_DAPM_PRE_PMU),
3142 SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
3143 MT6359_AUD_TOP_CKPDN_CON0,
3144 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
3145 SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
3146 MT6359_AUD_TOP_CKPDN_CON0,
3147 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
3148 SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
3149 MT6359_AUD_TOP_CKPDN_CON0,
3150 RG_AUD_CK_PDN_SFT, 1,
3151 mt_delay_250_event,
3152 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
3153 SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
3154 MT6359_AUD_TOP_CKPDN_CON0,
3155 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
3156 /* vow */
3157 SND_SOC_DAPM_SUPPLY_S("VOW_AUD_LPW", SUPPLY_SEQ_VOW_AUD_LPW,
3158 SND_SOC_NOPM, 0, 0,
3159 mt_vow_aud_lpw_event,
3160 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3161 SND_SOC_DAPM_SUPPLY_S("AUD_VOW", SUPPLY_SEQ_AUD_VOW,
3162 MT6359_AUDENC_ANA_CON23,
3163 RG_AUDIO_VOW_EN_SFT, 0, NULL, 0),
3164 SND_SOC_DAPM_SUPPLY_S("VOW_CLK", SUPPLY_SEQ_VOW_CLK,
3165 MT6359_DCXO_CW11,
3166 RG_XO_VOW_EN_SFT, 0, NULL, 0),
3167 SND_SOC_DAPM_SUPPLY_S("VOW_LDO", SUPPLY_SEQ_VOW_LDO,
3168 MT6359_AUDENC_ANA_CON23,
3169 RG_CLKSQ_EN_VOW_SFT, 0, NULL, 0),
3170 SND_SOC_DAPM_SUPPLY_S("VOW_DIG_CFG", SUPPLY_SEQ_VOW_DIG_CFG,
3171 MT6359_AUD_TOP_CKPDN_CON0,
3172 RG_VOW13M_CK_PDN_SFT, 1,
3173 mt_vow_digital_cfg_event,
3174 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
3175 SND_SOC_DAPM_SUPPLY_S("VOW_PERIODIC_CFG", SUPPLY_SEQ_VOW_PERIODIC_CFG,
3176 SND_SOC_NOPM, 0, 0,
3177 mt_vow_periodic_cfg_event,
3178 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3179 /* Digital Clock */
3180 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
3181 MT6359_AUDIO_TOP_CON0,
3182 PDN_AFE_CTL_SFT, 1,
3183 mt_delay_250_event,
3184 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
3185 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
3186 MT6359_AUDIO_TOP_CON0,
3187 PDN_DAC_CTL_SFT, 1, NULL, 0),
3188 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
3189 MT6359_AUDIO_TOP_CON0,
3190 PDN_ADC_CTL_SFT, 1, NULL, 0),
3191 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADDA6_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
3192 MT6359_AUDIO_TOP_CON0,
3193 PDN_ADDA6_ADC_CTL_SFT, 1, NULL, 0),
3194 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
3195 MT6359_AUDIO_TOP_CON0,
3196 PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
3197 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
3198 MT6359_AUDIO_TOP_CON0,
3199 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
3200 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
3201 MT6359_AUDIO_TOP_CON0,
3202 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
3203 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
3204 MT6359_AUDIO_TOP_CON0,
3205 PDN_RESERVED_SFT, 1, NULL, 0),
3206
3207 SND_SOC_DAPM_SUPPLY_S("SDM", SUPPLY_SEQ_DL_SDM,
3208 SND_SOC_NOPM, 0, 0,
3209 mt_sdm_event,
3210 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3211 SND_SOC_DAPM_SUPPLY_S("SDM_3RD", SUPPLY_SEQ_DL_SDM,
3212 SND_SOC_NOPM, 0, 0,
3213 mt_sdm_3rd_event,
3214 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3215
3216 /* ch123 share SDM FIFO CLK */
3217 SND_SOC_DAPM_SUPPLY_S("SDM_FIFO_CLK", SUPPLY_SEQ_DL_SDM_FIFO_CLK,
3218 MT6359_AFUNC_AUD_CON2,
3219 CCI_AFIFO_CLK_PWDB_SFT, 0,
3220 NULL, 0),
3221
3222 SND_SOC_DAPM_SUPPLY_S("NCP", SUPPLY_SEQ_DL_NCP,
3223 MT6359_AFE_NCP_CFG0,
3224 RG_NCP_ON_SFT, 0,
3225 mt_ncp_event,
3226 SND_SOC_DAPM_PRE_PMU),
3227
3228 SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
3229 0, 0, NULL, 0),
3230 SND_SOC_DAPM_SUPPLY("DL Digital Clock CH_1_2", SND_SOC_NOPM,
3231 0, 0, NULL, 0),
3232 SND_SOC_DAPM_SUPPLY("DL Digital Clock CH_3", SND_SOC_NOPM,
3233 0, 0, NULL, 0),
3234
3235 /* AFE ON */
3236 SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
3237 MT6359_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
3238 NULL, 0),
3239
3240 /* GPIO */
3241 SND_SOC_DAPM_SUPPLY_S("DL_GPIO", SUPPLY_SEQ_DL_GPIO,
3242 SND_SOC_NOPM, 0, 0,
3243 mt_dl_gpio_event,
3244 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3245 SND_SOC_DAPM_SUPPLY_S("UL_GPIO", SUPPLY_SEQ_UL_GPIO,
3246 SND_SOC_NOPM, 0, 0,
3247 mt_ul_gpio_event,
3248 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3249
3250 /* AIF Rx*/
3251 SND_SOC_DAPM_AIF_IN("AIF_RX", "AIF1 Playback", 0,
3252 SND_SOC_NOPM, 0, 0),
3253
3254 SND_SOC_DAPM_AIF_IN("AIF2_RX", "AIF2 Playback", 0,
3255 SND_SOC_NOPM, 0, 0),
3256
3257 SND_SOC_DAPM_SUPPLY_S("AFE_DL_SRC", SUPPLY_SEQ_DL_SRC,
3258 MT6359_AFE_DL_SRC2_CON0_L,
3259 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
3260 NULL, 0),
3261
3262 /* DL Supply */
3263 SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
3264 0, 0, NULL, 0),
3265
3266 SND_SOC_DAPM_SUPPLY_S("ESD_RESIST", SUPPLY_SEQ_DL_ESD_RESIST,
3267 SND_SOC_NOPM,
3268 0, 0,
3269 mt_esd_resist_event,
3270 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3271 SND_SOC_DAPM_SUPPLY_S("LDO", SUPPLY_SEQ_DL_LDO,
3272 MT6359_AUDDEC_ANA_CON14,
3273 RG_LCLDO_DEC_EN_VA32_SFT, 0,
3274 NULL, 0),
3275 SND_SOC_DAPM_SUPPLY_S("LDO_REMOTE", SUPPLY_SEQ_DL_LDO_REMOTE_SENSE,
3276 MT6359_AUDDEC_ANA_CON14,
3277 RG_LCLDO_DEC_REMOTE_SENSE_VA18_SFT, 0,
3278 NULL, 0),
3279 SND_SOC_DAPM_SUPPLY_S("NV_REGULATOR", SUPPLY_SEQ_DL_NV,
3280 MT6359_AUDDEC_ANA_CON14,
3281 RG_NVREG_EN_VAUDP32_SFT, 0,
3282 mt_delay_100_event, SND_SOC_DAPM_POST_PMU),
3283 SND_SOC_DAPM_SUPPLY_S("IBIST", SUPPLY_SEQ_DL_IBIST,
3284 MT6359_AUDDEC_ANA_CON12,
3285 RG_AUDIBIASPWRDN_VAUDP32_SFT, 1,
3286 NULL, 0),
3287
3288 /* DAC */
3289 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
3290
3291 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
3292
3293 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
3294
3295 SND_SOC_DAPM_DAC("DAC_3RD", NULL, SND_SOC_NOPM, 0, 0),
3296
3297 /* Headphone */
3298 SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0,
3299 &hpl_in_mux_control,
3300 mt_hp_event,
3301 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
3302
3303 SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0,
3304 &hpr_in_mux_control,
3305 mt_hp_event,
3306 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
3307
3308 SND_SOC_DAPM_SUPPLY("HP_Supply", SND_SOC_NOPM,
3309 0, 0, NULL, 0),
3310 SND_SOC_DAPM_SUPPLY_S("HP_PULL_DOWN", SUPPLY_SEQ_HP_PULL_DOWN,
3311 SND_SOC_NOPM,
3312 0, 0,
3313 mt_hp_pull_down_event,
3314 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3315 SND_SOC_DAPM_SUPPLY_S("HP_MUTE", SUPPLY_SEQ_HP_MUTE,
3316 SND_SOC_NOPM,
3317 0, 0,
3318 mt_hp_mute_event,
3319 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3320 SND_SOC_DAPM_SUPPLY_S("HP_DAMP", SUPPLY_SEQ_HP_DAMPING_OFF_RESET_CMFB,
3321 SND_SOC_NOPM,
3322 0, 0,
3323 mt_hp_damp_event,
3324 SND_SOC_DAPM_POST_PMD),
3325
3326 /* Receiver */
3327 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
3328 &rcv_in_mux_control,
3329 mt_rcv_event,
3330 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
3331
3332 /* LOL */
3333 SND_SOC_DAPM_MUX_E("LOL Mux", SND_SOC_NOPM, 0, 0,
3334 &lo_in_mux_control,
3335 mt_lo_event,
3336 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
3337
3338 /* Outputs */
3339 SND_SOC_DAPM_OUTPUT("Receiver"),
3340 SND_SOC_DAPM_OUTPUT("Headphone L"),
3341 SND_SOC_DAPM_OUTPUT("Headphone R"),
3342 SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
3343 SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
3344 SND_SOC_DAPM_OUTPUT("LINEOUT L"),
3345
3346 /* SGEN */
3347 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6359_AFE_SGEN_CFG0,
3348 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
3349 SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6359_AFE_SGEN_CFG0,
3350 SGEN_MUTE_SW_CTL_SFT, 1,
3351 mt_sgen_event,
3352 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3353 SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6359_AFE_DL_SRC2_CON0_L,
3354 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
3355 /* tricky, same reg/bit as "AIF_RX", reconsider */
3356
3357 SND_SOC_DAPM_INPUT("SGEN DL"),
3358
3359 /* Uplinks */
3360 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
3361 SND_SOC_NOPM, 0, 0),
3362 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
3363 SND_SOC_NOPM, 0, 0),
3364
3365 SND_SOC_DAPM_SUPPLY_S("ADC_CLKGEN", SUPPLY_SEQ_ADC_CLKGEN,
3366 SND_SOC_NOPM, 0, 0,
3367 mt_adc_clk_gen_event,
3368 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
3369
3370 SND_SOC_DAPM_SUPPLY_S("DCC_CLK", SUPPLY_SEQ_DCC_CLK,
3371 SND_SOC_NOPM, 0, 0,
3372 mt_dcc_clk_event,
3373 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3374
3375 /* Uplinks MUX */
3376 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
3377 &aif_out_mux_control),
3378
3379 SND_SOC_DAPM_MUX("AIF2 Out Mux", SND_SOC_NOPM, 0, 0,
3380 &aif2_out_mux_control),
3381
3382 SND_SOC_DAPM_SUPPLY("AIFTX_Supply", SND_SOC_NOPM, 0, 0, NULL, 0),
3383
3384 SND_SOC_DAPM_SUPPLY_S("MTKAIF_TX", SUPPLY_SEQ_UL_MTKAIF,
3385 SND_SOC_NOPM, 0, 0,
3386 mt_mtkaif_tx_event,
3387 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3388
3389 SND_SOC_DAPM_SUPPLY_S("UL_SRC", SUPPLY_SEQ_UL_SRC,
3390 MT6359_AFE_UL_SRC_CON0_L,
3391 UL_SRC_ON_TMP_CTL_SFT, 0,
3392 NULL, 0),
3393
3394 SND_SOC_DAPM_SUPPLY_S("UL_SRC_DMIC", SUPPLY_SEQ_UL_SRC_DMIC,
3395 SND_SOC_NOPM, 0, 0,
3396 mt_ul_src_dmic_event,
3397 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3398
3399 SND_SOC_DAPM_SUPPLY_S("UL_SRC_34", SUPPLY_SEQ_UL_SRC,
3400 MT6359_AFE_ADDA6_UL_SRC_CON0_L,
3401 ADDA6_UL_SRC_ON_TMP_CTL_SFT, 0,
3402 NULL, 0),
3403
3404 SND_SOC_DAPM_SUPPLY_S("UL_SRC_34_DMIC", SUPPLY_SEQ_UL_SRC_DMIC,
3405 SND_SOC_NOPM, 0, 0,
3406 mt_ul_src_34_dmic_event,
3407 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3408
3409 SND_SOC_DAPM_MUX("MISO0_MUX", SND_SOC_NOPM, 0, 0, &miso0_mux_control),
3410 SND_SOC_DAPM_MUX("MISO1_MUX", SND_SOC_NOPM, 0, 0, &miso1_mux_control),
3411 SND_SOC_DAPM_MUX("MISO2_MUX", SND_SOC_NOPM, 0, 0, &miso2_mux_control),
3412
3413 SND_SOC_DAPM_MUX("UL_SRC_MUX", SND_SOC_NOPM, 0, 0,
3414 &ul_src_mux_control),
3415 SND_SOC_DAPM_MUX("UL2_SRC_MUX", SND_SOC_NOPM, 0, 0,
3416 &ul2_src_mux_control),
3417 SND_SOC_DAPM_MUX("VOW_UL_SRC_MUX", SND_SOC_NOPM, 0, 0,
3418 &vow_ul_src_mux_control),
3419
3420 SND_SOC_DAPM_MUX("DMIC0_MUX", SND_SOC_NOPM, 0, 0, &dmic0_mux_control),
3421 SND_SOC_DAPM_MUX("DMIC1_MUX", SND_SOC_NOPM, 0, 0, &dmic1_mux_control),
3422 SND_SOC_DAPM_MUX("DMIC2_MUX", SND_SOC_NOPM, 0, 0, &dmic2_mux_control),
3423
3424 SND_SOC_DAPM_MUX("VOW_AMIC0_MUX", SND_SOC_NOPM, 0, 0,
3425 &vow_amic0_mux_control),
3426 SND_SOC_DAPM_MUX("VOW_AMIC1_MUX", SND_SOC_NOPM, 0, 0,
3427 &vow_amic1_mux_control),
3428
3429 SND_SOC_DAPM_MUX_E("ADC_L_Mux", SND_SOC_NOPM, 0, 0,
3430 &adc_left_mux_control, NULL, 0),
3431 SND_SOC_DAPM_MUX_E("ADC_R_Mux", SND_SOC_NOPM, 0, 0,
3432 &adc_right_mux_control, NULL, 0),
3433 SND_SOC_DAPM_MUX_E("ADC_3_Mux", SND_SOC_NOPM, 0, 0,
3434 &adc_3_mux_control, NULL, 0),
3435
3436 SND_SOC_DAPM_ADC("ADC_L", NULL, SND_SOC_NOPM, 0, 0),
3437 SND_SOC_DAPM_ADC("ADC_R", NULL, SND_SOC_NOPM, 0, 0),
3438 SND_SOC_DAPM_ADC("ADC_3", NULL, SND_SOC_NOPM, 0, 0),
3439
3440 SND_SOC_DAPM_SUPPLY_S("ADC_L_EN", SUPPLY_SEQ_UL_ADC,
3441 MT6359_AUDENC_ANA_CON0,
3442 RG_AUDADCLPWRUP_SFT, 0,
3443 mt_adc_l_event,
3444 SND_SOC_DAPM_POST_PMU),
3445 SND_SOC_DAPM_SUPPLY_S("ADC_R_EN", SUPPLY_SEQ_UL_ADC,
3446 MT6359_AUDENC_ANA_CON1,
3447 RG_AUDADCRPWRUP_SFT, 0,
3448 mt_adc_r_event,
3449 SND_SOC_DAPM_POST_PMU),
3450 SND_SOC_DAPM_SUPPLY_S("ADC_3_EN", SUPPLY_SEQ_UL_ADC,
3451 MT6359_AUDENC_ANA_CON2,
3452 RG_AUDADC3PWRUP_SFT, 0,
3453 mt_adc_3_event,
3454 SND_SOC_DAPM_POST_PMU),
3455
3456 SND_SOC_DAPM_MUX_E("PGA_L_Mux", SND_SOC_NOPM, 0, 0,
3457 &pga_left_mux_control,
3458 mt_pga_l_mux_event,
3459 SND_SOC_DAPM_WILL_PMU),
3460 SND_SOC_DAPM_MUX_E("PGA_R_Mux", SND_SOC_NOPM, 0, 0,
3461 &pga_right_mux_control,
3462 mt_pga_r_mux_event,
3463 SND_SOC_DAPM_WILL_PMU),
3464 SND_SOC_DAPM_MUX_E("PGA_3_Mux", SND_SOC_NOPM, 0, 0,
3465 &pga_3_mux_control,
3466 mt_pga_3_mux_event,
3467 SND_SOC_DAPM_WILL_PMU),
3468
3469 SND_SOC_DAPM_PGA("PGA_L", SND_SOC_NOPM, 0, 0, NULL, 0),
3470 SND_SOC_DAPM_PGA("PGA_R", SND_SOC_NOPM, 0, 0, NULL, 0),
3471 SND_SOC_DAPM_PGA("PGA_3", SND_SOC_NOPM, 0, 0, NULL, 0),
3472
3473 SND_SOC_DAPM_SUPPLY_S("PGA_L_EN", SUPPLY_SEQ_UL_PGA,
3474 MT6359_AUDENC_ANA_CON0,
3475 RG_AUDPREAMPLON_SFT, 0,
3476 mt_pga_l_event,
3477 SND_SOC_DAPM_PRE_PMU |
3478 SND_SOC_DAPM_POST_PMU |
3479 SND_SOC_DAPM_POST_PMD),
3480 SND_SOC_DAPM_SUPPLY_S("PGA_R_EN", SUPPLY_SEQ_UL_PGA,
3481 MT6359_AUDENC_ANA_CON1,
3482 RG_AUDPREAMPRON_SFT, 0,
3483 mt_pga_r_event,
3484 SND_SOC_DAPM_PRE_PMU |
3485 SND_SOC_DAPM_POST_PMU |
3486 SND_SOC_DAPM_POST_PMD),
3487 SND_SOC_DAPM_SUPPLY_S("PGA_3_EN", SUPPLY_SEQ_UL_PGA,
3488 MT6359_AUDENC_ANA_CON2,
3489 RG_AUDPREAMP3ON_SFT, 0,
3490 mt_pga_3_event,
3491 SND_SOC_DAPM_PRE_PMU |
3492 SND_SOC_DAPM_POST_PMU |
3493 SND_SOC_DAPM_POST_PMD),
3494
3495 /* UL input */
3496 SND_SOC_DAPM_INPUT("AIN0"),
3497 SND_SOC_DAPM_INPUT("AIN1"),
3498 SND_SOC_DAPM_INPUT("AIN2"),
3499 SND_SOC_DAPM_INPUT("AIN3"),
3500
3501 SND_SOC_DAPM_INPUT("AIN0_DMIC"),
3502 SND_SOC_DAPM_INPUT("AIN2_DMIC"),
3503 SND_SOC_DAPM_INPUT("AIN3_DMIC"),
3504
3505 /* mic bias */
3506 SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_0", SUPPLY_SEQ_MIC_BIAS,
3507 MT6359_AUDENC_ANA_CON15,
3508 RG_AUDPWDBMICBIAS0_SFT, 0,
3509 mt_mic_bias_0_event,
3510 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3511 SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_1", SUPPLY_SEQ_MIC_BIAS,
3512 MT6359_AUDENC_ANA_CON16,
3513 RG_AUDPWDBMICBIAS1_SFT, 0,
3514 mt_mic_bias_1_event,
3515 SND_SOC_DAPM_PRE_PMU),
3516 SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_2", SUPPLY_SEQ_MIC_BIAS,
3517 MT6359_AUDENC_ANA_CON17,
3518 RG_AUDPWDBMICBIAS2_SFT, 0,
3519 mt_mic_bias_2_event,
3520 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3521
3522 /* dmic */
3523 SND_SOC_DAPM_SUPPLY_S("DMIC_0", SUPPLY_SEQ_DMIC,
3524 MT6359_AUDENC_ANA_CON13,
3525 RG_AUDDIGMICEN_SFT, 0,
3526 NULL, 0),
3527 SND_SOC_DAPM_SUPPLY_S("DMIC_1", SUPPLY_SEQ_DMIC,
3528 MT6359_AUDENC_ANA_CON14,
3529 RG_AUDDIGMIC1EN_SFT, 0,
3530 NULL, 0),
3531
3532 /* VOW */
3533 SND_SOC_DAPM_AIF_OUT_E("VOW TX", "VOW Capture", 0,
3534 SND_SOC_NOPM, 0, 0,
3535 mt_vow_out_event,
3536 SND_SOC_DAPM_WILL_PMU |
3537 SND_SOC_DAPM_PRE_PMU |
3538 SND_SOC_DAPM_POST_PMD),
3539};
3540
3541static int mt_vow_amic_connect(struct snd_soc_dapm_widget *source,
3542 struct snd_soc_dapm_widget *sink)
3543{
3544
3545 struct snd_soc_dapm_widget *w = sink;
3546 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
3547 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
3548
3549 if (IS_VOW_AMIC_BASE(priv->mux_select[MUX_MIC_TYPE_0]) ||
3550 IS_VOW_AMIC_BASE(priv->mux_select[MUX_MIC_TYPE_1]) ||
3551 IS_VOW_AMIC_BASE(priv->mux_select[MUX_MIC_TYPE_2]))
3552 return 1;
3553 else
3554 return 0;
3555}
3556
3557static int mt_vow_amic_dcc_connect(struct snd_soc_dapm_widget *source,
3558 struct snd_soc_dapm_widget *sink)
3559{
3560
3561 struct snd_soc_dapm_widget *w = sink;
3562 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
3563 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
3564
3565 if (IS_VOW_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_0]) ||
3566 IS_VOW_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_1]) ||
3567 IS_VOW_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_2]))
3568 return 1;
3569 else
3570 return 0;
3571}
3572
3573static int mt_dcc_clk_connect(struct snd_soc_dapm_widget *source,
3574 struct snd_soc_dapm_widget *sink)
3575{
3576 struct snd_soc_dapm_widget *w = sink;
3577 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
3578 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
3579
3580 if (IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_0]) ||
3581 IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_1]) ||
3582 IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_2]))
3583 return 1;
3584 else
3585 return 0;
3586}
3587
3588static const struct snd_soc_dapm_route mt6359_dapm_routes[] = {
3589 /* Capture */
3590 {"AIFTX_Supply", NULL, "CLK_BUF"},
3591 {"AIFTX_Supply", NULL, "LDO_VAUD18"},
3592 {"AIFTX_Supply", NULL, "AUDGLB"},
3593 {"AIFTX_Supply", NULL, "CLKSQ Audio"},
3594 {"AIFTX_Supply", NULL, "AUD_CK"},
3595 {"AIFTX_Supply", NULL, "AUDIF_CK"},
3596 {"AIFTX_Supply", NULL, "AUDIO_TOP_AFE_CTL"},
3597 {"AIFTX_Supply", NULL, "AUDIO_TOP_PWR_CLK"},
3598 {"AIFTX_Supply", NULL, "AUDIO_TOP_PDN_RESERVED"},
3599 {"AIFTX_Supply", NULL, "AUDIO_TOP_I2S_DL"},
3600 /*
3601 * *_ADC_CTL should enable only if UL_SRC in use,
3602 * but dm ck may be needed even UL_SRC_x not in use
3603 */
3604 {"AIFTX_Supply", NULL, "AUDIO_TOP_ADC_CTL"},
3605 {"AIFTX_Supply", NULL, "AUDIO_TOP_ADDA6_ADC_CTL"},
3606 {"AIFTX_Supply", NULL, "AFE_ON"},
3607
3608 /* ul ch 12 */
3609 {"AIF1TX", NULL, "AIF Out Mux"},
3610 {"AIF1TX", NULL, "AIFTX_Supply"},
3611 {"AIF1TX", NULL, "UL_GPIO"},
3612 {"AIF1TX", NULL, "MTKAIF_TX"},
3613
3614 {"AIF2TX", NULL, "AIF2 Out Mux"},
3615 {"AIF2TX", NULL, "AIFTX_Supply"},
3616 {"AIF2TX", NULL, "UL_GPIO"},
3617 {"AIF2TX", NULL, "MTKAIF_TX"},
3618
3619 {"AIF Out Mux", "Normal Path", "MISO0_MUX"},
3620 {"AIF Out Mux", "Normal Path", "MISO1_MUX"},
3621 {"AIF2 Out Mux", "Normal Path", "MISO2_MUX"},
3622
3623 {"MISO0_MUX", "UL1_CH1", "UL_SRC_MUX"},
3624 {"MISO0_MUX", "UL1_CH2", "UL_SRC_MUX"},
3625 {"MISO0_MUX", "UL2_CH1", "UL2_SRC_MUX"},
3626 {"MISO0_MUX", "UL2_CH2", "UL2_SRC_MUX"},
3627
3628 {"MISO1_MUX", "UL1_CH1", "UL_SRC_MUX"},
3629 {"MISO1_MUX", "UL1_CH2", "UL_SRC_MUX"},
3630 {"MISO1_MUX", "UL2_CH1", "UL2_SRC_MUX"},
3631 {"MISO1_MUX", "UL2_CH2", "UL2_SRC_MUX"},
3632
3633 {"MISO2_MUX", "UL1_CH1", "UL_SRC_MUX"},
3634 {"MISO2_MUX", "UL1_CH2", "UL_SRC_MUX"},
3635 {"MISO2_MUX", "UL2_CH1", "UL2_SRC_MUX"},
3636 {"MISO2_MUX", "UL2_CH2", "UL2_SRC_MUX"},
3637
3638 {"UL_SRC_MUX", "AMIC", "ADC_L"},
3639 {"UL_SRC_MUX", "AMIC", "ADC_R"},
3640 {"UL_SRC_MUX", "DMIC", "DMIC0_MUX"},
3641 {"UL_SRC_MUX", "DMIC", "DMIC1_MUX"},
3642 {"UL_SRC_MUX", NULL, "UL_SRC"},
3643
3644 {"UL2_SRC_MUX", "AMIC", "ADC_3"},
3645 {"UL2_SRC_MUX", "DMIC", "DMIC2_MUX"},
3646 {"UL2_SRC_MUX", NULL, "UL_SRC_34"},
3647
3648 {"DMIC0_MUX", "DMIC_DATA0", "AIN0_DMIC"},
3649 {"DMIC0_MUX", "DMIC_DATA1_L", "AIN2_DMIC"},
3650 {"DMIC0_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"},
3651 {"DMIC0_MUX", "DMIC_DATA1_R", "AIN3_DMIC"},
3652 {"DMIC1_MUX", "DMIC_DATA0", "AIN0_DMIC"},
3653 {"DMIC1_MUX", "DMIC_DATA1_L", "AIN2_DMIC"},
3654 {"DMIC1_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"},
3655 {"DMIC1_MUX", "DMIC_DATA1_R", "AIN3_DMIC"},
3656 {"DMIC2_MUX", "DMIC_DATA0", "AIN0_DMIC"},
3657 {"DMIC2_MUX", "DMIC_DATA1_L", "AIN2_DMIC"},
3658 {"DMIC2_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"},
3659 {"DMIC2_MUX", "DMIC_DATA1_R", "AIN3_DMIC"},
3660
3661 {"DMIC0_MUX", NULL, "UL_SRC_DMIC"},
3662 {"DMIC1_MUX", NULL, "UL_SRC_DMIC"},
3663 {"DMIC2_MUX", NULL, "UL_SRC_34_DMIC"},
3664
3665 {"AIN0_DMIC", NULL, "DMIC_0"},
3666 {"AIN2_DMIC", NULL, "DMIC_1"},
3667 {"AIN3_DMIC", NULL, "DMIC_1"},
3668 {"AIN2_DMIC", NULL, "MIC_BIAS_2"},
3669 {"AIN3_DMIC", NULL, "MIC_BIAS_2"},
3670
3671 /* adc */
3672 {"ADC_L", NULL, "ADC_L_Mux"},
3673 {"ADC_L", NULL, "ADC_CLKGEN"},
3674 {"ADC_L", NULL, "ADC_L_EN"},
3675 {"ADC_R", NULL, "ADC_R_Mux"},
3676 {"ADC_R", NULL, "ADC_CLKGEN"},
3677 {"ADC_R", NULL, "ADC_R_EN"},
3678 /*
3679 * amic fifo ch1/2 clk from ADC_L,
3680 * enable ADC_L even use ADC_R only
3681 */
3682 {"ADC_R", NULL, "ADC_L_EN"},
3683 {"ADC_3", NULL, "ADC_3_Mux"},
3684 {"ADC_3", NULL, "ADC_CLKGEN"},
3685 {"ADC_3", NULL, "ADC_3_EN"},
3686
3687 {"ADC_L_Mux", "Left Preamplifier", "PGA_L"},
3688 {"ADC_R_Mux", "Right Preamplifier", "PGA_R"},
3689 {"ADC_3_Mux", "Preamplifier", "PGA_3"},
3690
3691 {"PGA_L", NULL, "PGA_L_Mux"},
3692 {"PGA_L", NULL, "PGA_L_EN"},
3693 {"PGA_R", NULL, "PGA_R_Mux"},
3694 {"PGA_R", NULL, "PGA_R_EN"},
3695 {"PGA_3", NULL, "PGA_3_Mux"},
3696 {"PGA_3", NULL, "PGA_3_EN"},
3697
3698 {"PGA_L", NULL, "DCC_CLK", mt_dcc_clk_connect},
3699 {"PGA_R", NULL, "DCC_CLK", mt_dcc_clk_connect},
3700 {"PGA_3", NULL, "DCC_CLK", mt_dcc_clk_connect},
3701
3702 {"PGA_L_Mux", "AIN0", "AIN0"},
3703 {"PGA_L_Mux", "AIN1", "AIN1"},
3704
3705 {"PGA_R_Mux", "AIN0", "AIN0"},
3706 {"PGA_R_Mux", "AIN2", "AIN2"},
3707 {"PGA_R_Mux", "AIN3", "AIN3"},
3708
3709 {"PGA_3_Mux", "AIN2", "AIN2"},
3710 {"PGA_3_Mux", "AIN3", "AIN3"},
3711
3712 {"AIN0", NULL, "MIC_BIAS_0"},
3713 {"AIN1", NULL, "MIC_BIAS_1"},
3714 {"AIN2", NULL, "MIC_BIAS_0"},
3715 {"AIN2", NULL, "MIC_BIAS_2"},
3716 {"AIN3", NULL, "MIC_BIAS_2"},
3717
3718 /* DL Supply */
3719 {"DL Power Supply", NULL, "CLK_BUF"},
3720 {"DL Power Supply", NULL, "LDO_VAUD18"},
3721 {"DL Power Supply", NULL, "AUDGLB"},
3722 {"DL Power Supply", NULL, "CLKSQ Audio"},
3723
3724 {"DL Power Supply", NULL, "AUDNCP_CK"},
3725 {"DL Power Supply", NULL, "ZCD13M_CK"},
3726 {"DL Power Supply", NULL, "AUD_CK"},
3727 {"DL Power Supply", NULL, "AUDIF_CK"},
3728
3729 {"DL Power Supply", NULL, "ESD_RESIST"},
3730 {"DL Power Supply", NULL, "LDO"},
3731 {"DL Power Supply", NULL, "LDO_REMOTE"},
3732 {"DL Power Supply", NULL, "NV_REGULATOR"},
3733 {"DL Power Supply", NULL, "IBIST"},
3734
3735 /* DL Digital Supply */
3736 {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
3737 {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
3738 {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
3739 {"DL Digital Clock", NULL, "AUDIO_TOP_PDN_RESERVED"},
3740
3741 {"DL Digital Clock", NULL, "SDM_FIFO_CLK"},
3742 {"DL Digital Clock", NULL, "NCP"},
3743
3744 {"DL Digital Clock", NULL, "AFE_ON"},
3745 {"DL Digital Clock", NULL, "AFE_DL_SRC"},
3746
3747 {"DL Digital Clock CH_1_2", NULL, "DL Digital Clock"},
3748 {"DL Digital Clock CH_1_2", NULL, "SDM"},
3749
3750 {"DL Digital Clock CH_3", NULL, "DL Digital Clock"},
3751 {"DL Digital Clock CH_3", NULL, "SDM_3RD"},
3752
3753 {"AIF_RX", NULL, "DL Digital Clock CH_1_2"},
3754 {"AIF_RX", NULL, "DL_GPIO"},
3755
3756 {"AIF2_RX", NULL, "DL Digital Clock CH_3"},
3757 {"AIF2_RX", NULL, "DL_GPIO"},
3758
3759 /* DL Path */
3760 {"DAC In Mux", "Normal Path", "AIF_RX"},
3761 {"DAC In Mux", "Sgen", "SGEN DL"},
3762 {"SGEN DL", NULL, "SGEN DL SRC"},
3763 {"SGEN DL", NULL, "SGEN MUTE"},
3764 {"SGEN DL", NULL, "SGEN DL Enable"},
3765 {"SGEN DL", NULL, "DL Digital Clock CH_1_2"},
3766 {"SGEN DL", NULL, "DL Digital Clock CH_3"},
3767 {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
3768
3769 {"DACL", NULL, "DAC In Mux"},
3770 {"DACL", NULL, "DL Power Supply"},
3771
3772 {"DACR", NULL, "DAC In Mux"},
3773 {"DACR", NULL, "DL Power Supply"},
3774
3775 /* DAC 3RD */
3776 {"DAC In Mux", "Normal Path", "AIF2_RX"},
3777 {"DAC_3RD", NULL, "DAC In Mux"},
3778 {"DAC_3RD", NULL, "DL Power Supply"},
3779
3780 /* Lineout Path */
3781 {"LOL Mux", "Playback", "DAC_3RD"},
3782 {"LINEOUT L", NULL, "LOL Mux"},
3783
3784 /* Headphone Path */
3785 {"HP_Supply", NULL, "HP_PULL_DOWN"},
3786 {"HP_Supply", NULL, "HP_MUTE"},
3787 {"HP_Supply", NULL, "HP_DAMP"},
3788 {"HPL Mux", NULL, "HP_Supply"},
3789 {"HPR Mux", NULL, "HP_Supply"},
3790
3791 {"HPL Mux", "Audio Playback", "DACL"},
3792 {"HPR Mux", "Audio Playback", "DACR"},
3793 {"HPL Mux", "HP Impedance", "DACL"},
3794 {"HPR Mux", "HP Impedance", "DACR"},
3795 {"HPL Mux", "LoudSPK Playback", "DACL"},
3796 {"HPR Mux", "LoudSPK Playback", "DACR"},
3797
3798 {"Headphone L", NULL, "HPL Mux"},
3799 {"Headphone R", NULL, "HPR Mux"},
3800 {"Headphone L Ext Spk Amp", NULL, "HPL Mux"},
3801 {"Headphone R Ext Spk Amp", NULL, "HPR Mux"},
3802
3803 /* Receiver Path */
3804 {"RCV Mux", "Voice Playback", "DACL"},
3805 {"Receiver", NULL, "RCV Mux"},
3806
3807 /* VOW */
3808 {"VOW TX", NULL, "VOW_UL_SRC_MUX"},
3809 {"VOW TX", NULL, "CLK_BUF"},
3810 {"VOW TX", NULL, "LDO_VAUD18"},
3811 {"VOW TX", NULL, "AUDGLB"},
3812 {"VOW TX", NULL, "AUDGLB_VOW", mt_vow_amic_connect},
3813 {"VOW TX", NULL, "AUD_CK", mt_vow_amic_connect},
3814 {"VOW TX", NULL, "VOW_AUD_LPW", mt_vow_amic_connect},
3815 {"VOW TX", NULL, "VOW_CLK"},
3816 {"VOW TX", NULL, "AUD_VOW"},
3817 {"VOW TX", NULL, "VOW_LDO", mt_vow_amic_connect},
3818 {"VOW TX", NULL, "VOW_DIG_CFG"},
3819 {"VOW TX", NULL, "VOW_PERIODIC_CFG", mt_vow_amic_dcc_connect},
3820 {"VOW_UL_SRC_MUX", "AMIC", "VOW_AMIC0_MUX"},
3821 {"VOW_UL_SRC_MUX", "AMIC", "VOW_AMIC1_MUX"},
3822 {"VOW_UL_SRC_MUX", "DMIC", "DMIC0_MUX"},
3823 {"VOW_UL_SRC_MUX", "DMIC", "DMIC1_MUX"},
3824 {"VOW_AMIC0_MUX", "ADC_L", "ADC_L"},
3825 {"VOW_AMIC0_MUX", "ADC_R", "ADC_R"},
3826 {"VOW_AMIC0_MUX", "ADC_T", "ADC_3"},
3827 {"VOW_AMIC1_MUX", "ADC_L", "ADC_L"},
3828 {"VOW_AMIC1_MUX", "ADC_R", "ADC_R"},
3829 {"VOW_AMIC1_MUX", "ADC_T", "ADC_3"},
3830};
3831
3832static int mt6359_codec_dai_hw_params(struct snd_pcm_substream *substream,
3833 struct snd_pcm_hw_params *params,
3834 struct snd_soc_dai *dai)
3835{
3836 struct snd_soc_component *cmpnt = dai->component;
3837 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
3838 unsigned int rate = params_rate(params);
3839 int id = dai->id;
3840
3841
3842 dev_info(priv->dev, "%s(), id %d, substream->stream %d, rate %d, number %d\n",
3843 __func__,
3844 id,
3845 substream->stream,
3846 rate,
3847 substream->number);
3848
3849 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3850 priv->dl_rate[id] = rate;
3851 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3852 priv->ul_rate[id] = rate;
3853
3854 return 0;
3855}
3856
3857static const struct snd_soc_dai_ops mt6359_codec_dai_ops = {
3858 .hw_params = mt6359_codec_dai_hw_params,
3859};
3860
3861static int mt6359_codec_dai_vow_hw_params(struct snd_pcm_substream *substream,
3862 struct snd_pcm_hw_params *params,
3863 struct snd_soc_dai *dai)
3864{
3865 struct snd_soc_component *cmpnt = dai->component;
3866 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
3867 unsigned int channel = params_channels(params);
3868
3869 dev_info(priv->dev, "%s(), substream->stream %d, channel %d, number %d\n",
3870 __func__,
3871 substream->stream,
3872 channel,
3873 substream->number);
3874
3875 priv->vow_channel = channel;
3876
3877 return 0;
3878}
3879
3880static const struct snd_soc_dai_ops mt6359_codec_dai_vow_ops = {
3881 .hw_params = mt6359_codec_dai_vow_hw_params,
3882};
3883
3884#define MT6359_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\
3885 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\
3886 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\
3887 SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\
3888 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\
3889 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE)
3890
3891static struct snd_soc_dai_driver mt6359_dai_driver[] = {
3892 {
3893 .id = MT6359_AIF_1,
3894 .name = "mt6359-snd-codec-aif1",
3895 .playback = {
3896 .stream_name = "AIF1 Playback",
3897 .channels_min = 1,
3898 .channels_max = 2,
3899 .rates = SNDRV_PCM_RATE_8000_48000 |
3900 SNDRV_PCM_RATE_96000 |
3901 SNDRV_PCM_RATE_192000,
3902 .formats = MT6359_FORMATS,
3903 },
3904 .capture = {
3905 .stream_name = "AIF1 Capture",
3906 .channels_min = 1,
3907 .channels_max = 2,
3908 .rates = SNDRV_PCM_RATE_8000 |
3909 SNDRV_PCM_RATE_16000 |
3910 SNDRV_PCM_RATE_32000 |
3911 SNDRV_PCM_RATE_48000 |
3912 SNDRV_PCM_RATE_96000 |
3913 SNDRV_PCM_RATE_192000,
3914 .formats = MT6359_FORMATS,
3915 },
3916 .ops = &mt6359_codec_dai_ops,
3917 },
3918 {
3919 .id = MT6359_AIF_2,
3920 .name = "mt6359-snd-codec-aif2",
3921 .playback = {
3922 .stream_name = "AIF2 Playback",
3923 .channels_min = 1,
3924 .channels_max = 2,
3925 .rates = SNDRV_PCM_RATE_8000_48000 |
3926 SNDRV_PCM_RATE_96000 |
3927 SNDRV_PCM_RATE_192000,
3928 .formats = MT6359_FORMATS,
3929 },
3930 .capture = {
3931 .stream_name = "AIF2 Capture",
3932 .channels_min = 1,
3933 .channels_max = 2,
3934 .rates = SNDRV_PCM_RATE_8000 |
3935 SNDRV_PCM_RATE_16000 |
3936 SNDRV_PCM_RATE_32000 |
3937 SNDRV_PCM_RATE_48000,
3938 .formats = MT6359_FORMATS,
3939 },
3940 .ops = &mt6359_codec_dai_ops,
3941 },
3942 {
3943 .id = MT6359_AIF_VOW,
3944 .name = "mt6359-snd-codec-vow",
3945 .capture = {
3946 .stream_name = "VOW Capture",
3947 .channels_min = 1,
3948 .channels_max = 2,
3949 .rates = SNDRV_PCM_RATE_16000,
3950 .formats = MT6359_FORMATS,
3951 },
3952 .ops = &mt6359_codec_dai_vow_ops,
3953 },
3954};
3955
3956/* vow control */
3957static void *get_vow_coeff_by_name(struct mt6359_priv *priv,
3958 const char *name)
3959{
3960 if (strcmp(name, "Audio VOWCFG0 Data") == 0)
3961 return &(priv->reg_afe_vow_vad_cfg0);
3962 else if (strcmp(name, "Audio VOWCFG1 Data") == 0)
3963 return &(priv->reg_afe_vow_vad_cfg1);
3964 else if (strcmp(name, "Audio VOWCFG2 Data") == 0)
3965 return &(priv->reg_afe_vow_vad_cfg2);
3966 else if (strcmp(name, "Audio VOWCFG3 Data") == 0)
3967 return &(priv->reg_afe_vow_vad_cfg3);
3968 else if (strcmp(name, "Audio VOWCFG4 Data") == 0)
3969 return &(priv->reg_afe_vow_vad_cfg4);
3970 else if (strcmp(name, "Audio VOWCFG5 Data") == 0)
3971 return &(priv->reg_afe_vow_vad_cfg5);
3972 else if (strcmp(name, "Audio_VOW_Periodic") == 0)
3973 return &(priv->reg_afe_vow_periodic);
3974 else if (strcmp(name, "Audio_VOW_Periodic_Param") == 0)
3975 return (void *)&(priv->vow_periodic_param);
3976 else
3977 return NULL;
3978}
3979
3980static int audio_vow_cfg_get(struct snd_kcontrol *kcontrol,
3981 struct snd_ctl_elem_value *ucontrol)
3982{
3983 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3984 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
3985 int *vow_cfg;
3986
3987 vow_cfg = (int *)get_vow_coeff_by_name(priv, kcontrol->id.name);
3988 if (!vow_cfg) {
3989 dev_err(priv->dev, "%s(), vow_cfg == NULL\n", __func__);
3990 return -EINVAL;
3991 }
3992 dev_info(priv->dev, "%s(), %s = 0x%x\n",
3993 __func__, kcontrol->id.name, *vow_cfg);
3994
3995 ucontrol->value.integer.value[0] = *vow_cfg;
3996 return 0;
3997}
3998
3999static int audio_vow_cfg_set(struct snd_kcontrol *kcontrol,
4000 struct snd_ctl_elem_value *ucontrol)
4001{
4002 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
4003 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
4004 int index = ucontrol->value.integer.value[0];
4005 int *vow_cfg;
4006
4007 vow_cfg = (int *)get_vow_coeff_by_name(priv, kcontrol->id.name);
4008 if (!vow_cfg) {
4009 dev_err(priv->dev, "%s(), vow_cfg == NULL\n", __func__);
4010 return -EINVAL;
4011 }
4012 dev_info(priv->dev, "%s(), %s = 0x%x\n",
4013 __func__, kcontrol->id.name, index);
4014
4015 *vow_cfg = index;
4016 return 0;
4017}
4018
4019static int audio_vow_periodic_parm_get(struct snd_kcontrol *kcontrol,
4020 unsigned int __user *data,
4021 unsigned int size)
4022{
4023 return 0;
4024}
4025
4026static int audio_vow_periodic_parm_set(struct snd_kcontrol *kcontrol,
4027 const unsigned int __user *data,
4028 unsigned int size)
4029{
4030 int ret = 0;
4031 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
4032 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
4033 struct mt6359_vow_periodic_on_off_data *vow_param_cfg;
4034
4035 dev_info(priv->dev, "%s(), size = %d\n", __func__, size);
4036 if (size > sizeof(struct mt6359_vow_periodic_on_off_data))
4037 return -EINVAL;
4038 vow_param_cfg = (struct mt6359_vow_periodic_on_off_data *)
4039 get_vow_coeff_by_name(priv, kcontrol->id.name);
4040 if (copy_from_user(vow_param_cfg, data,
4041 sizeof(struct mt6359_vow_periodic_on_off_data))) {
4042 dev_info(priv->dev, "%s(),Fail copy to user Ptr:%p,r_sz:%zu\n",
4043 __func__,
4044 data,
4045 sizeof(struct mt6359_vow_periodic_on_off_data));
4046 ret = -EFAULT;
4047 }
4048 return ret;
4049}
4050
4051/* misc control */
4052static const char *const off_on_function[] = {"Off", "On"};
4053
4054static int hp_plugged_in_get(struct snd_kcontrol *kcontrol,
4055 struct snd_ctl_elem_value *ucontrol)
4056{
4057 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
4058 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
4059
4060 ucontrol->value.integer.value[0] = priv->hp_plugged;
4061 return 0;
4062}
4063
4064static int hp_plugged_in_set(struct snd_kcontrol *kcontrol,
4065 struct snd_ctl_elem_value *ucontrol)
4066{
4067 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
4068 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
4069
4070 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(off_on_function)) {
4071 dev_warn(priv->dev, "%s(), return -EINVAL\n", __func__);
4072 return -EINVAL;
4073 }
4074
4075 priv->hp_plugged = ucontrol->value.integer.value[0];
4076
4077 return 0;
4078}
4079
4080static const struct soc_enum misc_control_enum[] = {
4081 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(off_on_function), off_on_function),
4082};
4083
4084static int mt6359_rcv_dcc_set(struct snd_kcontrol *kcontrol,
4085 struct snd_ctl_elem_value *ucontrol)
4086{
4087 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
4088 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
4089
4090 /* receiver downlink */
4091 playback_gpio_set(priv);
4092 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
4093 RG_AUDGLB_PWRDN_VA32_MASK_SFT, 0x0);
4094 regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
4095 0x1 << RG_XO_AUDIO_EN_M_SFT,
4096 0x1 << RG_XO_AUDIO_EN_M_SFT);
4097 /* audio clk source from internal dcxo */
4098 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
4099 RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
4100 0x0);
4101
4102 /* Enable/disable CLKSQ 26MHz */
4103 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
4104 RG_CLKSQ_EN_MASK_SFT,
4105 1 << RG_CLKSQ_EN_SFT);
4106
4107 regmap_update_bits(priv->regmap, MT6359_AUD_TOP_CKPDN_CON0,
4108 0x66, 0x0);
4109 usleep_range(250, 270);
4110 /* Audio system digital clock power down release */
4111 regmap_update_bits(priv->regmap, MT6359_AUDIO_TOP_CON0,
4112 0x00ff, 0x0000);
4113 usleep_range(250, 270);
4114
4115 /* sdm audio fifo clock power on */
4116 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0006);
4117 /* scrambler clock on enable */
4118 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xCBA1);
4119 /* sdm power on */
4120 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0003);
4121 /* sdm fifo enable */
4122 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x000B);
4123
4124 regmap_write(priv->regmap, MT6359_AFE_NCP_CFG0, 0xc800);
4125 regmap_write(priv->regmap, MT6359_AFE_NCP_CFG0, 0xc801);
4126
4127 /* afe enable, dl_lr_swap = 0 */
4128 regmap_update_bits(priv->regmap, MT6359_AFE_UL_DL_CON0,
4129 0xc001, 0x0001);
4130
4131 /* turn on dl */
4132 regmap_write(priv->regmap, MT6359_AFE_DL_SRC2_CON0_L, 0x0001);
4133
4134 /* set DL in normal path, not from sine gen table */
4135 regmap_write(priv->regmap, MT6359_AFE_TOP_CON0, 0x0000);
4136
4137 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
4138 RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT,
4139 0x1 << RG_AUDREFN_DERES_EN_VAUDP32_SFT);
4140 usleep_range(250, 270);
4141
4142 /* Enable cap-less LDOs (1.5V) */
4143 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON14, 0x0005);
4144 /* Enable NV regulator (-1.2V) */
4145 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON14, 0x0015);
4146 usleep_range(100, 120);
4147
4148 /* Disable AUD_ZCD */
4149 zcd_disable(priv);
4150
4151 /* Disable handset short-circuit protection */
4152 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0010);
4153 /* Enable IBIST */
4154 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON12, 0x0055);
4155 /* Set HP DR bias current optimization, 010: 6uA */
4156 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON11, 0x4900);
4157 /* Set HP & ZCD bias current optimization */
4158 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
4159 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON12, 0x0055);
4160 /* Set HS STB enhance circuits */
4161 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0090);
4162
4163 /* Set HS output stage (3'b111 = 8x) */
4164 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x7000);
4165
4166 /* Enable HS driver bias circuits */
4167 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0092);
4168 /* Enable HS driver core circuits */
4169 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0093);
4170
4171 /* Set HS gain to normal gain step by step */
4172 regmap_write(priv->regmap, MT6359_ZCD_CON3, 0x0);
4173
4174 /* Enable AUD_CLK */
4175 mt6359_set_decoder_clk(priv, true);
4176 /* Enable Audio DAC */
4177 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x0009);
4178 /* Enable low-noise mode of DAC */
4179 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0001);
4180 /* Switch HS MUX to audio DAC */
4181 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x009b);
4182
4183 /* phone mic dcc */
4184
4185 /* Enable audio ADC CLKGEN */
4186 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON5, 0x0001);
4187 /* ADC CLK from CLKGEN (13MHz) */
4188 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON5, 0x0021);
4189
4190 /* DCC 50k CLK (from 26M) */
4191 regmap_write(priv->regmap, MT6359_AFE_DCCLK_CFG0, 0x2062);
4192 regmap_write(priv->regmap, MT6359_AFE_DCCLK_CFG0, 0x2060);
4193 regmap_write(priv->regmap, MT6359_AFE_DCCLK_CFG0, 0x2061);
4194 regmap_write(priv->regmap, MT6359_AFE_DCCLK_CFG1, 0x0100);
4195
4196 /* phone mic */
4197 /* Enable MICBIAS0, MISBIAS0 = 1P9V */
4198 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON15, 0x0021);
4199
4200 /* dcc precharge */
4201 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON1, 0x0004);
4202 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON0, 0x0004);
4203
4204 /* preamplifier input sel, enable pga */
4205 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON1, 0x0045);
4206 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON0, 0x0045);
4207
4208 /* pga gain 18 dB */
4209 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON1, 0x0345);
4210 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON0, 0x0345);
4211
4212 /* preamplifier dcc en */
4213 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON1, 0x0347);
4214 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON0, 0x0347);
4215
4216 /* adc in sel, enable adc */
4217 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON1, 0x5347);
4218 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON0, 0x5347);
4219
4220 usleep_range(100, 120);
4221
4222 /* preamplifier dcc precharge off */
4223 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON1, 0x5343);
4224 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON0, 0x5343);
4225
4226 /* here to set digital part */
4227
4228 /* set gpio miso mode */
4229 capture_gpio_set(priv);
4230
4231 /* power on clock */
4232 regmap_update_bits(priv->regmap, MT6359_AUDIO_TOP_CON0,
4233 0x00ff, 0x0000);
4234
4235 /* configure ADC setting */
4236 regmap_write(priv->regmap, MT6359_AFE_TOP_CON0, 0x0000);
4237
4238 /* [0] afe enable */
4239 regmap_update_bits(priv->regmap, MT6359_AFE_UL_DL_CON0,
4240 0x0001, 0x0001);
4241
4242 mt6359_mtkaif_tx_enable(priv);
4243
4244 /* UL dmic setting */
4245 regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_H, 0x0000);
4246
4247 /* UL turn on */
4248 regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_L, 0x0001);
4249
4250 return 0;
4251}
4252
4253static int mt6359_rcv_dcc_get(struct snd_kcontrol *kcontrol,
4254 struct snd_ctl_elem_value *ucontrol)
4255{
4256 return 0;
4257}
4258
4259/* vow control */
4260static const struct snd_kcontrol_new mt6359_snd_vow_controls[] = {
4261 SOC_SINGLE_EXT("Audio VOWCFG0 Data",
4262 SND_SOC_NOPM, 0, 0x80000, 0,
4263 audio_vow_cfg_get, audio_vow_cfg_set),
4264 SOC_SINGLE_EXT("Audio VOWCFG1 Data",
4265 SND_SOC_NOPM, 0, 0x80000, 0,
4266 audio_vow_cfg_get, audio_vow_cfg_set),
4267 SOC_SINGLE_EXT("Audio VOWCFG2 Data",
4268 SND_SOC_NOPM, 0, 0x80000, 0,
4269 audio_vow_cfg_get, audio_vow_cfg_set),
4270 SOC_SINGLE_EXT("Audio VOWCFG3 Data",
4271 SND_SOC_NOPM, 0, 0x80000, 0,
4272 audio_vow_cfg_get, audio_vow_cfg_set),
4273 SOC_SINGLE_EXT("Audio VOWCFG4 Data",
4274 SND_SOC_NOPM, 0, 0x80000, 0,
4275 audio_vow_cfg_get, audio_vow_cfg_set),
4276 SOC_SINGLE_EXT("Audio VOWCFG5 Data",
4277 SND_SOC_NOPM, 0, 0x80000, 0,
4278 audio_vow_cfg_get, audio_vow_cfg_set),
4279 SOC_SINGLE_EXT("Audio_VOW_Periodic",
4280 SND_SOC_NOPM, 0, 0x80000, 0,
4281 audio_vow_cfg_get, audio_vow_cfg_set),
4282 SND_SOC_BYTES_TLV("Audio_VOW_Periodic_Param",
4283 sizeof(struct mt6359_vow_periodic_on_off_data),
4284 audio_vow_periodic_parm_get,
4285 audio_vow_periodic_parm_set),
4286};
4287
4288static const struct snd_kcontrol_new mt6359_snd_misc_controls[] = {
4289 SOC_ENUM_EXT("Headphone Plugged In", misc_control_enum[0],
4290 hp_plugged_in_get, hp_plugged_in_set),
4291 SOC_ENUM_EXT("PMIC_REG_CLEAR", misc_control_enum[0],
4292 mt6359_rcv_dcc_get, mt6359_rcv_dcc_set),
4293};
4294
4295static int mt6359_codec_init_reg(struct mt6359_priv *priv)
4296{
4297 int ret = 0;
4298
4299 /* enable clk buf */
4300 regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
4301 0x1 << RG_XO_AUDIO_EN_M_SFT,
4302 0x1 << RG_XO_AUDIO_EN_M_SFT);
4303
4304 /* set those not controlled by dapm widget */
4305
4306 /* audio clk source from internal dcxo */
4307 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
4308 RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
4309 0x0);
4310
4311 /* Disable HeadphoneL/HeadphoneR short circuit protection */
4312 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
4313 RG_AUDHPLSCDISABLE_VAUDP32_MASK_SFT,
4314 0x1 << RG_AUDHPLSCDISABLE_VAUDP32_SFT);
4315 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
4316 RG_AUDHPRSCDISABLE_VAUDP32_MASK_SFT,
4317 0x1 << RG_AUDHPRSCDISABLE_VAUDP32_SFT);
4318 /* Disable voice short circuit protection */
4319 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
4320 RG_AUDHSSCDISABLE_VAUDP32_MASK_SFT,
4321 0x1 << RG_AUDHSSCDISABLE_VAUDP32_SFT);
4322 /* disable LO buffer left short circuit protection */
4323 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
4324 RG_AUDLOLSCDISABLE_VAUDP32_MASK_SFT,
4325 0x1 << RG_AUDLOLSCDISABLE_VAUDP32_SFT);
4326
4327 /* set gpio */
4328 playback_gpio_reset(priv);
4329 capture_gpio_reset(priv);
4330
4331 /* hp gain ctl default choose ZCD */
4332 priv->hp_gain_ctl = HP_GAIN_CTL_ZCD;
4333 hp_gain_ctl_select(priv, priv->hp_gain_ctl);
4334
4335 /* hp hifi mode, default normal mode */
4336 priv->hp_hifi_mode = 0;
4337
4338 /* Disable AUD_ZCD */
4339 zcd_disable(priv);
4340
4341 /* disable clk buf */
4342 regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
4343 0x1 << RG_XO_AUDIO_EN_M_SFT,
4344 0x0);
4345
4346 return ret;
4347}
4348
4349static int mt6359_codec_probe(struct snd_soc_component *cmpnt)
4350{
4351 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
4352 int ret;
4353
4354 snd_soc_component_init_regmap(cmpnt, priv->regmap);
4355
4356 /* add codec controls */
4357 snd_soc_add_component_controls(cmpnt,
4358 mt6359_snd_misc_controls,
4359 ARRAY_SIZE(mt6359_snd_misc_controls));
4360 snd_soc_add_component_controls(cmpnt,
4361 mt6359_snd_vow_controls,
4362 ARRAY_SIZE(mt6359_snd_vow_controls));
4363
4364 mt6359_codec_init_reg(priv);
4365
4366 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = 8;
4367 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = 8;
4368 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] = 3;
4369 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] = 3;
4370 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3] = 3;
4371
4372 priv->avdd_reg = devm_regulator_get(priv->dev, "vaud18");
4373 if (IS_ERR(priv->avdd_reg)) {
4374 dev_err(priv->dev, "%s(), have no vaud18 supply", __func__);
4375 return PTR_ERR(priv->avdd_reg);
4376 }
4377
4378 ret = regulator_enable(priv->avdd_reg);
4379 if (ret)
4380 return ret;
4381
4382 return 0;
4383}
4384
4385static const struct snd_soc_component_driver mt6359_soc_component_driver = {
4386 .name = CODEC_MT6359_NAME,
4387 .probe = mt6359_codec_probe,
4388 .controls = mt6359_snd_controls,
4389 .num_controls = ARRAY_SIZE(mt6359_snd_controls),
4390 .dapm_widgets = mt6359_dapm_widgets,
4391 .num_dapm_widgets = ARRAY_SIZE(mt6359_dapm_widgets),
4392 .dapm_routes = mt6359_dapm_routes,
4393 .num_dapm_routes = ARRAY_SIZE(mt6359_dapm_routes),
4394};
4395
4396static void debug_write_reg(struct file *file, void *arg)
4397{
4398 struct mt6359_priv *priv = file->private_data;
4399 char *token1 = NULL;
4400 char *token2 = NULL;
4401 char *temp = arg;
4402 char delim[] = " ,";
4403 unsigned int reg_addr = 0;
4404 unsigned int reg_value = 0;
4405 int ret = 0;
4406
4407 token1 = strsep(&temp, delim);
4408 token2 = strsep(&temp, delim);
4409 dev_info(priv->dev, "%s(), token1 = %s, token2 = %s, temp = %s\n",
4410 __func__, token1, token2, temp);
4411
4412 if ((token1 != NULL) && (token2 != NULL)) {
4413 ret = kstrtouint(token1, 16, &reg_addr);
4414 ret = kstrtouint(token2, 16, &reg_value);
4415 dev_info(priv->dev, "%s(), reg_addr = 0x%x, reg_value = 0x%x\n",
4416 __func__,
4417 reg_addr, reg_value);
4418 regmap_write(priv->regmap, reg_addr, reg_value);
4419 regmap_read(priv->regmap, reg_addr, &reg_value);
4420 dev_info(priv->dev, "%s(), reg_addr = 0x%x, reg_value = 0x%x\n",
4421 __func__,
4422 reg_addr, reg_value);
4423 } else {
4424 dev_err(priv->dev, "token1 or token2 is NULL!\n");
4425 }
4426}
4427
4428struct command_function {
4429 const char *cmd;
4430 void (*fn)(struct file *file, void *arg);
4431};
4432
4433#define CMD_FN(_cmd, _fn) { \
4434 .cmd = _cmd, \
4435 .fn = _fn, \
4436}
4437
4438static const struct command_function debug_cmds[] = {
4439 CMD_FN("write_reg", debug_write_reg),
4440 {}
4441};
4442
4443static int mt6359_debugfs_open(struct inode *inode, struct file *file)
4444{
4445 file->private_data = inode->i_private;
4446 return 0;
4447}
4448
4449static ssize_t mt6359_debugfs_read(struct file *file, char __user *buf,
4450 size_t count, loff_t *pos)
4451{
4452 struct mt6359_priv *priv = file->private_data;
4453 const int size = 12288;
4454 char *buffer = NULL; /* for reduce kernel stack */
4455 int n = 0;
4456 unsigned int value;
4457 int ret = 0;
4458
4459 buffer = kmalloc(size, GFP_KERNEL);
4460 if (!buffer)
4461 return -ENOMEM;
4462
4463 n += scnprintf(buffer + n, size - n, "mtkaif_protocol = %d\n",
4464 priv->mtkaif_protocol);
4465
4466 regmap_read(priv->regmap, MT6359_GPIO_DIR0, &value);
4467 n += scnprintf(buffer + n, size - n,
4468 "MT6359_GPIO_DIR0 = 0x%x\n", value);
4469 regmap_read(priv->regmap, MT6359_GPIO_DIR1, &value);
4470 n += scnprintf(buffer + n, size - n,
4471 "MT6359_GPIO_DIR1 = 0x%x\n", value);
4472 regmap_read(priv->regmap, MT6359_GPIO_MODE2, &value);
4473 n += scnprintf(buffer + n, size - n,
4474 "MT6359_GPIO_MODE2 = 0x%x\n", value);
4475 regmap_read(priv->regmap, MT6359_GPIO_MODE3, &value);
4476 n += scnprintf(buffer + n, size - n,
4477 "MT6359_GPIO_MODE3 = 0x%x\n", value);
4478 regmap_read(priv->regmap, MT6359_GPIO_MODE4, &value);
4479 n += scnprintf(buffer + n, size - n,
4480 "MT6359_GPIO_MODE4 = 0x%x\n", value);
4481 regmap_read(priv->regmap, MT6359_DCXO_CW11, &value);
4482 n += scnprintf(buffer + n, size - n,
4483 "MT6359_DCXO_CW11 = 0x%x\n", value);
4484 regmap_read(priv->regmap, MT6359_DCXO_CW12, &value);
4485 n += scnprintf(buffer + n, size - n,
4486 "MT6359_DCXO_CW12 = 0x%x\n", value);
4487 regmap_read(priv->regmap, MT6359_LDO_VAUD18_CON0, &value);
4488 n += scnprintf(buffer + n, size - n,
4489 "MT6359_LDO_VAUD18_CON0 = 0x%x\n", value);
4490 regmap_read(priv->regmap, MT6359_AUD_TOP_ID, &value);
4491 n += scnprintf(buffer + n, size - n,
4492 "MT6359_AUD_TOP_ID = 0x%x\n", value);
4493 regmap_read(priv->regmap, MT6359_AUD_TOP_REV0, &value);
4494 n += scnprintf(buffer + n, size - n,
4495 "MT6359_AUD_TOP_REV0 = 0x%x\n", value);
4496 regmap_read(priv->regmap, MT6359_AUD_TOP_DBI, &value);
4497 n += scnprintf(buffer + n, size - n,
4498 "MT6359_AUD_TOP_DBI = 0x%x\n", value);
4499 regmap_read(priv->regmap, MT6359_AUD_TOP_DXI, &value);
4500 n += scnprintf(buffer + n, size - n,
4501 "MT6359_AUD_TOP_DXI = 0x%x\n", value);
4502 regmap_read(priv->regmap, MT6359_AUD_TOP_CKPDN_TPM0, &value);
4503 n += scnprintf(buffer + n, size - n,
4504 "MT6359_AUD_TOP_CKPDN_TPM0 = 0x%x\n", value);
4505 regmap_read(priv->regmap, MT6359_AUD_TOP_CKPDN_TPM1, &value);
4506 n += scnprintf(buffer + n, size - n,
4507 "MT6359_AUD_TOP_CKPDN_TPM1 = 0x%x\n", value);
4508 regmap_read(priv->regmap, MT6359_AUD_TOP_CKPDN_CON0, &value);
4509 n += scnprintf(buffer + n, size - n,
4510 "MT6359_AUD_TOP_CKPDN_CON0 = 0x%x\n", value);
4511 regmap_read(priv->regmap, MT6359_AUD_TOP_CKPDN_CON0_SET, &value);
4512 n += scnprintf(buffer + n, size - n,
4513 "MT6359_AUD_TOP_CKPDN_CON0_SET = 0x%x\n", value);
4514 regmap_read(priv->regmap, MT6359_AUD_TOP_CKPDN_CON0_CLR, &value);
4515 n += scnprintf(buffer + n, size - n,
4516 "MT6359_AUD_TOP_CKPDN_CON0_CLR = 0x%x\n", value);
4517 regmap_read(priv->regmap, MT6359_AUD_TOP_CKSEL_CON0, &value);
4518 n += scnprintf(buffer + n, size - n,
4519 "MT6359_AUD_TOP_CKSEL_CON0 = 0x%x\n", value);
4520 regmap_read(priv->regmap, MT6359_AUD_TOP_CKSEL_CON0_SET, &value);
4521 n += scnprintf(buffer + n, size - n,
4522 "MT6359_AUD_TOP_CKSEL_CON0_SET = 0x%x\n", value);
4523 regmap_read(priv->regmap, MT6359_AUD_TOP_CKSEL_CON0_CLR, &value);
4524 n += scnprintf(buffer + n, size - n,
4525 "MT6359_AUD_TOP_CKSEL_CON0_CLR = 0x%x\n", value);
4526 regmap_read(priv->regmap, MT6359_AUD_TOP_CKTST_CON0, &value);
4527 n += scnprintf(buffer + n, size - n,
4528 "MT6359_AUD_TOP_CKTST_CON0 = 0x%x\n", value);
4529 regmap_read(priv->regmap, MT6359_AUD_TOP_CLK_HWEN_CON0, &value);
4530 n += scnprintf(buffer + n, size - n,
4531 "MT6359_AUD_TOP_CLK_HWEN_CON0 = 0x%x\n", value);
4532 regmap_read(priv->regmap, MT6359_AUD_TOP_CLK_HWEN_CON0_SET, &value);
4533 n += scnprintf(buffer + n, size - n,
4534 "MT6359_AUD_TOP_CLK_HWEN_CON0_SET = 0x%x\n", value);
4535 regmap_read(priv->regmap, MT6359_AUD_TOP_CLK_HWEN_CON0_CLR, &value);
4536 n += scnprintf(buffer + n, size - n,
4537 "MT6359_AUD_TOP_CLK_HWEN_CON0_CLR = 0x%x\n", value);
4538 regmap_read(priv->regmap, MT6359_AUD_TOP_RST_CON0, &value);
4539 n += scnprintf(buffer + n, size - n,
4540 "MT6359_AUD_TOP_RST_CON0 = 0x%x\n", value);
4541 regmap_read(priv->regmap, MT6359_AUD_TOP_RST_CON0_SET, &value);
4542 n += scnprintf(buffer + n, size - n,
4543 "MT6359_AUD_TOP_RST_CON0_SET = 0x%x\n", value);
4544 regmap_read(priv->regmap, MT6359_AUD_TOP_RST_CON0_CLR, &value);
4545 n += scnprintf(buffer + n, size - n,
4546 "MT6359_AUD_TOP_RST_CON0_CLR = 0x%x\n", value);
4547 regmap_read(priv->regmap, MT6359_AUD_TOP_RST_BANK_CON0, &value);
4548 n += scnprintf(buffer + n, size - n,
4549 "MT6359_AUD_TOP_RST_BANK_CON0 = 0x%x\n", value);
4550 regmap_read(priv->regmap, MT6359_AUD_TOP_INT_CON0, &value);
4551 n += scnprintf(buffer + n, size - n,
4552 "MT6359_AUD_TOP_INT_CON0 = 0x%x\n", value);
4553 regmap_read(priv->regmap, MT6359_AUD_TOP_INT_CON0_SET, &value);
4554 n += scnprintf(buffer + n, size - n,
4555 "MT6359_AUD_TOP_INT_CON0_SET = 0x%x\n", value);
4556 regmap_read(priv->regmap, MT6359_AUD_TOP_INT_CON0_CLR, &value);
4557 n += scnprintf(buffer + n, size - n,
4558 "MT6359_AUD_TOP_INT_CON0_CLR = 0x%x\n", value);
4559 regmap_read(priv->regmap, MT6359_AUD_TOP_INT_MASK_CON0, &value);
4560 n += scnprintf(buffer + n, size - n,
4561 "MT6359_AUD_TOP_INT_MASK_CON0 = 0x%x\n", value);
4562 regmap_read(priv->regmap, MT6359_AUD_TOP_INT_MASK_CON0_SET, &value);
4563 n += scnprintf(buffer + n, size - n,
4564 "MT6359_AUD_TOP_INT_MASK_CON0_SET = 0x%x\n", value);
4565 regmap_read(priv->regmap, MT6359_AUD_TOP_INT_MASK_CON0_CLR, &value);
4566 n += scnprintf(buffer + n, size - n,
4567 "MT6359_AUD_TOP_INT_MASK_CON0_CLR = 0x%x\n", value);
4568 regmap_read(priv->regmap, MT6359_AUD_TOP_INT_STATUS0, &value);
4569 n += scnprintf(buffer + n, size - n,
4570 "MT6359_AUD_TOP_INT_STATUS0 = 0x%x\n", value);
4571 regmap_read(priv->regmap, MT6359_AUD_TOP_INT_RAW_STATUS0, &value);
4572 n += scnprintf(buffer + n, size - n,
4573 "MT6359_AUD_TOP_INT_RAW_STATUS0 = 0x%x\n", value);
4574 regmap_read(priv->regmap, MT6359_AUD_TOP_INT_MISC_CON0, &value);
4575 n += scnprintf(buffer + n, size - n,
4576 "MT6359_AUD_TOP_INT_MISC_CON0 = 0x%x\n", value);
4577 regmap_read(priv->regmap, MT6359_AUD_TOP_MON_CON0, &value);
4578 n += scnprintf(buffer + n, size - n,
4579 "MT6359_AUD_TOP_MON_CON0 = 0x%x\n", value);
4580 regmap_read(priv->regmap, MT6359_AUDIO_DIG_DSN_ID, &value);
4581 n += scnprintf(buffer + n, size - n,
4582 "MT6359_AUDIO_DIG_DSN_ID = 0x%x\n", value);
4583 regmap_read(priv->regmap, MT6359_AUDIO_DIG_DSN_REV0, &value);
4584 n += scnprintf(buffer + n, size - n,
4585 "MT6359_AUDIO_DIG_DSN_REV0 = 0x%x\n", value);
4586 regmap_read(priv->regmap, MT6359_AUDIO_DIG_DSN_DBI, &value);
4587 n += scnprintf(buffer + n, size - n,
4588 "MT6359_AUDIO_DIG_DSN_DBI = 0x%x\n", value);
4589 regmap_read(priv->regmap, MT6359_AUDIO_DIG_DSN_DXI, &value);
4590 n += scnprintf(buffer + n, size - n,
4591 "MT6359_AUDIO_DIG_DSN_DXI = 0x%x\n", value);
4592 regmap_read(priv->regmap, MT6359_AFE_UL_DL_CON0, &value);
4593 n += scnprintf(buffer + n, size - n,
4594 "MT6359_AFE_UL_DL_CON0 = 0x%x\n", value);
4595 regmap_read(priv->regmap, MT6359_AFE_DL_SRC2_CON0_L, &value);
4596 n += scnprintf(buffer + n, size - n,
4597 "MT6359_AFE_DL_SRC2_CON0_L = 0x%x\n", value);
4598 regmap_read(priv->regmap, MT6359_AFE_UL_SRC_CON0_H, &value);
4599 n += scnprintf(buffer + n, size - n,
4600 "MT6359_AFE_UL_SRC_CON0_H = 0x%x\n", value);
4601 regmap_read(priv->regmap, MT6359_AFE_UL_SRC_CON0_L, &value);
4602 n += scnprintf(buffer + n, size - n,
4603 "MT6359_AFE_UL_SRC_CON0_L = 0x%x\n", value);
4604 regmap_read(priv->regmap, MT6359_AFE_ADDA6_L_SRC_CON0_H, &value);
4605 n += scnprintf(buffer + n, size - n,
4606 "MT6359_AFE_ADDA6_L_SRC_CON0_H = 0x%x\n", value);
4607 regmap_read(priv->regmap, MT6359_AFE_ADDA6_UL_SRC_CON0_L, &value);
4608 n += scnprintf(buffer + n, size - n,
4609 "MT6359_AFE_ADDA6_UL_SRC_CON0_L = 0x%x\n", value);
4610 regmap_read(priv->regmap, MT6359_AFE_TOP_CON0, &value);
4611 n += scnprintf(buffer + n, size - n,
4612 "MT6359_AFE_TOP_CON0 = 0x%x\n", value);
4613 regmap_read(priv->regmap, MT6359_AUDIO_TOP_CON0, &value);
4614 n += scnprintf(buffer + n, size - n,
4615 "MT6359_AUDIO_TOP_CON0 = 0x%x\n", value);
4616 regmap_read(priv->regmap, MT6359_AFE_MON_DEBUG0, &value);
4617 n += scnprintf(buffer + n, size - n,
4618 "MT6359_AFE_MON_DEBUG0 = 0x%x\n", value);
4619 regmap_read(priv->regmap, MT6359_AFUNC_AUD_CON0, &value);
4620 n += scnprintf(buffer + n, size - n,
4621 "MT6359_AFUNC_AUD_CON0 = 0x%x\n", value);
4622 regmap_read(priv->regmap, MT6359_AFUNC_AUD_CON1, &value);
4623 n += scnprintf(buffer + n, size - n,
4624 "MT6359_AFUNC_AUD_CON1 = 0x%x\n", value);
4625 regmap_read(priv->regmap, MT6359_AFUNC_AUD_CON2, &value);
4626 n += scnprintf(buffer + n, size - n,
4627 "MT6359_AFUNC_AUD_CON2 = 0x%x\n", value);
4628 regmap_read(priv->regmap, MT6359_AFUNC_AUD_CON3, &value);
4629 n += scnprintf(buffer + n, size - n,
4630 "MT6359_AFUNC_AUD_CON3 = 0x%x\n", value);
4631 regmap_read(priv->regmap, MT6359_AFUNC_AUD_CON4, &value);
4632 n += scnprintf(buffer + n, size - n,
4633 "MT6359_AFUNC_AUD_CON4 = 0x%x\n", value);
4634 regmap_read(priv->regmap, MT6359_AFUNC_AUD_CON5, &value);
4635 n += scnprintf(buffer + n, size - n,
4636 "MT6359_AFUNC_AUD_CON5 = 0x%x\n", value);
4637 regmap_read(priv->regmap, MT6359_AFUNC_AUD_CON6, &value);
4638 n += scnprintf(buffer + n, size - n,
4639 "MT6359_AFUNC_AUD_CON6 = 0x%x\n", value);
4640 regmap_read(priv->regmap, MT6359_AFUNC_AUD_CON7, &value);
4641 n += scnprintf(buffer + n, size - n,
4642 "MT6359_AFUNC_AUD_CON7 = 0x%x\n", value);
4643 regmap_read(priv->regmap, MT6359_AFUNC_AUD_CON8, &value);
4644 n += scnprintf(buffer + n, size - n,
4645 "MT6359_AFUNC_AUD_CON8 = 0x%x\n", value);
4646 regmap_read(priv->regmap, MT6359_AFUNC_AUD_CON9, &value);
4647 n += scnprintf(buffer + n, size - n,
4648 "MT6359_AFUNC_AUD_CON9 = 0x%x\n", value);
4649 regmap_read(priv->regmap, MT6359_AFUNC_AUD_CON10, &value);
4650 n += scnprintf(buffer + n, size - n,
4651 "MT6359_AFUNC_AUD_CON10 = 0x%x\n", value);
4652 regmap_read(priv->regmap, MT6359_AFUNC_AUD_CON11, &value);
4653 n += scnprintf(buffer + n, size - n,
4654 "MT6359_AFUNC_AUD_CON11 = 0x%x\n", value);
4655 regmap_read(priv->regmap, MT6359_AFUNC_AUD_CON12, &value);
4656 n += scnprintf(buffer + n, size - n,
4657 "MT6359_AFUNC_AUD_CON12 = 0x%x\n", value);
4658 regmap_read(priv->regmap, MT6359_AFUNC_AUD_MON0, &value);
4659 n += scnprintf(buffer + n, size - n,
4660 "MT6359_AFUNC_AUD_MON0 = 0x%x\n", value);
4661 regmap_read(priv->regmap, MT6359_AFUNC_AUD_MON1, &value);
4662 n += scnprintf(buffer + n, size - n,
4663 "MT6359_AFUNC_AUD_MON1 = 0x%x\n", value);
4664 regmap_read(priv->regmap, MT6359_AUDRC_TUNE_MON0, &value);
4665 n += scnprintf(buffer + n, size - n,
4666 "MT6359_AUDRC_TUNE_MON0 = 0x%x\n", value);
4667 regmap_read(priv->regmap, MT6359_AFE_ADDA_MTKAIF_FIFO_CFG0, &value);
4668 n += scnprintf(buffer + n, size - n,
4669 "MT6359_AFE_ADDA_MTKAIF_FIFO_CFG0 = 0x%x\n", value);
4670 regmap_read(priv->regmap, MT6359_AFE_ADDA_MTKAIF_FIFO_LOG_MON1, &value);
4671 n += scnprintf(buffer + n, size - n,
4672 "MT6359_AFE_ADDA_MTKAIF_FIFO_LOG_MON1 = 0x%x\n", value);
4673 regmap_read(priv->regmap, MT6359_AFE_ADDA_MTKAIF_MON0, &value);
4674 n += scnprintf(buffer + n, size - n,
4675 "MT6359_AFE_ADDA_MTKAIF_MON0 = 0x%x\n", value);
4676 regmap_read(priv->regmap, MT6359_AFE_ADDA_MTKAIF_MON1, &value);
4677 n += scnprintf(buffer + n, size - n,
4678 "MT6359_AFE_ADDA_MTKAIF_MON1 = 0x%x\n", value);
4679 regmap_read(priv->regmap, MT6359_AFE_ADDA_MTKAIF_MON2, &value);
4680 n += scnprintf(buffer + n, size - n,
4681 "MT6359_AFE_ADDA_MTKAIF_MON2 = 0x%x\n", value);
4682 regmap_read(priv->regmap, MT6359_AFE_ADDA6_MTKAIF_MON3, &value);
4683 n += scnprintf(buffer + n, size - n,
4684 "MT6359_AFE_ADDA6_MTKAIF_MON3 = 0x%x\n", value);
4685 regmap_read(priv->regmap, MT6359_AFE_ADDA_MTKAIF_MON4, &value);
4686 n += scnprintf(buffer + n, size - n,
4687 "MT6359_AFE_ADDA_MTKAIF_MON4 = 0x%x\n", value);
4688 regmap_read(priv->regmap, MT6359_AFE_ADDA_MTKAIF_MON5, &value);
4689 n += scnprintf(buffer + n, size - n,
4690 "MT6359_AFE_ADDA_MTKAIF_MON5 = 0x%x\n", value);
4691 regmap_read(priv->regmap, MT6359_AFE_ADDA_MTKAIF_CFG0, &value);
4692 n += scnprintf(buffer + n, size - n,
4693 "MT6359_AFE_ADDA_MTKAIF_CFG0 = 0x%x\n", value);
4694 regmap_read(priv->regmap, MT6359_AFE_ADDA_MTKAIF_RX_CFG0, &value);
4695 n += scnprintf(buffer + n, size - n,
4696 "MT6359_AFE_ADDA_MTKAIF_RX_CFG0 = 0x%x\n", value);
4697 regmap_read(priv->regmap, MT6359_AFE_ADDA_MTKAIF_RX_CFG1, &value);
4698 n += scnprintf(buffer + n, size - n,
4699 "MT6359_AFE_ADDA_MTKAIF_RX_CFG1 = 0x%x\n", value);
4700 regmap_read(priv->regmap, MT6359_AFE_ADDA_MTKAIF_RX_CFG2, &value);
4701 n += scnprintf(buffer + n, size - n,
4702 "MT6359_AFE_ADDA_MTKAIF_RX_CFG2 = 0x%x\n", value);
4703 regmap_read(priv->regmap, MT6359_AFE_ADDA_MTKAIF_RX_CFG3, &value);
4704 n += scnprintf(buffer + n, size - n,
4705 "MT6359_AFE_ADDA_MTKAIF_RX_CFG3 = 0x%x\n", value);
4706 regmap_read(priv->regmap, MT6359_AFE_ADDA_MTKAIF_SYNCWORD_CFG0, &value);
4707 n += scnprintf(buffer + n, size - n,
4708 "MT6359_AFE_ADDA_MTKAIF_SYNCWORD_CFG0 = 0x%x\n", value);
4709 regmap_read(priv->regmap, MT6359_AFE_ADDA_MTKAIF_SYNCWORD_CFG1, &value);
4710 n += scnprintf(buffer + n, size - n,
4711 "MT6359_AFE_ADDA_MTKAIF_SYNCWORD_CFG1 = 0x%x\n", value);
4712 regmap_read(priv->regmap, MT6359_AFE_SGEN_CFG0, &value);
4713 n += scnprintf(buffer + n, size - n,
4714 "MT6359_AFE_SGEN_CFG0 = 0x%x\n", value);
4715 regmap_read(priv->regmap, MT6359_AFE_SGEN_CFG1, &value);
4716 n += scnprintf(buffer + n, size - n,
4717 "MT6359_AFE_SGEN_CFG1 = 0x%x\n", value);
4718 regmap_read(priv->regmap, MT6359_AFE_ADC_ASYNC_FIFO_CFG, &value);
4719 n += scnprintf(buffer + n, size - n,
4720 "MT6359_AFE_ADC_ASYNC_FIFO_CFG = 0x%x\n", value);
4721 regmap_read(priv->regmap, MT6359_AFE_ADC_ASYNC_FIFO_CFG1, &value);
4722 n += scnprintf(buffer + n, size - n,
4723 "MT6359_AFE_ADC_ASYNC_FIFO_CFG1 = 0x%x\n", value);
4724 regmap_read(priv->regmap, MT6359_AFE_DCCLK_CFG0, &value);
4725 n += scnprintf(buffer + n, size - n,
4726 "MT6359_AFE_DCCLK_CFG0 = 0x%x\n", value);
4727 regmap_read(priv->regmap, MT6359_AFE_DCCLK_CFG1, &value);
4728 n += scnprintf(buffer + n, size - n,
4729 "MT6359_AFE_DCCLK_CFG1 = 0x%x\n", value);
4730 regmap_read(priv->regmap, MT6359_AUDIO_DIG_CFG, &value);
4731 n += scnprintf(buffer + n, size - n,
4732 "MT6359_AUDIO_DIG_CFG = 0x%x\n", value);
4733 regmap_read(priv->regmap, MT6359_AUDIO_DIG_CFG1, &value);
4734 n += scnprintf(buffer + n, size - n,
4735 "MT6359_AUDIO_DIG_CFG1 = 0x%x\n", value);
4736 regmap_read(priv->regmap, MT6359_AFE_AUD_PAD_TOP, &value);
4737 n += scnprintf(buffer + n, size - n,
4738 "MT6359_AFE_AUD_PAD_TOP = 0x%x\n", value);
4739 regmap_read(priv->regmap, MT6359_AFE_AUD_PAD_TOP_MON, &value);
4740 n += scnprintf(buffer + n, size - n,
4741 "MT6359_AFE_AUD_PAD_TOP_MON = 0x%x\n", value);
4742 regmap_read(priv->regmap, MT6359_AFE_AUD_PAD_TOP_MON1, &value);
4743 n += scnprintf(buffer + n, size - n,
4744 "MT6359_AFE_AUD_PAD_TOP_MON1 = 0x%x\n", value);
4745 regmap_read(priv->regmap, MT6359_AFE_AUD_PAD_TOP_MON2, &value);
4746 n += scnprintf(buffer + n, size - n,
4747 "MT6359_AFE_AUD_PAD_TOP_MON2 = 0x%x\n", value);
4748 regmap_read(priv->regmap, MT6359_AFE_DL_NLE_CFG, &value);
4749 n += scnprintf(buffer + n, size - n,
4750 "MT6359_AFE_DL_NLE_CFG = 0x%x\n", value);
4751 regmap_read(priv->regmap, MT6359_AFE_DL_NLE_MON, &value);
4752 n += scnprintf(buffer + n, size - n,
4753 "MT6359_AFE_DL_NLE_MON = 0x%x\n", value);
4754 regmap_read(priv->regmap, MT6359_AFE_CG_EN_MON, &value);
4755 n += scnprintf(buffer + n, size - n,
4756 "MT6359_AFE_CG_EN_MON = 0x%x\n", value);
4757 regmap_read(priv->regmap, MT6359_AFE_MIC_ARRAY_CFG, &value);
4758 n += scnprintf(buffer + n, size - n,
4759 "MT6359_AFE_MIC_ARRAY_CFG = 0x%x\n", value);
4760 regmap_read(priv->regmap, MT6359_AFE_CHOP_CFG0, &value);
4761 n += scnprintf(buffer + n, size - n,
4762 "MT6359_AFE_CHOP_CFG0 = 0x%x\n", value);
4763 regmap_read(priv->regmap, MT6359_AFE_MTKAIF_MUX_CFG, &value);
4764 n += scnprintf(buffer + n, size - n,
4765 "MT6359_AFE_MTKAIF_MUX_CFG = 0x%x\n", value);
4766 regmap_read(priv->regmap, MT6359_AUDIO_DIG_2ND_DSN_ID, &value);
4767 n += scnprintf(buffer + n, size - n,
4768 "MT6359_AUDIO_DIG_2ND_DSN_ID = 0x%x\n", value);
4769 regmap_read(priv->regmap, MT6359_AUDIO_DIG_2ND_DSN_REV0, &value);
4770 n += scnprintf(buffer + n, size - n,
4771 "MT6359_AUDIO_DIG_2ND_DSN_REV0 = 0x%x\n", value);
4772 regmap_read(priv->regmap, MT6359_AUDIO_DIG_2ND_DSN_DBI, &value);
4773 n += scnprintf(buffer + n, size - n,
4774 "MT6359_AUDIO_DIG_2ND_DSN_DBI = 0x%x\n", value);
4775 regmap_read(priv->regmap, MT6359_AUDIO_DIG_2ND_DSN_DXI, &value);
4776 n += scnprintf(buffer + n, size - n,
4777 "MT6359_AUDIO_DIG_2ND_DSN_DXI = 0x%x\n", value);
4778 regmap_read(priv->regmap, MT6359_AFE_PMIC_NEWIF_CFG3, &value);
4779 n += scnprintf(buffer + n, size - n,
4780 "MT6359_AFE_PMIC_NEWIF_CFG3 = 0x%x\n", value);
4781 regmap_read(priv->regmap, MT6359_AFE_VOW_TOP_CON0, &value);
4782 n += scnprintf(buffer + n, size - n,
4783 "MT6359_AFE_VOW_TOP_CON0 = 0x%x\n", value);
4784 regmap_read(priv->regmap, MT6359_AFE_VOW_TOP_CON1, &value);
4785 n += scnprintf(buffer + n, size - n,
4786 "MT6359_AFE_VOW_TOP_CON1 = 0x%x\n", value);
4787 regmap_read(priv->regmap, MT6359_AFE_VOW_TOP_CON2, &value);
4788 n += scnprintf(buffer + n, size - n,
4789 "MT6359_AFE_VOW_TOP_CON2 = 0x%x\n", value);
4790 regmap_read(priv->regmap, MT6359_AFE_VOW_TOP_CON3, &value);
4791 n += scnprintf(buffer + n, size - n,
4792 "MT6359_AFE_VOW_TOP_CON3 = 0x%x\n", value);
4793 regmap_read(priv->regmap, MT6359_AFE_VOW_TOP_CON4, &value);
4794 n += scnprintf(buffer + n, size - n,
4795 "MT6359_AFE_VOW_TOP_CON4 = 0x%x\n", value);
4796 regmap_read(priv->regmap, MT6359_AFE_VOW_TOP_MON0, &value);
4797 n += scnprintf(buffer + n, size - n,
4798 "MT6359_AFE_VOW_TOP_MON0 = 0x%x\n", value);
4799 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_CFG0, &value);
4800 n += scnprintf(buffer + n, size - n,
4801 "MT6359_AFE_VOW_VAD_CFG0 = 0x%x\n", value);
4802 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_CFG1, &value);
4803 n += scnprintf(buffer + n, size - n,
4804 "MT6359_AFE_VOW_VAD_CFG1 = 0x%x\n", value);
4805 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_CFG2, &value);
4806 n += scnprintf(buffer + n, size - n,
4807 "MT6359_AFE_VOW_VAD_CFG2 = 0x%x\n", value);
4808 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_CFG3, &value);
4809 n += scnprintf(buffer + n, size - n,
4810 "MT6359_AFE_VOW_VAD_CFG3 = 0x%x\n", value);
4811 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_CFG4, &value);
4812 n += scnprintf(buffer + n, size - n,
4813 "MT6359_AFE_VOW_VAD_CFG4 = 0x%x\n", value);
4814 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_CFG5, &value);
4815 n += scnprintf(buffer + n, size - n,
4816 "MT6359_AFE_VOW_VAD_CFG5 = 0x%x\n", value);
4817 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_CFG6, &value);
4818 n += scnprintf(buffer + n, size - n,
4819 "MT6359_AFE_VOW_VAD_CFG6 = 0x%x\n", value);
4820 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_CFG7, &value);
4821 n += scnprintf(buffer + n, size - n,
4822 "MT6359_AFE_VOW_VAD_CFG7 = 0x%x\n", value);
4823 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_CFG8, &value);
4824 n += scnprintf(buffer + n, size - n,
4825 "MT6359_AFE_VOW_VAD_CFG8 = 0x%x\n", value);
4826 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_CFG9, &value);
4827 n += scnprintf(buffer + n, size - n,
4828 "MT6359_AFE_VOW_VAD_CFG9 = 0x%x\n", value);
4829 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_CFG10, &value);
4830 n += scnprintf(buffer + n, size - n,
4831 "MT6359_AFE_VOW_VAD_CFG10 = 0x%x\n", value);
4832 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_CFG11, &value);
4833 n += scnprintf(buffer + n, size - n,
4834 "MT6359_AFE_VOW_VAD_CFG11 = 0x%x\n", value);
4835 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_CFG12, &value);
4836 n += scnprintf(buffer + n, size - n,
4837 "MT6359_AFE_VOW_VAD_CFG12 = 0x%x\n", value);
4838 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_MON0, &value);
4839 n += scnprintf(buffer + n, size - n,
4840 "MT6359_AFE_VOW_VAD_MON0 = 0x%x\n", value);
4841 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_MON1, &value);
4842 n += scnprintf(buffer + n, size - n,
4843 "MT6359_AFE_VOW_VAD_MON1 = 0x%x\n", value);
4844 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_MON2, &value);
4845 n += scnprintf(buffer + n, size - n,
4846 "MT6359_AFE_VOW_VAD_MON2 = 0x%x\n", value);
4847 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_MON3, &value);
4848 n += scnprintf(buffer + n, size - n,
4849 "MT6359_AFE_VOW_VAD_MON3 = 0x%x\n", value);
4850 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_MON4, &value);
4851 n += scnprintf(buffer + n, size - n,
4852 "MT6359_AFE_VOW_VAD_MON4 = 0x%x\n", value);
4853 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_MON5, &value);
4854 n += scnprintf(buffer + n, size - n,
4855 "MT6359_AFE_VOW_VAD_MON5 = 0x%x\n", value);
4856 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_MON6, &value);
4857 n += scnprintf(buffer + n, size - n,
4858 "MT6359_AFE_VOW_VAD_MON6 = 0x%x\n", value);
4859 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_MON7, &value);
4860 n += scnprintf(buffer + n, size - n,
4861 "MT6359_AFE_VOW_VAD_MON7 = 0x%x\n", value);
4862 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_MON8, &value);
4863 n += scnprintf(buffer + n, size - n,
4864 "MT6359_AFE_VOW_VAD_MON8 = 0x%x\n", value);
4865 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_MON9, &value);
4866 n += scnprintf(buffer + n, size - n,
4867 "MT6359_AFE_VOW_VAD_MON9 = 0x%x\n", value);
4868 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_MON10, &value);
4869 n += scnprintf(buffer + n, size - n,
4870 "MT6359_AFE_VOW_VAD_MON10 = 0x%x\n", value);
4871 regmap_read(priv->regmap, MT6359_AFE_VOW_VAD_MON11, &value);
4872 n += scnprintf(buffer + n, size - n,
4873 "MT6359_AFE_VOW_VAD_MON11 = 0x%x\n", value);
4874 regmap_read(priv->regmap, MT6359_AFE_VOW_TGEN_CFG0, &value);
4875 n += scnprintf(buffer + n, size - n,
4876 "MT6359_AFE_VOW_TGEN_CFG0 = 0x%x\n", value);
4877 regmap_read(priv->regmap, MT6359_AFE_VOW_TGEN_CFG1, &value);
4878 n += scnprintf(buffer + n, size - n,
4879 "MT6359_AFE_VOW_TGEN_CFG1 = 0x%x\n", value);
4880 regmap_read(priv->regmap, MT6359_AFE_VOW_HPF_CFG0, &value);
4881 n += scnprintf(buffer + n, size - n,
4882 "MT6359_AFE_VOW_HPF_CFG0 = 0x%x\n", value);
4883 regmap_read(priv->regmap, MT6359_AFE_VOW_HPF_CFG1, &value);
4884 n += scnprintf(buffer + n, size - n,
4885 "MT6359_AFE_VOW_HPF_CFG1 = 0x%x\n", value);
4886 regmap_read(priv->regmap, MT6359_AUDIO_DIG_3RD_DSN_ID, &value);
4887 n += scnprintf(buffer + n, size - n,
4888 "MT6359_AUDIO_DIG_3RD_DSN_ID = 0x%x\n", value);
4889 regmap_read(priv->regmap, MT6359_AUDIO_DIG_3RD_DSN_REV0, &value);
4890 n += scnprintf(buffer + n, size - n,
4891 "MT6359_AUDIO_DIG_3RD_DSN_REV0 = 0x%x\n", value);
4892 regmap_read(priv->regmap, MT6359_AUDIO_DIG_3RD_DSN_DBI, &value);
4893 n += scnprintf(buffer + n, size - n,
4894 "MT6359_AUDIO_DIG_3RD_DSN_DBI = 0x%x\n", value);
4895 regmap_read(priv->regmap, MT6359_AUDIO_DIG_3RD_DSN_DXI, &value);
4896 n += scnprintf(buffer + n, size - n,
4897 "MT6359_AUDIO_DIG_3RD_DSN_DXI = 0x%x\n", value);
4898 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG0, &value);
4899 n += scnprintf(buffer + n, size - n,
4900 "MT6359_AFE_VOW_PERIODIC_CFG0 = 0x%x\n", value);
4901 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG1, &value);
4902 n += scnprintf(buffer + n, size - n,
4903 "MT6359_AFE_VOW_PERIODIC_CFG1 = 0x%x\n", value);
4904 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG2, &value);
4905 n += scnprintf(buffer + n, size - n,
4906 "MT6359_AFE_VOW_PERIODIC_CFG2 = 0x%x\n", value);
4907 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG3, &value);
4908 n += scnprintf(buffer + n, size - n,
4909 "MT6359_AFE_VOW_PERIODIC_CFG3 = 0x%x\n", value);
4910 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG4, &value);
4911 n += scnprintf(buffer + n, size - n,
4912 "MT6359_AFE_VOW_PERIODIC_CFG4 = 0x%x\n", value);
4913 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG5, &value);
4914 n += scnprintf(buffer + n, size - n,
4915 "MT6359_AFE_VOW_PERIODIC_CFG5 = 0x%x\n", value);
4916 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG6, &value);
4917 n += scnprintf(buffer + n, size - n,
4918 "MT6359_AFE_VOW_PERIODIC_CFG6 = 0x%x\n", value);
4919 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG7, &value);
4920 n += scnprintf(buffer + n, size - n,
4921 "MT6359_AFE_VOW_PERIODIC_CFG7 = 0x%x\n", value);
4922 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG8, &value);
4923 n += scnprintf(buffer + n, size - n,
4924 "MT6359_AFE_VOW_PERIODIC_CFG8 = 0x%x\n", value);
4925 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG9, &value);
4926 n += scnprintf(buffer + n, size - n,
4927 "MT6359_AFE_VOW_PERIODIC_CFG9 = 0x%x\n", value);
4928 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG10, &value);
4929 n += scnprintf(buffer + n, size - n,
4930 "MT6359_AFE_VOW_PERIODIC_CFG10 = 0x%x\n", value);
4931 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG11, &value);
4932 n += scnprintf(buffer + n, size - n,
4933 "MT6359_AFE_VOW_PERIODIC_CFG11 = 0x%x\n", value);
4934 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG12, &value);
4935 n += scnprintf(buffer + n, size - n,
4936 "MT6359_AFE_VOW_PERIODIC_CFG12 = 0x%x\n", value);
4937 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG13, &value);
4938 n += scnprintf(buffer + n, size - n,
4939 "MT6359_AFE_VOW_PERIODIC_CFG13 = 0x%x\n", value);
4940 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG14, &value);
4941 n += scnprintf(buffer + n, size - n,
4942 "MT6359_AFE_VOW_PERIODIC_CFG14 = 0x%x\n", value);
4943 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG15, &value);
4944 n += scnprintf(buffer + n, size - n,
4945 "MT6359_AFE_VOW_PERIODIC_CFG15 = 0x%x\n", value);
4946 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG16, &value);
4947 n += scnprintf(buffer + n, size - n,
4948 "MT6359_AFE_VOW_PERIODIC_CFG16 = 0x%x\n", value);
4949 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG17, &value);
4950 n += scnprintf(buffer + n, size - n,
4951 "MT6359_AFE_VOW_PERIODIC_CFG17 = 0x%x\n", value);
4952 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG18, &value);
4953 n += scnprintf(buffer + n, size - n,
4954 "MT6359_AFE_VOW_PERIODIC_CFG18 = 0x%x\n", value);
4955 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG19, &value);
4956 n += scnprintf(buffer + n, size - n,
4957 "MT6359_AFE_VOW_PERIODIC_CFG19 = 0x%x\n", value);
4958 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG20, &value);
4959 n += scnprintf(buffer + n, size - n,
4960 "MT6359_AFE_VOW_PERIODIC_CFG20 = 0x%x\n", value);
4961 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG21, &value);
4962 n += scnprintf(buffer + n, size - n,
4963 "MT6359_AFE_VOW_PERIODIC_CFG21 = 0x%x\n", value);
4964 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG22, &value);
4965 n += scnprintf(buffer + n, size - n,
4966 "MT6359_AFE_VOW_PERIODIC_CFG22 = 0x%x\n", value);
4967 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG23, &value);
4968 n += scnprintf(buffer + n, size - n,
4969 "MT6359_AFE_VOW_PERIODIC_CFG23 = 0x%x\n", value);
4970 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG24, &value);
4971 n += scnprintf(buffer + n, size - n,
4972 "MT6359_AFE_VOW_PERIODIC_CFG24 = 0x%x\n", value);
4973 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG25, &value);
4974 n += scnprintf(buffer + n, size - n,
4975 "MT6359_AFE_VOW_PERIODIC_CFG25 = 0x%x\n", value);
4976 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG26, &value);
4977 n += scnprintf(buffer + n, size - n,
4978 "MT6359_AFE_VOW_PERIODIC_CFG26 = 0x%x\n", value);
4979 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG27, &value);
4980 n += scnprintf(buffer + n, size - n,
4981 "MT6359_AFE_VOW_PERIODIC_CFG27 = 0x%x\n", value);
4982 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG28, &value);
4983 n += scnprintf(buffer + n, size - n,
4984 "MT6359_AFE_VOW_PERIODIC_CFG28 = 0x%x\n", value);
4985 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG29, &value);
4986 n += scnprintf(buffer + n, size - n,
4987 "MT6359_AFE_VOW_PERIODIC_CFG29 = 0x%x\n", value);
4988 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG30, &value);
4989 n += scnprintf(buffer + n, size - n,
4990 "MT6359_AFE_VOW_PERIODIC_CFG30 = 0x%x\n", value);
4991 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG31, &value);
4992 n += scnprintf(buffer + n, size - n,
4993 "MT6359_AFE_VOW_PERIODIC_CFG31 = 0x%x\n", value);
4994 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG32, &value);
4995 n += scnprintf(buffer + n, size - n,
4996 "MT6359_AFE_VOW_PERIODIC_CFG32 = 0x%x\n", value);
4997 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG33, &value);
4998 n += scnprintf(buffer + n, size - n,
4999 "MT6359_AFE_VOW_PERIODIC_CFG33 = 0x%x\n", value);
5000 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG34, &value);
5001 n += scnprintf(buffer + n, size - n,
5002 "MT6359_AFE_VOW_PERIODIC_CFG34 = 0x%x\n", value);
5003 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG35, &value);
5004 n += scnprintf(buffer + n, size - n,
5005 "MT6359_AFE_VOW_PERIODIC_CFG35 = 0x%x\n", value);
5006 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG36, &value);
5007 n += scnprintf(buffer + n, size - n,
5008 "MT6359_AFE_VOW_PERIODIC_CFG36 = 0x%x\n", value);
5009 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG37, &value);
5010 n += scnprintf(buffer + n, size - n,
5011 "MT6359_AFE_VOW_PERIODIC_CFG37 = 0x%x\n", value);
5012 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG38, &value);
5013 n += scnprintf(buffer + n, size - n,
5014 "MT6359_AFE_VOW_PERIODIC_CFG38 = 0x%x\n", value);
5015 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_CFG39, &value);
5016 n += scnprintf(buffer + n, size - n,
5017 "MT6359_AFE_VOW_PERIODIC_CFG39 = 0x%x\n", value);
5018 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_MON0, &value);
5019 n += scnprintf(buffer + n, size - n,
5020 "MT6359_AFE_VOW_PERIODIC_MON0 = 0x%x\n", value);
5021 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_MON1, &value);
5022 n += scnprintf(buffer + n, size - n,
5023 "MT6359_AFE_VOW_PERIODIC_MON1 = 0x%x\n", value);
5024 regmap_read(priv->regmap, MT6359_AFE_VOW_PERIODIC_MON2, &value);
5025 n += scnprintf(buffer + n, size - n,
5026 "MT6359_AFE_VOW_PERIODIC_MON2 = 0x%x\n", value);
5027 regmap_read(priv->regmap, MT6359_AFE_NCP_CFG0, &value);
5028 n += scnprintf(buffer + n, size - n,
5029 "MT6359_AFE_NCP_CFG0 = 0x%x\n", value);
5030 regmap_read(priv->regmap, MT6359_AFE_NCP_CFG1, &value);
5031 n += scnprintf(buffer + n, size - n,
5032 "MT6359_AFE_NCP_CFG1 = 0x%x\n", value);
5033 regmap_read(priv->regmap, MT6359_AFE_NCP_CFG2, &value);
5034 n += scnprintf(buffer + n, size - n,
5035 "MT6359_AFE_NCP_CFG2 = 0x%x\n", value);
5036 regmap_read(priv->regmap, MT6359_AUDENC_DSN_ID, &value);
5037 n += scnprintf(buffer + n, size - n,
5038 "MT6359_AUDENC_DSN_ID = 0x%x\n", value);
5039 regmap_read(priv->regmap, MT6359_AUDENC_DSN_REV0, &value);
5040 n += scnprintf(buffer + n, size - n,
5041 "MT6359_AUDENC_DSN_REV0 = 0x%x\n", value);
5042 regmap_read(priv->regmap, MT6359_AUDENC_DSN_DBI, &value);
5043 n += scnprintf(buffer + n, size - n,
5044 "MT6359_AUDENC_DSN_DBI = 0x%x\n", value);
5045 regmap_read(priv->regmap, MT6359_AUDENC_DSN_FPI, &value);
5046 n += scnprintf(buffer + n, size - n,
5047 "MT6359_AUDENC_DSN_FPI = 0x%x\n", value);
5048 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON0, &value);
5049 n += scnprintf(buffer + n, size - n,
5050 "MT6359_AUDENC_ANA_CON0 = 0x%x\n", value);
5051 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON1, &value);
5052 n += scnprintf(buffer + n, size - n,
5053 "MT6359_AUDENC_ANA_CON1 = 0x%x\n", value);
5054 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON2, &value);
5055 n += scnprintf(buffer + n, size - n,
5056 "MT6359_AUDENC_ANA_CON2 = 0x%x\n", value);
5057 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON3, &value);
5058 n += scnprintf(buffer + n, size - n,
5059 "MT6359_AUDENC_ANA_CON3 = 0x%x\n", value);
5060 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON4, &value);
5061 n += scnprintf(buffer + n, size - n,
5062 "MT6359_AUDENC_ANA_CON4 = 0x%x\n", value);
5063 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON5, &value);
5064 n += scnprintf(buffer + n, size - n,
5065 "MT6359_AUDENC_ANA_CON5 = 0x%x\n", value);
5066 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON6, &value);
5067 n += scnprintf(buffer + n, size - n,
5068 "MT6359_AUDENC_ANA_CON6 = 0x%x\n", value);
5069 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON7, &value);
5070 n += scnprintf(buffer + n, size - n,
5071 "MT6359_AUDENC_ANA_CON7 = 0x%x\n", value);
5072 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON8, &value);
5073 n += scnprintf(buffer + n, size - n,
5074 "MT6359_AUDENC_ANA_CON8 = 0x%x\n", value);
5075 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON9, &value);
5076 n += scnprintf(buffer + n, size - n,
5077 "MT6359_AUDENC_ANA_CON9 = 0x%x\n", value);
5078 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON10, &value);
5079 n += scnprintf(buffer + n, size - n,
5080 "MT6359_AUDENC_ANA_CON10 = 0x%x\n", value);
5081 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON11, &value);
5082 n += scnprintf(buffer + n, size - n,
5083 "MT6359_AUDENC_ANA_CON11 = 0x%x\n", value);
5084 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON12, &value);
5085 n += scnprintf(buffer + n, size - n,
5086 "MT6359_AUDENC_ANA_CON12 = 0x%x\n", value);
5087 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON13, &value);
5088 n += scnprintf(buffer + n, size - n,
5089 "MT6359_AUDENC_ANA_CON13 = 0x%x\n", value);
5090 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON14, &value);
5091 n += scnprintf(buffer + n, size - n,
5092 "MT6359_AUDENC_ANA_CON14 = 0x%x\n", value);
5093 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON15, &value);
5094 n += scnprintf(buffer + n, size - n,
5095 "MT6359_AUDENC_ANA_CON15 = 0x%x\n", value);
5096 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON16, &value);
5097 n += scnprintf(buffer + n, size - n,
5098 "MT6359_AUDENC_ANA_CON16 = 0x%x\n", value);
5099 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON17, &value);
5100 n += scnprintf(buffer + n, size - n,
5101 "MT6359_AUDENC_ANA_CON17 = 0x%x\n", value);
5102 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON18, &value);
5103 n += scnprintf(buffer + n, size - n,
5104 "MT6359_AUDENC_ANA_CON18 = 0x%x\n", value);
5105 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON19, &value);
5106 n += scnprintf(buffer + n, size - n,
5107 "MT6359_AUDENC_ANA_CON19 = 0x%x\n", value);
5108 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON20, &value);
5109 n += scnprintf(buffer + n, size - n,
5110 "MT6359_AUDENC_ANA_CON20 = 0x%x\n", value);
5111 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON21, &value);
5112 n += scnprintf(buffer + n, size - n,
5113 "MT6359_AUDENC_ANA_CON21 = 0x%x\n", value);
5114 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON22, &value);
5115 n += scnprintf(buffer + n, size - n,
5116 "MT6359_AUDENC_ANA_CON22 = 0x%x\n", value);
5117 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON23, &value);
5118 n += scnprintf(buffer + n, size - n,
5119 "MT6359_AUDENC_ANA_CON23 = 0x%x\n", value);
5120 regmap_read(priv->regmap, MT6359_AUDDEC_DSN_ID, &value);
5121 n += scnprintf(buffer + n, size - n,
5122 "MT6359_AUDDEC_DSN_ID = 0x%x\n", value);
5123 regmap_read(priv->regmap, MT6359_AUDDEC_DSN_REV0, &value);
5124 n += scnprintf(buffer + n, size - n,
5125 "MT6359_AUDDEC_DSN_REV0 = 0x%x\n", value);
5126 regmap_read(priv->regmap, MT6359_AUDDEC_DSN_DBI, &value);
5127 n += scnprintf(buffer + n, size - n,
5128 "MT6359_AUDDEC_DSN_DBI = 0x%x\n", value);
5129 regmap_read(priv->regmap, MT6359_AUDDEC_DSN_FPI, &value);
5130 n += scnprintf(buffer + n, size - n,
5131 "MT6359_AUDDEC_DSN_FPI = 0x%x\n", value);
5132 regmap_read(priv->regmap, MT6359_AUDDEC_ANA_CON0, &value);
5133 n += scnprintf(buffer + n, size - n,
5134 "MT6359_AUDDEC_ANA_CON0 = 0x%x\n", value);
5135 regmap_read(priv->regmap, MT6359_AUDDEC_ANA_CON1, &value);
5136 n += scnprintf(buffer + n, size - n,
5137 "MT6359_AUDDEC_ANA_CON1 = 0x%x\n", value);
5138 regmap_read(priv->regmap, MT6359_AUDDEC_ANA_CON2, &value);
5139 n += scnprintf(buffer + n, size - n,
5140 "MT6359_AUDDEC_ANA_CON2 = 0x%x\n", value);
5141 regmap_read(priv->regmap, MT6359_AUDDEC_ANA_CON3, &value);
5142 n += scnprintf(buffer + n, size - n,
5143 "MT6359_AUDDEC_ANA_CON3 = 0x%x\n", value);
5144 regmap_read(priv->regmap, MT6359_AUDDEC_ANA_CON4, &value);
5145 n += scnprintf(buffer + n, size - n,
5146 "MT6359_AUDDEC_ANA_CON4 = 0x%x\n", value);
5147 regmap_read(priv->regmap, MT6359_AUDDEC_ANA_CON5, &value);
5148 n += scnprintf(buffer + n, size - n,
5149 "MT6359_AUDDEC_ANA_CON5 = 0x%x\n", value);
5150 regmap_read(priv->regmap, MT6359_AUDDEC_ANA_CON6, &value);
5151 n += scnprintf(buffer + n, size - n,
5152 "MT6359_AUDDEC_ANA_CON6 = 0x%x\n", value);
5153 regmap_read(priv->regmap, MT6359_AUDDEC_ANA_CON7, &value);
5154 n += scnprintf(buffer + n, size - n,
5155 "MT6359_AUDDEC_ANA_CON7 = 0x%x\n", value);
5156 regmap_read(priv->regmap, MT6359_AUDDEC_ANA_CON8, &value);
5157 n += scnprintf(buffer + n, size - n,
5158 "MT6359_AUDDEC_ANA_CON8 = 0x%x\n", value);
5159 regmap_read(priv->regmap, MT6359_AUDDEC_ANA_CON9, &value);
5160 n += scnprintf(buffer + n, size - n,
5161 "MT6359_AUDDEC_ANA_CON9 = 0x%x\n", value);
5162 regmap_read(priv->regmap, MT6359_AUDDEC_ANA_CON10, &value);
5163 n += scnprintf(buffer + n, size - n,
5164 "MT6359_AUDDEC_ANA_CON10 = 0x%x\n", value);
5165 regmap_read(priv->regmap, MT6359_AUDDEC_ANA_CON11, &value);
5166 n += scnprintf(buffer + n, size - n,
5167 "MT6359_AUDDEC_ANA_CON11 = 0x%x\n", value);
5168 regmap_read(priv->regmap, MT6359_AUDDEC_ANA_CON12, &value);
5169 n += scnprintf(buffer + n, size - n,
5170 "MT6359_AUDDEC_ANA_CON12 = 0x%x\n", value);
5171 regmap_read(priv->regmap, MT6359_AUDDEC_ANA_CON13, &value);
5172 n += scnprintf(buffer + n, size - n,
5173 "MT6359_AUDDEC_ANA_CON13 = 0x%x\n", value);
5174 regmap_read(priv->regmap, MT6359_AUDDEC_ANA_CON14, &value);
5175 n += scnprintf(buffer + n, size - n,
5176 "MT6359_AUDDEC_ANA_CON14 = 0x%x\n", value);
5177 regmap_read(priv->regmap, MT6359_AUDZCD_DSN_ID, &value);
5178 n += scnprintf(buffer + n, size - n,
5179 "MT6359_AUDZCD_DSN_ID = 0x%x\n", value);
5180 regmap_read(priv->regmap, MT6359_AUDZCD_DSN_REV0, &value);
5181 n += scnprintf(buffer + n, size - n,
5182 "MT6359_AUDZCD_DSN_REV0 = 0x%x\n", value);
5183 regmap_read(priv->regmap, MT6359_AUDZCD_DSN_DBI, &value);
5184 n += scnprintf(buffer + n, size - n,
5185 "MT6359_AUDZCD_DSN_DBI = 0x%x\n", value);
5186 regmap_read(priv->regmap, MT6359_AUDZCD_DSN_FPI, &value);
5187 n += scnprintf(buffer + n, size - n,
5188 "MT6359_AUDZCD_DSN_FPI = 0x%x\n", value);
5189 regmap_read(priv->regmap, MT6359_ZCD_CON0, &value);
5190 n += scnprintf(buffer + n, size - n,
5191 "MT6359_ZCD_CON0 = 0x%x\n", value);
5192 regmap_read(priv->regmap, MT6359_ZCD_CON1, &value);
5193 n += scnprintf(buffer + n, size - n,
5194 "MT6359_ZCD_CON1 = 0x%x\n", value);
5195 regmap_read(priv->regmap, MT6359_ZCD_CON2, &value);
5196 n += scnprintf(buffer + n, size - n,
5197 "MT6359_ZCD_CON2 = 0x%x\n", value);
5198 regmap_read(priv->regmap, MT6359_ZCD_CON3, &value);
5199 n += scnprintf(buffer + n, size - n,
5200 "MT6359_ZCD_CON3 = 0x%x\n", value);
5201 regmap_read(priv->regmap, MT6359_ZCD_CON4, &value);
5202 n += scnprintf(buffer + n, size - n,
5203 "MT6359_ZCD_CON4 = 0x%x\n", value);
5204 regmap_read(priv->regmap, MT6359_ZCD_CON5, &value);
5205 n += scnprintf(buffer + n, size - n,
5206 "MT6359_ZCD_CON5 = 0x%x\n", value);
5207
5208 ret = simple_read_from_buffer(buf, count, pos, buffer, n);
5209 kfree(buffer);
5210 return ret;
5211}
5212
5213static ssize_t mt6359_debugfs_write(struct file *f, const char __user *buf,
5214 size_t count, loff_t *offset)
5215{
5216#define MAX_DEBUG_WRITE_INPUT 256
5217 struct mt6359_priv *priv = f->private_data;
5218 char input[MAX_DEBUG_WRITE_INPUT];
5219 char *temp = NULL;
5220 char *command = NULL;
5221 char *str_begin = NULL;
5222 char delim[] = " ,";
5223 const struct command_function *cf;
5224
5225 if (!count) {
5226 dev_info(priv->dev, "%s(), count is 0, return directly\n",
5227 __func__);
5228 goto exit;
5229 }
5230
5231 if (count > MAX_DEBUG_WRITE_INPUT)
5232 count = MAX_DEBUG_WRITE_INPUT;
5233
5234 memset((void *)input, 0, MAX_DEBUG_WRITE_INPUT);
5235
5236 if (copy_from_user(input, buf, count))
5237 dev_warn(priv->dev, "%s(), copy_from_user fail, count = %zu\n",
5238 __func__, count);
5239
5240 str_begin = kstrndup(input, MAX_DEBUG_WRITE_INPUT - 1,
5241 GFP_KERNEL);
5242 if (!str_begin) {
5243 dev_info(priv->dev, "%s(), kstrdup fail\n", __func__);
5244 goto exit;
5245 }
5246 temp = str_begin;
5247
5248 command = strsep(&temp, delim);
5249
5250 dev_info(priv->dev, "%s(), command %s, content %s\n",
5251 __func__, command, temp);
5252
5253 for (cf = debug_cmds; cf->cmd; cf++) {
5254 if (strcmp(cf->cmd, command) == 0) {
5255 cf->fn(f, temp);
5256 break;
5257 }
5258 }
5259
5260 kfree(str_begin);
5261exit:
5262 return count;
5263}
5264
5265static const struct file_operations mt6359_debugfs_ops = {
5266 .open = mt6359_debugfs_open,
5267 .write = mt6359_debugfs_write,
5268 .read = mt6359_debugfs_read,
5269};
5270
5271static int mt6359_platform_driver_probe(struct platform_device *pdev)
5272{
5273 struct mt6359_priv *priv;
5274 int ret;
5275 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
5276
5277 priv = devm_kzalloc(&pdev->dev,
5278 sizeof(struct mt6359_priv),
5279 GFP_KERNEL);
5280 if (!priv)
5281 return -ENOMEM;
5282
5283 priv->regmap = mt6397->regmap;
5284 if (IS_ERR(priv->regmap))
5285 return PTR_ERR(priv->regmap);
5286
5287 dev_set_drvdata(&pdev->dev, priv);
5288 priv->dev = &pdev->dev;
5289
5290 /* create debugfs file */
5291 priv->debugfs = debugfs_create_file("mtksocanaaudio",
5292 S_IFREG | 0444, NULL,
5293 priv, &mt6359_debugfs_ops);
5294
5295 dev_info(&pdev->dev, "%s(), dev name %s\n",
5296 __func__, dev_name(&pdev->dev));
5297
5298 ret = devm_snd_soc_register_component(&pdev->dev,
5299 &mt6359_soc_component_driver,
5300 mt6359_dai_driver,
5301 ARRAY_SIZE(mt6359_dai_driver));
5302
5303 dev_info(&pdev->dev, "%s(), ret = %d\n", __func__, ret);
5304 return ret;
5305}
5306
5307static const struct of_device_id mt6359_of_match[] = {
5308 {.compatible = "mediatek,mt6359-sound",},
5309 {}
5310};
5311MODULE_DEVICE_TABLE(of, mt6359_of_match);
5312
5313static struct platform_driver mt6359_platform_driver = {
5314 .driver = {
5315 .name = "mt6359-sound",
5316 .of_match_table = mt6359_of_match,
5317 },
5318 .probe = mt6359_platform_driver_probe,
5319};
5320
5321module_platform_driver(mt6359_platform_driver)
5322
5323/* Module information */
5324MODULE_DESCRIPTION("MT6359 ALSA SoC codec driver");
5325MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
5326MODULE_LICENSE("GPL v2");