| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * sleep mode for CSR SiRFprimaII |
| 3 | * |
| 4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. |
| 5 | * |
| 6 | * Licensed under GPLv2 or later. |
| 7 | */ |
| 8 | |
| 9 | #include <linux/linkage.h> |
| 10 | #include <asm/ptrace.h> |
| 11 | #include <asm/assembler.h> |
| 12 | |
| 13 | #include "pm.h" |
| 14 | |
| 15 | #define DENALI_CTL_22_OFF 0x58 |
| 16 | #define DENALI_CTL_112_OFF 0x1c0 |
| 17 | |
| 18 | .text |
| 19 | |
| 20 | ENTRY(sirfsoc_finish_suspend) |
| 21 | @ r5: mem controller |
| 22 | ldr r0, =sirfsoc_memc_base |
| 23 | ldr r5, [r0] |
| 24 | @ r6: pwrc base offset |
| 25 | ldr r0, =sirfsoc_pwrc_base |
| 26 | ldr r6, [r0] |
| 27 | @ r7: rtc iobrg controller |
| 28 | ldr r0, =sirfsoc_rtciobrg_base |
| 29 | ldr r7, [r0] |
| 30 | |
| 31 | @ Read the power control register and set the |
| 32 | @ sleep force bit. |
| 33 | add r0, r6, #SIRFSOC_PWRC_PDN_CTRL |
| 34 | bl __sirfsoc_rtc_iobrg_readl |
| 35 | orr r0,r0,#SIRFSOC_PWR_SLEEPFORCE |
| 36 | add r1, r6, #SIRFSOC_PWRC_PDN_CTRL |
| 37 | bl sirfsoc_rtc_iobrg_pre_writel |
| 38 | mov r1, #0x1 |
| 39 | |
| 40 | @ read the MEM ctl register and set the self |
| 41 | @ refresh bit |
| 42 | |
| 43 | ldr r2, [r5, #DENALI_CTL_22_OFF] |
| 44 | orr r2, r2, #0x1 |
| 45 | |
| 46 | @ Following code has to run from cache since |
| 47 | @ the RAM is going to self refresh mode |
| 48 | .align 5 |
| 49 | str r2, [r5, #DENALI_CTL_22_OFF] |
| 50 | |
| 51 | 1: |
| 52 | ldr r4, [r5, #DENALI_CTL_112_OFF] |
| 53 | tst r4, #0x1 |
| 54 | bne 1b |
| 55 | |
| 56 | @ write SLEEPFORCE through rtc iobridge |
| 57 | |
| 58 | str r1, [r7] |
| 59 | @ wait rtc io bridge sync |
| 60 | 1: |
| 61 | ldr r3, [r7] |
| 62 | tst r3, #0x01 |
| 63 | bne 1b |
| 64 | b . |