blob: f9e589e67ddcbdcf7221cb640cd28b8a139ee678 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9
10#include "clk-mtk.h"
11#include "clk-gate.h"
12
13#include <dt-bindings/clock/mt6779-clk.h>
14
15static const struct mtk_gate_regs mfg_cg_regs = {
16 .set_ofs = 0x4,
17 .clr_ofs = 0x8,
18 .sta_ofs = 0x0,
19};
20
21#define GATE_MFG(_id, _name, _parent, _shift) { \
22 .id = _id, \
23 .name = _name, \
24 .parent_name = _parent, \
25 .regs = &mfg_cg_regs, \
26 .shift = _shift, \
27 .ops = &mtk_clk_gate_ops_setclr, \
28 }
29
30static const struct mtk_gate mfg_clks[] = {
31 GATE_MFG(CLK_MFGCFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
32};
33
34static int clk_mt6779_mfg_probe(struct platform_device *pdev)
35{
36 struct clk_onecell_data *clk_data;
37 struct device_node *node = pdev->dev.of_node;
38
39 clk_data = mtk_alloc_clk_data(CLK_MFGCFG_NR_CLK);
40
41 mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
42 clk_data);
43
44 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
45}
46
47static const struct of_device_id of_match_clk_mt6779_mfg[] = {
48 { .compatible = "mediatek,mt6779-mfgcfg", },
49 {}
50};
51
52static struct platform_driver clk_mt6779_mfg_drv = {
53 .probe = clk_mt6779_mfg_probe,
54 .driver = {
55 .name = "clk-mt6779-mfg",
56 .of_match_table = of_match_clk_mt6779_mfg,
57 },
58};
59
60builtin_platform_driver(clk_mt6779_mfg_drv);