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192.168.1.100 / T800 / 15d4438f3c457b15d5b7f076bba313638bae4402 / . / src / kernel / linux / v4.19 / drivers / clk / mediatek / clk-mt6779.c
blob: fbd07525ea419bccc1d49d3a7f404a8841d2cc6a [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/of.h>
8#include <linux/of_address.h>
9#include <linux/of_device.h>
10#include <linux/platform_device.h>
11
12#include "clk-mtk.h"
13#include "clk-mux.h"
14#include "clk-gate.h"
15
16#include <dt-bindings/clock/mt6779-clk.h>
17
18static DEFINE_SPINLOCK(mt6779_clk_lock);
19
20static const struct mtk_fixed_clk top_fixed_clks[] = {
21 FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
22};
23
24static const struct mtk_fixed_factor top_divs[] = {
25 FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1,
26 2),
27 FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1,
28 2),
29 FACTOR(CLK_TOP_MAINPLL_CK, "mainpll_ck", "mainpll", 1,
30 1),
31 FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll_ck", 1,
32 2),
33 FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1,
34 2),
35 FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1,
36 4),
37 FACTOR(CLK_TOP_MAINPLL_D2_D8, "mainpll_d2_d8", "mainpll_d2", 1,
38 8),
39 FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1,
40 16),
41
42 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1,
43 3),
44 FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1,
45 2),
46 FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1,
47 4),
48 FACTOR(CLK_TOP_MAINPLL_D3_D8, "mainpll_d3_d8", "mainpll_d3", 1,
49 8),
50
51 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1,
52 5),
53 FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1,
54 2),
55 FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1,
56 4),
57
58 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1,
59 7),
60 FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1,
61 2),
62 FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1,
63 4),
64
65 FACTOR(CLK_TOP_UNIVPLL_CK, "univpll", "univ2pll", 1,
66 2),
67 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1,
68 2),
69 FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1,
70 2),
71 FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1,
72 4),
73 FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1,
74 8),
75
76
77 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1,
78 3),
79 FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1,
80 2),
81 FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1,
82 4),
83 FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1,
84 8),
85 FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1,
86 16),
87
88 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1,
89 5),
90 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1,
91 2),
92 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1,
93 4),
94 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1,
95 8),
96
97 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1,
98 7),
99
100 FACTOR(CLK_TOP_UNIVP_192M_CK, "univpll_192m_ck", "univ2pll", 1,
101 13),
102 FACTOR(CLK_TOP_UNIVP_192M_D2, "univpll_192m_d2", "univpll_192m_ck", 1,
103 2),
104 FACTOR(CLK_TOP_UNIVP_192M_D4, "univpll_192m_d4", "univpll_192m_ck", 1,
105 4),
106 FACTOR(CLK_TOP_UNIVP_192M_D8, "univpll_192m_d8", "univpll_192m_ck", 1,
107 8),
108 FACTOR(CLK_TOP_UNIVP_192M_D16, "univpll_192m_d16", "univpll_192m_ck", 1,
109 16),
110 FACTOR(CLK_TOP_UNIVP_192M_D32, "univpll_192m_d32", "univpll_192m_ck", 1,
111 32),
112
113 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1,
114 1),
115 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1,
116 2),
117 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1,
118 4),
119 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1,
120 8),
121 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1,
122 1),
123 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1,
124 2),
125 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1,
126 4),
127 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1,
128 8),
129 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1,
130 1),
131 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
132 2),
133 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1,
134 4),
135 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1,
136 8),
137 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1,
138 16),
139
140 FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1,
141 1),
142 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1,
143 4),
144 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1,
145 2),
146 FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1,
147 4),
148 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1,
149 5),
150 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1,
151 2),
152 FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1,
153 4),
154 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1,
155 6),
156 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1,
157 7),
158
159 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1,
160 1),
161 FACTOR(CLK_TOP_ADSPPLL_CK, "adsppll_ck", "adsppll", 1,
162 1),
163 FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1,
164 4),
165 FACTOR(CLK_TOP_ADSPPLL_D5, "adsppll_d5", "adsppll", 1,
166 5),
167 FACTOR(CLK_TOP_ADSPPLL_D6, "adsppll_d6", "adsppll", 1,
168 6),
169
170 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1,
171 1),
172 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1,
173 2),
174 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1,
175 4),
176 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1,
177 8),
178 FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1,
179 16),
180 FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1,
181 1),
182 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1,
183 2),
184 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1,
185 4),
186 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1,
187 8),
188 FACTOR(CLK_TOP_OSC_D10, "osc_d10", "osc", 1,
189 10),
190 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1,
191 16),
192 FACTOR(CLK_TOP_AD_OSC2_CK, "ad_osc2_ck", "osc2", 1,
193 1),
194 FACTOR(CLK_TOP_OSC2_D2, "osc2_d2", "osc2", 1,
195 2),
196 FACTOR(CLK_TOP_OSC2_D3, "osc2_d3", "osc2", 1,
197 3),
198
199 FACTOR(CLK_TOP_TVDPLL_MAINPLL_D2_CK, "tvdpll_mainpll_d2_ck",
200 "tvdpll", 1, 1),
201
202 FACTOR(CLK_TOP_FMEM_466M_CK, "fmem_466m_ck", "fmem", 1,
203 1),
204};
205
206static const char * const axi_parents[] = {
207 "clk26m",
208 "mainpll_d2_d4",
209 "mainpll_d7",
210 "osc_d4"
211};
212
213static const char * const mm_parents[] = {
214 "clk26m",
215 "tvdpll_mainpll_d2_ck",
216 "mmpll_d7",
217 "mmpll_d5_d2",
218 "mainpll_d2_d2",
219 "mainpll_d3_d2"
220};
221
222static const char * const scp_parents[] = {
223 "clk26m",
224 "univpll_d2_d8",
225 "mainpll_d2_d4",
226 "mainpll_d3",
227 "univpll_d3",
228 "ad_osc2_ck",
229 "osc2_d2",
230 "osc2_d3"
231};
232
233static const char * const img_parents[] = {
234 "clk26m",
235 "mainpll_d2",
236 "mainpll_d2",
237 "univpll_d3",
238 "mainpll_d3",
239 "mmpll_d5_d2",
240 "tvdpll_mainpll_d2_ck",
241 "mainpll_d5"
242};
243
244static const char * const ipe_parents[] = {
245 "clk26m",
246 "mainpll_d2",
247 "mmpll_d7",
248 "univpll_d3",
249 "mainpll_d3",
250 "mmpll_d5_d2",
251 "mainpll_d2_d2",
252 "mainpll_d5"
253};
254
255static const char * const dpe_parents[] = {
256 "clk26m",
257 "mainpll_d2",
258 "mmpll_d7",
259 "univpll_d3",
260 "mainpll_d3",
261 "mmpll_d5_d2",
262 "mainpll_d2_d2",
263 "mainpll_d5"
264};
265
266static const char * const cam_parents[] = {
267 "clk26m",
268 "mainpll_d2",
269 "mmpll_d6",
270 "mainpll_d3",
271 "mmpll_d7",
272 "univpll_d3",
273 "mmpll_d5_d2",
274 "adsppll_d5",
275 "tvdpll_mainpll_d2_ck",
276 "univpll_d3_d2"
277};
278
279static const char * const ccu_parents[] = {
280 "clk26m",
281 "mainpll_d2",
282 "mmpll_d6",
283 "mainpll_d3",
284 "mmpll_d7",
285 "univpll_d3",
286 "mmpll_d5_d2",
287 "mainpll_d2_d2",
288 "adsppll_d5",
289 "univpll_d3_d2"
290};
291
292static const char * const dsp_parents[] = {
293 "clk26m",
294 "univpll_d3_d8",
295 "univpll_d3_d4",
296 "mainpll_d2_d4",
297 "univpll_d3_d2",
298 "mainpll_d2_d2",
299 "univpll_d2_d2",
300 "mainpll_d3",
301 "univpll_d3",
302 "mmpll_d7",
303 "mmpll_d6",
304 "adsppll_d5",
305 "tvdpll_ck",
306 "tvdpll_mainpll_d2_ck",
307 "univpll_d2",
308 "adsppll_d4"
309};
310
311static const char * const dsp1_parents[] = {
312 "clk26m",
313 "univpll_d3_d8",
314 "univpll_d3_d4",
315 "mainpll_d2_d4",
316 "univpll_d3_d2",
317 "mainpll_d2_d2",
318 "univpll_d2_d2",
319 "mainpll_d3",
320 "univpll_d3",
321 "mmpll_d7",
322 "mmpll_d6",
323 "adsppll_d5",
324 "tvdpll_ck",
325 "tvdpll_mainpll_d2_ck",
326 "univpll_d2",
327 "adsppll_d4"
328};
329
330static const char * const dsp2_parents[] = {
331 "clk26m",
332 "univpll_d3_d8",
333 "univpll_d3_d4",
334 "mainpll_d2_d4",
335 "univpll_d3_d2",
336 "mainpll_d2_d2",
337 "univpll_d2_d2",
338 "mainpll_d3",
339 "univpll_d3",
340 "mmpll_d7",
341 "mmpll_d6",
342 "adsppll_d5",
343 "tvdpll_ck",
344 "tvdpll_mainpll_d2_ck",
345 "univpll_d2",
346 "adsppll_d4"
347};
348
349static const char * const dsp3_parents[] = {
350 "clk26m",
351 "univpll_d3_d8",
352 "mainpll_d2_d4",
353 "univpll_d3_d2",
354 "mainpll_d2_d2",
355 "univpll_d2_d2",
356 "mainpll_d3",
357 "univpll_d3",
358 "mmpll_d7",
359 "mmpll_d6",
360 "mainpll_d2",
361 "tvdpll_ck",
362 "tvdpll_mainpll_d2_ck",
363 "univpll_d2",
364 "adsppll_d4",
365 "mmpll_d4"
366};
367
368static const char * const ipu_if_parents[] = {
369 "clk26m",
370 "univpll_d3_d8",
371 "univpll_d3_d4",
372 "mainpll_d2_d4",
373 "univpll_d3_d2",
374 "mainpll_d2_d2",
375 "univpll_d2_d2",
376 "mainpll_d3",
377 "univpll_d3",
378 "mmpll_d7",
379 "mmpll_d6",
380 "adsppll_d5",
381 "tvdpll_ck",
382 "tvdpll_mainpll_d2_ck",
383 "univpll_d2",
384 "adsppll_d4"
385};
386
387static const char * const mfg_parents[] = {
388 "clk26m",
389 "mfgpll_ck",
390 "univpll_d3",
391 "mainpll_d5"
392};
393
394static const char * const f52m_mfg_parents[] = {
395 "clk26m",
396 "univpll_d3_d2",
397 "univpll_d3_d4",
398 "univpll_d3_d8"
399};
400
401static const char * const camtg_parents[] = {
402 "clk26m",
403 "univpll_192m_d8",
404 "univpll_d3_d8",
405 "univpll_192m_d4",
406 "univpll_d3_d16",
407 "csw_f26m_ck_d2",
408 "univpll_192m_d16",
409 "univpll_192m_d32"
410};
411
412static const char * const camtg2_parents[] = {
413 "clk26m",
414 "univpll_192m_d8",
415 "univpll_d3_d8",
416 "univpll_192m_d4",
417 "univpll_d3_d16",
418 "csw_f26m_ck_d2",
419 "univpll_192m_d16",
420 "univpll_192m_d32"
421};
422
423static const char * const camtg3_parents[] = {
424 "clk26m",
425 "univpll_192m_d8",
426 "univpll_d3_d8",
427 "univpll_192m_d4",
428 "univpll_d3_d16",
429 "csw_f26m_ck_d2",
430 "univpll_192m_d16",
431 "univpll_192m_d32"
432};
433
434static const char * const camtg4_parents[] = {
435 "clk26m",
436 "univpll_192m_d8",
437 "univpll_d3_d8",
438 "univpll_192m_d4",
439 "univpll_d3_d16",
440 "csw_f26m_ck_d2",
441 "univpll_192m_d16",
442 "univpll_192m_d32"
443};
444
445static const char * const uart_parents[] = {
446 "clk26m",
447 "univpll_d3_d8"
448};
449
450static const char * const spi_parents[] = {
451 "clk26m",
452 "mainpll_d5_d2",
453 "mainpll_d3_d4",
454 "msdcpll_d4"
455};
456
457static const char * const msdc50_hclk_parents[] = {
458 "clk26m",
459 "mainpll_d2_d2",
460 "mainpll_d3_d2"
461};
462
463static const char * const msdc50_0_parents[] = {
464 "clk26m",
465 "msdcpll_ck",
466 "msdcpll_d2",
467 "univpll_d2_d4",
468 "mainpll_d3_d2",
469 "univpll_d2_d2"
470};
471
472static const char * const msdc30_1_parents[] = {
473 "clk26m",
474 "univpll_d3_d2",
475 "mainpll_d3_d2",
476 "mainpll_d7",
477 "msdcpll_d2"
478};
479
480static const char * const audio_parents[] = {
481 "clk26m",
482 "mainpll_d5_d4",
483 "mainpll_d7_d4",
484 "mainpll_d2_d16"
485};
486
487static const char * const aud_intbus_parents[] = {
488 "clk26m",
489 "mainpll_d2_d4",
490 "mainpll_d7_d2"
491};
492
493
494static const char * const fpwrap_ulposc_parents[] = {
495 "osc_d10",
496 "clk26m",
497 "osc_d4",
498 "osc_d8",
499 "osc_d16"
500};
501
502static const char * const atb_parents[] = {
503 "clk26m",
504 "mainpll_d2_d2",
505 "mainpll_d5"
506};
507
508static const char * const sspm_parents[] = {
509 "clk26m",
510 "univpll_d2_d4",
511 "mainpll_d2_d2",
512 "univpll_d2_d2",
513 "mainpll_d3"
514};
515
516static const char * const dpi0_parents[] = {
517 "clk26m",
518 "tvdpll_d2",
519 "tvdpll_d4",
520 "tvdpll_d8",
521 "tvdpll_d16"
522};
523
524static const char * const scam_parents[] = {
525 "clk26m",
526 "mainpll_d5_d2"
527};
528
529static const char * const disppwm_parents[] = {
530 "clk26m",
531 "univpll_d3_d4",
532 "osc_d2",
533 "osc_d4",
534 "osc_d16"
535};
536
537static const char * const usb_top_parents[] = {
538 "clk26m",
539 "univpll_d5_d4",
540 "univpll_d3_d4",
541 "univpll_d5_d2"
542};
543
544
545static const char * const ssusb_top_xhci_parents[] = {
546 "clk26m",
547 "univpll_d5_d4",
548 "univpll_d3_d4",
549 "univpll_d5_d2"
550};
551
552static const char * const spm_parents[] = {
553 "clk26m",
554 "osc_d8",
555 "mainpll_d2_d8"
556};
557
558static const char * const i2c_parents[] = {
559 "clk26m",
560 "mainpll_d2_d8",
561 "univpll_d5_d2"
562};
563
564static const char * const seninf_parents[] = {
565 "clk26m",
566 "univpll_d7",
567 "univpll_d3_d2",
568 "univpll_d2_d2",
569 "mainpll_d3",
570 "mmpll_d4_d2",
571 "mmpll_d7",
572 "mmpll_d6"
573};
574
575static const char * const seninf1_parents[] = {
576 "clk26m",
577 "univpll_d7",
578 "univpll_d3_d2",
579 "univpll_d2_d2",
580 "mainpll_d3",
581 "mmpll_d4_d2",
582 "mmpll_d7",
583 "mmpll_d6"
584};
585
586static const char * const seninf2_parents[] = {
587 "clk26m",
588 "univpll_d7",
589 "univpll_d3_d2",
590 "univpll_d2_d2",
591 "mainpll_d3",
592 "mmpll_d4_d2",
593 "mmpll_d7",
594 "mmpll_d6"
595};
596
597static const char * const dxcc_parents[] = {
598 "clk26m",
599 "mainpll_d2_d2",
600 "mainpll_d2_d4",
601 "mainpll_d2_d8"
602};
603
604static const char * const aud_engen1_parents[] = {
605 "clk26m",
606 "apll1_d2",
607 "apll1_d4",
608 "apll1_d8"
609};
610
611static const char * const aud_engen2_parents[] = {
612 "clk26m",
613 "apll2_d2",
614 "apll2_d4",
615 "apll2_d8"
616};
617
618static const char * const faes_ufsfde_parents[] = {
619 "clk26m",
620 "mainpll_d2",
621 "mainpll_d2_d2",
622 "mainpll_d3",
623 "mainpll_d2_d4",
624 "univpll_d3"
625};
626
627static const char * const fufs_parents[] = {
628 "clk26m",
629 "mainpll_d2_d4",
630 "mainpll_d2_d8",
631 "mainpll_d2_d16"
632};
633
634static const char * const aud_1_parents[] = {
635 "clk26m",
636 "apll1_ck"
637};
638
639static const char * const aud_2_parents[] = {
640 "clk26m",
641 "apll2_ck"
642};
643
644static const char * const adsp_parents[] = {
645 "clk26m",
646 "mainpll_d3",
647 "univpll_d2_d4",
648 "univpll_d2",
649 "mmpll_d4",
650 "adsppll_d4",
651 "adsppll_d6"
652};
653
654static const char * const dpmaif_parents[] = {
655 "clk26m",
656 "univpll_d2_d4",
657 "mainpll_d3",
658 "mainpll_d2_d2",
659 "univpll_d2_d2",
660 "univpll_d3"
661};
662
663static const char * const venc_parents[] = {
664 "clk26m",
665 "mmpll_d7",
666 "mainpll_d3",
667 "univpll_d2_d2",
668 "mainpll_d2_d2",
669 "univpll_d3",
670 "mmpll_d6",
671 "mainpll_d5",
672 "mainpll_d3_d2",
673 "mmpll_d4_d2",
674 "univpll_d2_d4",
675 "mmpll_d5",
676 "univpll_192m_d2"
677
678};
679
680static const char * const vdec_parents[] = {
681 "clk26m",
682 "univpll_d2_d4",
683 "mainpll_d3",
684 "univpll_d2_d2",
685 "mainpll_d2_d2",
686 "univpll_d3",
687 "univpll_d5",
688 "univpll_d5_d2",
689 "mainpll_d2",
690 "univpll_d2",
691 "univpll_192m_d2"
692};
693
694static const char * const camtm_parents[] = {
695 "clk26m",
696 "univpll_d7",
697 "univpll_d3_d2",
698 "univpll_d2_d2"
699};
700
701static const char * const pwm_parents[] = {
702 "clk26m",
703 "univpll_d2_d8"
704};
705
706static const char * const audio_h_parents[] = {
707 "clk26m",
708 "univpll_d7",
709 "apll1_ck",
710 "apll2_ck"
711};
712
713static const char * const camtg5_parents[] = {
714 "clk26m",
715 "univpll_192m_d8",
716 "univpll_d3_d8",
717 "univpll_192m_d4",
718 "univpll_d3_d16",
719 "csw_f26m_ck_d2",
720 "univpll_192m_d16",
721 "univpll_192m_d32"
722};
723
724static const struct mtk_mux top_muxes[] = {
725 /* CLK_CFG_0 */
726 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "axi_sel", axi_parents,
727 0x20, 0x24, 0x28,
728 0, 2, 7,
729 0x004, 0, CLK_IS_CRITICAL),
730
731 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
732 0x20, 0x24, 0x28,
733 8, 3, 15,
734 0x004, 1),
735
736 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents,
737 0x20, 0x24, 0x28,
738 16, 3, 23,
739 0x004, 2),
740
741 /* CLK_CFG_1 */
742 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "img_sel", img_parents,
743 0x30, 0x34, 0x38,
744 0, 3, 7,
745 0x004, 4),
746
747 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "ipe_sel", ipe_parents,
748 0x30, 0x34, 0x38,
749 8, 3, 15,
750 0x004, 5),
751
752 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE, "dpe_sel", dpe_parents,
753 0x30, 0x34, 0x38,
754 16, 3, 23,
755 0x004, 6),
756
757 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "cam_sel", cam_parents,
758 0x30, 0x34, 0x38,
759 24, 4, 31,
760 0x004, 7),
761
762 /* CLK_CFG_2 */
763 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "ccu_sel", ccu_parents,
764 0x40, 0x44, 0x48,
765 0, 4, 7,
766 0x004, 8),
767
768 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "dsp_sel", dsp_parents,
769 0x40, 0x44, 0x48,
770 8, 4, 15,
771 0x004, 9),
772
773 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "dsp1_sel", dsp1_parents,
774 0x40, 0x44, 0x48,
775 16, 4, 23,
776 0x004, 10),
777
778 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "dsp2_sel", dsp2_parents,
779 0x40, 0x44, 0x48,
780 24, 4, 31,
781 0x004, 11),
782
783 /* CLK_CFG_3 */
784 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "dsp3_sel", dsp3_parents,
785 0x50, 0x54, 0x58,
786 0, 4, 7,
787 0x004, 12),
788
789 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "ipu_if_sel", ipu_if_parents,
790 0x50, 0x54, 0x58,
791 8, 4, 15,
792 0x004, 13),
793
794 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "mfg_sel", mfg_parents,
795 0x50, 0x54, 0x58,
796 16, 2, 23,
797 0x004, 14),
798
799 MUX_GATE_CLR_SET_UPD(CLK_TOP_F52M_MFG, "f52m_mfg_sel",
800 f52m_mfg_parents,
801 0x50, 0x54, 0x58,
802 24, 2, 31,
803 0x004, 15),
804
805 /* CLK_CFG_4 */
806 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "camtg_sel", camtg_parents,
807 0x60, 0x64, 0x68,
808 0, 3, 7,
809 0x004, 16),
810
811 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "camtg2_sel", camtg2_parents,
812 0x60, 0x64, 0x68,
813 8, 3, 15,
814 0x004, 17),
815
816 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "camtg3_sel", camtg3_parents,
817 0x60, 0x64, 0x68,
818 16, 3, 23,
819 0x004, 18),
820
821 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "camtg4_sel", camtg4_parents,
822 0x60, 0x64, 0x68,
823 24, 3, 31,
824 0x004, 19),
825
826 /* CLK_CFG_5 */
827 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents,
828 0x70, 0x74, 0x78,
829 0, 1, 7,
830 0x004, 20),
831
832 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents,
833 0x70, 0x74, 0x78,
834 8, 2, 15,
835 0x004, 21),
836
837 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",
838 msdc50_hclk_parents,
839 0x70, 0x74, 0x78,
840 16, 2, 23,
841 0x004, 22),
842
843 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel",
844 msdc50_0_parents,
845 0x70, 0x74, 0x78,
846 24, 3, 31,
847 0x004, 23),
848
849 /* CLK_CFG_6 */
850 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel",
851 msdc30_1_parents,
852 0x80, 0x84, 0x88,
853 0, 3, 7,
854 0x004, 24),
855
856 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents,
857 0x80, 0x84, 0x88,
858 8, 2, 15,
859 0x004, 25),
860
861 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel",
862 aud_intbus_parents,
863 0x80, 0x84, 0x88,
864 16, 2, 23,
865 0x004, 26),
866
867 MUX_GATE_CLR_SET_UPD(CLK_TOP_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
868 fpwrap_ulposc_parents,
869 0x80, 0x84, 0x88,
870 24, 3, 31,
871 0x004, 27),
872
873 /* CLK_CFG_7 */
874 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "atb_sel", atb_parents,
875 0x90, 0x94, 0x98,
876 0, 2, 7,
877 0x004, 28),
878
879 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "sspm_sel", sspm_parents,
880 0x90, 0x94, 0x98,
881 8, 3, 15,
882 0x004, 29, CLK_IS_CRITICAL),
883
884 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0, "dpi0_sel", dpi0_parents,
885 0x90, 0x94, 0x98,
886 16, 3, 23,
887 0x004, 30),
888
889 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM, "scam_sel", scam_parents,
890 0x90, 0x94, 0x98,
891 24, 1, 31,
892 0x004, 0),
893
894 /* CLK_CFG_8 */
895 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "disppwm_sel",
896 disppwm_parents,
897 0xa0, 0xa4, 0xa8,
898 0, 3, 7,
899 0x008, 1),
900
901 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "usb_top_sel",
902 usb_top_parents,
903 0xa0, 0xa4, 0xa8,
904 8, 2, 15,
905 0x008, 2),
906
907 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
908 ssusb_top_xhci_parents,
909 0xa0, 0xa4, 0xa8,
910 16, 2, 23,
911 0x008, 3),
912
913 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "spm_sel", spm_parents,
914 0xa0, 0xa4, 0xa8,
915 24, 2, 31,
916 0x008, 4, CLK_IS_CRITICAL),
917
918 /* CLK_CFG_9 */
919 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "i2c_sel", i2c_parents,
920 0xb0, 0xb4, 0xb8,
921 0, 2, 7,
922 0x008, 5),
923
924 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "seninf_sel", seninf_parents,
925 0xb0, 0xb4, 0xb8,
926 8, 2, 15,
927 0x008, 6),
928
929 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "seninf1_sel",
930 seninf1_parents,
931 0xb0, 0xb4, 0xb8,
932 16, 2, 23,
933 0x008, 7),
934
935 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "seninf2_sel",
936 seninf2_parents,
937 0xb0, 0xb4, 0xb8,
938 24, 2, 31,
939 0x008, 8),
940
941 /* CLK_CFG_10 */
942 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc_sel", dxcc_parents,
943 0xc0, 0xc4, 0xc8,
944 0, 2, 7,
945 0x008, 9),
946
947 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG1, "aud_eng1_sel",
948 aud_engen1_parents,
949 0xc0, 0xc4, 0xc8,
950 8, 2, 15,
951 0x008, 10),
952
953 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG2, "aud_eng2_sel",
954 aud_engen2_parents,
955 0xc0, 0xc4, 0xc8,
956 16, 2, 23,
957 0x008, 11),
958
959 MUX_GATE_CLR_SET_UPD(CLK_TOP_FAES_UFSFDE, "faes_ufsfde_sel",
960 faes_ufsfde_parents,
961 0xc0, 0xc4, 0xc8,
962 24, 3, 31,
963 0x008, 12),
964
965 /* CLK_CFG_11 */
966 MUX_GATE_CLR_SET_UPD(CLK_TOP_FUFS, "fufs_sel", fufs_parents,
967 0xd0, 0xd4, 0xd8,
968 0, 2, 7,
969 0x008, 13),
970
971 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1_sel", aud_1_parents,
972 0xd0, 0xd4, 0xd8,
973 8, 1, 15,
974 0x008, 14),
975
976 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "aud_2_sel", aud_2_parents,
977 0xd0, 0xd4, 0xd8,
978 16, 1, 23,
979 0x008, 15),
980
981 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "adsp_sel", adsp_parents,
982 0xd0, 0xd4, 0xd8,
983 24, 3, 31,
984 0x008, 16),
985
986 /* CLK_CFG_12 */
987 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "dpmaif_sel", dpmaif_parents,
988 0xe0, 0xe4, 0xe8,
989 0, 3, 7,
990 0x008, 17),
991
992 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "venc_sel", venc_parents,
993 0xe0, 0xe4, 0xe8,
994 8, 4, 15,
995 0x008, 18),
996
997 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "vdec_sel", vdec_parents,
998 0xe0, 0xe4, 0xe8,
999 16, 4, 23,
1000 0x008, 19),
1001
1002 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "camtm_sel", camtm_parents,
1003 0xe0, 0xe4, 0xe8,
1004 24, 2, 31,
1005 0x004, 20),
1006
1007 /* CLK_CFG_13 */
1008 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "pwm_sel", pwm_parents,
1009 0xf0, 0xf4, 0xf8,
1010 0, 1, 7,
1011 0x008, 21),
1012
1013 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_H, "audio_h_sel",
1014 audio_h_parents,
1015 0xf0, 0xf4, 0xf8,
1016 8, 2, 15,
1017 0x008, 22),
1018
1019 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "camtg5_sel", camtg5_parents,
1020 0xf0, 0xf4, 0xf8,
1021 24, 3, 31,
1022 0x008, 24),
1023};
1024
1025static const char * const i2s0_m_ck_parents[] = {
1026 "aud_1_sel",
1027 "aud_2_sel"
1028};
1029
1030static const char * const i2s1_m_ck_parents[] = {
1031 "aud_1_sel",
1032 "aud_2_sel"
1033};
1034
1035static const char * const i2s2_m_ck_parents[] = {
1036 "aud_1_sel",
1037 "aud_2_sel"
1038};
1039
1040static const char * const i2s3_m_ck_parents[] = {
1041 "aud_1_sel",
1042 "aud_2_sel"
1043};
1044
1045static const char * const i2s4_m_ck_parents[] = {
1046 "aud_1_sel",
1047 "aud_2_sel"
1048};
1049
1050static const char * const i2s5_m_ck_parents[] = {
1051 "aud_1_sel",
1052 "aud_2_sel"
1053};
1054
1055static const struct mtk_composite top_aud_muxes[] = {
1056 MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents,
1057 0x320, 8, 1),
1058 MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents,
1059 0x320, 9, 1),
1060 MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents,
1061 0x320, 10, 1),
1062 MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents,
1063 0x320, 11, 1),
1064 MUX(CLK_TOP_I2S4_M_SEL, "i2s4_m_ck_sel", i2s4_m_ck_parents,
1065 0x320, 12, 1),
1066 MUX(CLK_TOP_I2S5_M_SEL, "i2s5_m_ck_sel", i2s5_m_ck_parents,
1067 0x328, 20, 1),
1068};
1069
1070static struct mtk_composite top_aud_divs[] = {
1071 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel",
1072 0x320, 2, 0x324, 8, 0),
1073 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel",
1074 0x320, 3, 0x324, 8, 8),
1075 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "i2s2_m_ck_sel",
1076 0x320, 4, 0x324, 8, 16),
1077 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "i2s3_m_ck_sel",
1078 0x320, 5, 0x324, 8, 24),
1079 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "i2s4_m_ck_sel",
1080 0x320, 6, 0x328, 8, 0),
1081 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
1082 0x320, 7, 0x328, 8, 8),
1083 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "i2s5_m_ck_sel",
1084 0x328, 16, 0x328, 4, 28),
1085};
1086
1087static const struct mtk_gate_regs infra0_cg_regs = {
1088 .set_ofs = 0x80,
1089 .clr_ofs = 0x84,
1090 .sta_ofs = 0x90,
1091};
1092
1093static const struct mtk_gate_regs infra1_cg_regs = {
1094 .set_ofs = 0x88,
1095 .clr_ofs = 0x8c,
1096 .sta_ofs = 0x94,
1097};
1098
1099static const struct mtk_gate_regs infra2_cg_regs = {
1100 .set_ofs = 0xa4,
1101 .clr_ofs = 0xa8,
1102 .sta_ofs = 0xac,
1103};
1104
1105static const struct mtk_gate_regs infra3_cg_regs = {
1106 .set_ofs = 0xc0,
1107 .clr_ofs = 0xc4,
1108 .sta_ofs = 0xc8,
1109};
1110
1111#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \
1112 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
1113 &mtk_clk_gate_ops_setclr)
1114
1115#define GATE_INFRA0(_id, _name, _parent, _shift) \
1116 GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
1117
1118#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \
1119 GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \
1120 &mtk_clk_gate_ops_setclr, _flags)
1121
1122#define GATE_INFRA1(_id, _name, _parent, _shift) \
1123 GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
1124
1125#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \
1126 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
1127 &mtk_clk_gate_ops_setclr)
1128
1129#define GATE_INFRA2(_id, _name, _parent, _shift) \
1130 GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
1131
1132#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \
1133 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
1134 &mtk_clk_gate_ops_setclr)
1135
1136#define GATE_INFRA3(_id, _name, _parent, _shift) \
1137 GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
1138
1139static const struct mtk_gate infra_clks[] = {
1140
1141 /* INFRA0 */
1142 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
1143 "axi_sel", 0),
1144 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
1145 "axi_sel", 1),
1146 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
1147 "axi_sel", 2),
1148 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
1149 "axi_sel", 3),
1150 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
1151 "f_f26m_ck", 5),
1152 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
1153 "axi_sel", 6),
1154 GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
1155 "axi_sel", 8),
1156 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
1157 "axi_sel", 9),
1158
1159 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
1160 "axi_sel", 10),
1161 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
1162 "i2c_sel", 11),
1163 GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
1164 "i2c_sel", 12),
1165 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
1166 "i2c_sel", 13),
1167 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
1168 "i2c_sel", 14),
1169
1170 GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
1171 "pwm_sel", 15),
1172 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
1173 "pwm_sel", 16),
1174 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
1175 "pwm_sel", 17),
1176 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
1177 "pwm_sel", 18),
1178 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
1179 "pwm_sel", 19),
1180 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
1181 "pwm_sel", 21),
1182
1183 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
1184 "uart_sel", 22),
1185
1186 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
1187 "uart_sel", 23),
1188
1189 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
1190 "uart_sel", 24),
1191 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
1192 "uart_sel", 25),
1193
1194 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
1195 "axi_sel", 27),
1196 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
1197 "axi_sel", 28),
1198 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
1199 "axi_sel", 31),
1200
1201 /* INFRA1 */
1202 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
1203 "spi_sel", 1),
1204 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
1205 "msdc50_hclk_sel", 2),
1206 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
1207 "axi_sel", 4),
1208 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
1209 "axi_sel", 5),
1210 GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
1211 "msdc50_0_sel", 6),
1212 GATE_INFRA1_FLAGS(CLK_INFRA_DVFSRC, "infra_dvfsrc",
1213 "f_f26m_ck", 7, CLK_IS_CRITICAL),
1214 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
1215 "axi_sel", 8),
1216 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
1217 "axi_sel", 9),
1218 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
1219 "f_f26m_ck", 10),
1220 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
1221 "axi_sel", 11),
1222 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
1223 "axi_sel", 12),
1224 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
1225 "axi_sel", 13),
1226 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
1227 "f_f26m_ck", 14),
1228 GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
1229 "msdc30_1_sel", 16),
1230 GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
1231 "msdc30_2_sel", 17),
1232 GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
1233 "axi_sel", 18),
1234 GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
1235 "axi_sel", 19),
1236 GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
1237 "axi_sel", 20),
1238 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
1239 "axi_sel", 23),
1240 /*GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",*/
1241 /*"axi_sel", 24),*/
1242 GATE_INFRA1(CLK_INFRA_AUD, "infra_audio",
1243 "axi_sel", 25),
1244 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
1245 "axi_sel", 26),
1246 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
1247 "dxcc_sel", 27),
1248 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
1249 "dxcc_sel", 28),
1250 GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
1251 "axi_sel", 30),
1252 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
1253 "f_f26m_ck", 31),
1254
1255 /* INFRA2 */
1256 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
1257 "f_f26m_ck", 0),
1258 GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
1259 "usb_top_sel", 1),
1260 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
1261 "axi_sel", 2),
1262 GATE_INFRA2(CLK_INFRA_AUD_26M_BCLK_CK,
1263 "infracfg_ao_audio_26m_bclk_ck", "f_f26m_ck", 4),
1264
1265 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
1266 "spi_sel", 6),
1267 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
1268 "i2c_sel", 7),
1269 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
1270 "f_f26m_ck", 8),
1271 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
1272 "spi_sel", 9),
1273 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
1274 "spi_sel", 10),
1275 GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
1276 "fufs_sel", 11),
1277 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
1278 "fufs_sel", 12),
1279 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
1280 "fufs_sel", 13),
1281 GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
1282 "axi_sel", 14),
1283
1284 /*GATE_INFRA2_FLAGS(CLK_INFRA_SSPM, "infra_sspm",*/
1285 /*"sspm_sel", 15, CLK_IGNORE_UNUSED),*/
1286
1287 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
1288 "axi_sel", 16),
1289 GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk",
1290 "axi_sel", 17),
1291 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
1292 "i2c_sel", 18),
1293 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
1294 "i2c_sel", 19),
1295 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
1296 "i2c_sel", 20),
1297 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
1298 "i2c_sel", 21),
1299 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
1300 "i2c_sel", 22),
1301 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
1302 "i2c_sel", 23),
1303 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
1304 "i2c_sel", 24),
1305 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
1306 "spi_sel", 25),
1307 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
1308 "spi_sel", 26),
1309 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
1310 "axi_sel", 27),
1311 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
1312 "fufs_sel", 28),
1313 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
1314 "faes_ufsfde_sel", 29),
1315 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
1316 "fufs_sel", 30),
1317 GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci",
1318 "ssusb_top_xhci_sel", 31),
1319
1320 /* INFRA3 */
1321 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
1322 "msdc50_0_sel", 0),
1323 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
1324 "msdc50_0_sel", 1),
1325 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
1326 "msdc50_0_sel", 2),
1327 GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self",
1328 "f_f26m_ck", 3),
1329 GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self",
1330 "f_f26m_ck", 4),
1331 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
1332 "axi_sel", 5),
1333 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
1334 "i2c_sel", 6),
1335 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
1336 "msdc50_hclk_sel", 7),
1337 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
1338 "msdc50_hclk_sel", 8),
1339
1340 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
1341 "axi_sel", 16),
1342 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
1343 "axi_sel", 17),
1344 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
1345 "axi_sel", 18),
1346 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
1347 "axi_sel", 19),
1348 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
1349 "f_f26m_ck", 20),
1350 GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
1351 "axi_sel", 21),
1352 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
1353 "i2c_sel", 22),
1354 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
1355 "i2c_sel", 23),
1356 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
1357 "msdc50_0_sel", 24),
1358 GATE_INFRA3(CLK_INFRA_DPMAIF_CK, "infra_dpmaif",
1359 "dpmaif_sel", 26),
1360 GATE_INFRA3(CLK_INFRA_FADSP, "infra_fadsp",
1361 "adsp_sel", 27),
1362 GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap",
1363 "axi_sel", 28),
1364 GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md",
1365 "axi_sel", 29),
1366 GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6",
1367 "spi_sel", 30),
1368 GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7",
1369 "spi_sel", 31),
1370};
1371
1372static const struct mtk_gate_regs apmixed_cg_regs = {
1373 .set_ofs = 0x20,
1374 .clr_ofs = 0x20,
1375 .sta_ofs = 0x20,
1376};
1377
1378#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
1379 GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
1380 _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
1381
1382#define GATE_APMIXED(_id, _name, _parent, _shift) \
1383 GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
1384
1385/*
1386 * CRITICAL CLOCK:
1387 * apmixed_appll26m is the toppest clock gate of all PLLs.
1388 */
1389static const struct mtk_gate apmixed_clks[] = {
1390 GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m",
1391 "f_f26m_ck",
1392 4),
1393 GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL26M, "apmixed_appll26m",
1394 "f_f26m_ck",
1395 5, CLK_IS_CRITICAL),
1396 GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
1397 "f_f26m_ck",
1398 6),
1399 GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m",
1400 "f_f26m_ck",
1401 7),
1402 GATE_APMIXED(CLK_APMIXED_MM_F26M, "apmixed_mmsys26m",
1403 "f_f26m_ck",
1404 8),
1405 GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m",
1406 "f_f26m_ck",
1407 9),
1408 GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
1409 "f_f26m_ck",
1410 11),
1411 GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m",
1412 "f_f26m_ck",
1413 13),
1414 GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
1415 "f_f26m_ck",
1416 14),
1417 GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
1418 "f_f26m_ck",
1419 16),
1420 GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
1421 "f_f26m_ck",
1422 17),
1423};
1424
1425#define MT6779_PLL_FMAX (3800UL * MHZ)
1426#define MT6779_PLL_FMIN (1500UL * MHZ)
1427
1428#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1429 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1430 _pd_shift, _tuner_reg, _tuner_en_reg, \
1431 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1432 _pcw_chg_reg, _div_table) { \
1433 .id = _id, \
1434 .name = _name, \
1435 .reg = _reg, \
1436 .pwr_reg = _pwr_reg, \
1437 .en_mask = _en_mask, \
1438 .flags = _flags, \
1439 .rst_bar_mask = _rst_bar_mask, \
1440 .fmax = MT6779_PLL_FMAX, \
1441 .fmin = MT6779_PLL_FMIN, \
1442 .pcwbits = _pcwbits, \
1443 .pcwibits = _pcwibits, \
1444 .pd_reg = _pd_reg, \
1445 .pd_shift = _pd_shift, \
1446 .tuner_reg = _tuner_reg, \
1447 .tuner_en_reg = _tuner_en_reg, \
1448 .tuner_en_bit = _tuner_en_bit, \
1449 .pcw_reg = _pcw_reg, \
1450 .pcw_shift = _pcw_shift, \
1451 .pcw_chg_reg = _pcw_chg_reg, \
1452 .div_table = _div_table, \
1453 }
1454
1455#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1456 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1457 _pd_shift, _tuner_reg, _tuner_en_reg, \
1458 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1459 _pcw_chg_reg) \
1460 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1461 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1462 _pd_shift, _tuner_reg, _tuner_en_reg, \
1463 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1464 _pcw_chg_reg, NULL)
1465
1466static const struct mtk_pll_data plls[] = {
1467 PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, BIT(0),
1468 PLL_AO, 0,
1469 22, 8,
1470 0x0204, 24,
1471 0, 0, 0,
1472 0x0204, 0, 0),
1473 PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, BIT(0),
1474 PLL_AO, 0,
1475 22, 8,
1476 0x0214, 24,
1477 0, 0, 0,
1478 0x0214, 0, 0),
1479 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, BIT(0),
1480 PLL_AO, 0,
1481 22, 8,
1482 0x02A4, 24,
1483 0, 0, 0,
1484 0x02A4, 0, 0),
1485 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, BIT(0),
1486 (HAVE_RST_BAR | PLL_AO), BIT(24),
1487 22, 8,
1488 0x0234, 24,
1489 0, 0, 0,
1490 0x0234, 0, 0),
1491
1492 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, BIT(0),
1493 (HAVE_RST_BAR), BIT(24),
1494 22, 8,
1495 0x0244, 24,
1496 0, 0, 0,
1497 0x0244, 0, 0),
1498
1499 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, BIT(0),
1500 0, 0,
1501 22, 8,
1502 0x0254, 24,
1503 0, 0, 0,
1504 0x0254, 0, 0),
1505
1506 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, BIT(0),
1507 0, 0,
1508 22, 8,
1509 0x0264, 24,
1510 0, 0, 0,
1511 0x0264, 0, 0),
1512
1513 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, BIT(0),
1514 0, 0,
1515 22, 8,
1516 0x0274, 24,
1517 0, 0, 0,
1518 0x0274, 0, 0),
1519
1520 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, BIT(0),
1521 (HAVE_RST_BAR), BIT(23),
1522 22, 8,
1523 0x02b4, 24,
1524 0, 0, 0,
1525 0x02b4, 0, 0),
1526
1527 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, BIT(0),
1528 (HAVE_RST_BAR), BIT(23),
1529 22, 8,
1530 0x0284, 24,
1531 0, 0, 0,
1532 0x0284, 0, 0),
1533
1534 PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, BIT(0),
1535 0, 0,
1536 32, 8,
1537 0x02C0, 1,
1538 0, 0x14, 0,
1539 0x02C4, 0, 0x2C0),
1540
1541 PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, BIT(0),
1542 0, 0,
1543 32, 8,
1544 0x02D4, 1,
1545 0, 0x14, 1,
1546 0x02D8, 0, 0x02D4),
1547};
1548
1549
1550static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
1551{
1552 struct clk_onecell_data *clk_data;
1553 struct device_node *node = pdev->dev.of_node;
1554
1555 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1556
1557 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1558
1559 mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks),
1560 clk_data);
1561
1562 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1563}
1564
1565static int clk_mt6779_top_probe(struct platform_device *pdev)
1566{
1567 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1568 void __iomem *base;
1569 struct clk_onecell_data *clk_data;
1570 struct device_node *node = pdev->dev.of_node;
1571
1572 base = devm_ioremap_resource(&pdev->dev, res);
1573 if (IS_ERR(base))
1574 return PTR_ERR(base);
1575
1576 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1577
1578 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1579 clk_data);
1580
1581 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
1582
1583 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
1584 node, &mt6779_clk_lock, clk_data);
1585
1586 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
1587 base, &mt6779_clk_lock, clk_data);
1588
1589 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
1590 base, &mt6779_clk_lock, clk_data);
1591
1592 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1593}
1594
1595static int clk_mt6779_infra_probe(struct platform_device *pdev)
1596{
1597 struct clk_onecell_data *clk_data;
1598 struct device_node *node = pdev->dev.of_node;
1599
1600 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1601
1602 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1603 clk_data);
1604
1605 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1606}
1607
1608static const struct of_device_id of_match_clk_mt6779[] = {
1609 {
1610 .compatible = "mediatek,mt6779-apmixed",
1611 .data = clk_mt6779_apmixed_probe,
1612 }, {
1613 .compatible = "mediatek,mt6779-topckgen",
1614 .data = clk_mt6779_top_probe,
1615 }, {
1616 .compatible = "mediatek,mt6779-infracfg_ao",
1617 .data = clk_mt6779_infra_probe,
1618 }, {
1619 /* sentinel */
1620 }
1621};
1622
1623static int clk_mt6779_probe(struct platform_device *pdev)
1624{
1625 int (*clk_probe)(struct platform_device *pdev);
1626 int r;
1627
1628 clk_probe = of_device_get_match_data(&pdev->dev);
1629 if (!clk_probe)
1630 return -EINVAL;
1631
1632 r = clk_probe(pdev);
1633 if (r)
1634 dev_err(&pdev->dev,
1635 "could not register clock provider: %s: %d\n",
1636 pdev->name, r);
1637
1638 return r;
1639}
1640
1641static struct platform_driver clk_mt6779_drv = {
1642 .probe = clk_mt6779_probe,
1643 .driver = {
1644 .name = "clk-mt6779",
1645 .of_match_table = of_match_clk_mt6779,
1646 },
1647};
1648
1649static int __init clk_mt6779_init(void)
1650{
1651 return platform_driver_register(&clk_mt6779_drv);
1652}
1653
1654arch_initcall(clk_mt6779_init);