| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | config USB_DWC3 |
| 2 | tristate "DesignWare USB3 DRD Core Support" |
| 3 | depends on (USB || USB_GADGET) && HAS_DMA |
| 4 | select USB_XHCI_PLATFORM if USB_XHCI_HCD |
| 5 | help |
| 6 | Say Y or M here if your system has a Dual Role SuperSpeed |
| 7 | USB controller based on the DesignWare USB3 IP Core. |
| 8 | |
| 9 | If you choose to build this driver is a dynamically linked |
| 10 | module, the module will be called dwc3.ko. |
| 11 | |
| 12 | if USB_DWC3 |
| 13 | |
| 14 | config USB_DWC3_ULPI |
| 15 | bool "Register ULPI PHY Interface" |
| 16 | depends on USB_ULPI_BUS=y || USB_ULPI_BUS=USB_DWC3 |
| 17 | help |
| 18 | Select this if you have ULPI type PHY attached to your DWC3 |
| 19 | controller. |
| 20 | |
| 21 | choice |
| 22 | bool "DWC3 Mode Selection" |
| 23 | default USB_DWC3_DUAL_ROLE if (USB && USB_GADGET) |
| 24 | default USB_DWC3_HOST if (USB && !USB_GADGET) |
| 25 | default USB_DWC3_GADGET if (!USB && USB_GADGET) |
| 26 | |
| 27 | config USB_DWC3_HOST |
| 28 | bool "Host only mode" |
| 29 | depends on USB=y || USB=USB_DWC3 |
| 30 | help |
| 31 | Select this when you want to use DWC3 in host mode only, |
| 32 | thereby the gadget feature will be regressed. |
| 33 | |
| 34 | config USB_DWC3_GADGET |
| 35 | bool "Gadget only mode" |
| 36 | depends on USB_GADGET=y || USB_GADGET=USB_DWC3 |
| 37 | help |
| 38 | Select this when you want to use DWC3 in gadget mode only, |
| 39 | thereby the host feature will be regressed. |
| 40 | |
| 41 | config USB_DWC3_DUAL_ROLE |
| 42 | bool "Dual Role mode" |
| 43 | depends on ((USB=y || USB=USB_DWC3) && (USB_GADGET=y || USB_GADGET=USB_DWC3)) |
| 44 | depends on (EXTCON=y || EXTCON=USB_DWC3) |
| 45 | help |
| 46 | This is the default mode of working of DWC3 controller where |
| 47 | both host and gadget features are enabled. |
| 48 | |
| 49 | endchoice |
| 50 | |
| 51 | comment "Platform Glue Driver Support" |
| 52 | |
| 53 | config USB_DWC3_OMAP |
| 54 | tristate "Texas Instruments OMAP5 and similar Platforms" |
| 55 | depends on EXTCON && (ARCH_OMAP2PLUS || COMPILE_TEST) |
| 56 | depends on OF |
| 57 | default USB_DWC3 |
| 58 | help |
| 59 | Some platforms from Texas Instruments like OMAP5, DRA7xxx and |
| 60 | AM437x use this IP for USB2/3 functionality. |
| 61 | |
| 62 | Say 'Y' or 'M' here if you have one such device |
| 63 | |
| 64 | config USB_DWC3_EXYNOS |
| 65 | tristate "Samsung Exynos Platform" |
| 66 | depends on (ARCH_EXYNOS || COMPILE_TEST) && OF |
| 67 | default USB_DWC3 |
| 68 | help |
| 69 | Recent Exynos5 SoCs ship with one DesignWare Core USB3 IP inside, |
| 70 | say 'Y' or 'M' if you have one such device. |
| 71 | |
| 72 | config USB_DWC3_PCI |
| 73 | tristate "PCIe-based Platforms" |
| 74 | depends on USB_PCI && ACPI |
| 75 | default USB_DWC3 |
| 76 | help |
| 77 | If you're using the DesignWare Core IP with a PCIe (but not HAPS |
| 78 | platform), please say 'Y' or 'M' here. |
| 79 | |
| 80 | config USB_DWC3_HAPS |
| 81 | tristate "Synopsys PCIe-based HAPS Platforms" |
| 82 | depends on USB_PCI |
| 83 | default USB_DWC3 |
| 84 | help |
| 85 | If you're using the DesignWare Core IP with a Synopsys PCIe HAPS |
| 86 | platform, please say 'Y' or 'M' here. |
| 87 | |
| 88 | config USB_DWC3_KEYSTONE |
| 89 | tristate "Texas Instruments Keystone2 Platforms" |
| 90 | depends on ARCH_KEYSTONE || COMPILE_TEST |
| 91 | default USB_DWC3 |
| 92 | help |
| 93 | Support of USB2/3 functionality in TI Keystone2 platforms. |
| 94 | Say 'Y' or 'M' here if you have one such device |
| 95 | |
| 96 | config USB_DWC3_OF_SIMPLE |
| 97 | tristate "Generic OF Simple Glue Layer" |
| 98 | depends on OF && COMMON_CLK |
| 99 | default USB_DWC3 |
| 100 | help |
| 101 | Support USB2/3 functionality in simple SoC integrations. |
| 102 | Currently supports Xilinx and Qualcomm DWC USB3 IP. |
| 103 | Say 'Y' or 'M' if you have one such device. |
| 104 | |
| 105 | config USB_DWC3_ST |
| 106 | tristate "STMicroelectronics Platforms" |
| 107 | depends on (ARCH_STI || COMPILE_TEST) && OF |
| 108 | default USB_DWC3 |
| 109 | help |
| 110 | STMicroelectronics SoCs with one DesignWare Core USB3 IP |
| 111 | inside (i.e. STiH407). |
| 112 | Say 'Y' or 'M' if you have one such device. |
| 113 | |
| 114 | config USB_DWC3_QCOM |
| 115 | tristate "Qualcomm Platform" |
| 116 | depends on ARCH_QCOM || COMPILE_TEST |
| 117 | depends on OF |
| 118 | default USB_DWC3 |
| 119 | help |
| 120 | Some Qualcomm SoCs use DesignWare Core IP for USB2/3 |
| 121 | functionality. |
| 122 | This driver also handles Qscratch wrapper which is needed |
| 123 | for peripheral mode support. |
| 124 | Say 'Y' or 'M' if you have one such device. |
| 125 | |
| 126 | endif |