| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 |
| 2 | * |
| 3 | * Copyright (C) 2018 Renesas Electronics Corp. |
| 4 | * Copyright (C) 2018 Cogent Embedded, Inc. |
| 5 | */ |
| 6 | #ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__ |
| 7 | #define __DT_BINDINGS_POWER_R8A77980_SYSC_H__ |
| 8 | |
| 9 | /* |
| 10 | * These power domain indices match the numbers of the interrupt bits |
| 11 | * representing the power areas in the various Interrupt Registers |
| 12 | * (e.g. SYSCISR, Interrupt Status Register) |
| 13 | */ |
| 14 | |
| 15 | #define R8A77980_PD_A2SC2 0 |
| 16 | #define R8A77980_PD_A2SC3 1 |
| 17 | #define R8A77980_PD_A2SC4 2 |
| 18 | #define R8A77980_PD_A2DP0 3 |
| 19 | #define R8A77980_PD_A2DP1 4 |
| 20 | #define R8A77980_PD_CA53_CPU0 5 |
| 21 | #define R8A77980_PD_CA53_CPU1 6 |
| 22 | #define R8A77980_PD_CA53_CPU2 7 |
| 23 | #define R8A77980_PD_CA53_CPU3 8 |
| 24 | #define R8A77980_PD_A2CN 10 |
| 25 | #define R8A77980_PD_A3VIP0 11 |
| 26 | #define R8A77980_PD_A2IR5 12 |
| 27 | #define R8A77980_PD_CR7 13 |
| 28 | #define R8A77980_PD_A2IR4 15 |
| 29 | #define R8A77980_PD_CA53_SCU 21 |
| 30 | #define R8A77980_PD_A2IR0 23 |
| 31 | #define R8A77980_PD_A3IR 24 |
| 32 | #define R8A77980_PD_A3VIP1 25 |
| 33 | #define R8A77980_PD_A3VIP2 26 |
| 34 | #define R8A77980_PD_A2IR1 27 |
| 35 | #define R8A77980_PD_A2IR2 28 |
| 36 | #define R8A77980_PD_A2IR3 29 |
| 37 | #define R8A77980_PD_A2SC0 30 |
| 38 | #define R8A77980_PD_A2SC1 31 |
| 39 | |
| 40 | /* Always-on power area */ |
| 41 | #define R8A77980_PD_ALWAYS_ON 32 |
| 42 | |
| 43 | #endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */ |