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xjb04a4022021-11-25 15:01:52 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9#include <dt-bindings/clock/mt6779-clk.h>
10
11#include "clk-mtk.h"
12#include "clk-gate.h"
13
14static const struct mtk_gate_regs ipe_cg_regs = {
15 .set_ofs = 0x0004,
16 .clr_ofs = 0x0008,
17 .sta_ofs = 0x0000,
18};
19
20#define GATE_IPE(_id, _name, _parent, _shift) \
21 GATE_IPE_FLAGS(_id, _name, _parent, _shift, 0)
22
23#define GATE_IPE_FLAGS(_id, _name, _parent, _shift, _flags) { \
24 .id = _id, \
25 .name = _name, \
26 .parent_name = _parent, \
27 .regs = &ipe_cg_regs, \
28 .shift = _shift, \
29 .ops = &mtk_clk_gate_ops_setclr, \
30 .flags = _flags, \
31 }
32
33static const struct mtk_gate ipe_clks[] = {
34 GATE_IPE(CLK_IPE_LARB7, "ipe_larb7", "ipe_sel", 0),
35 GATE_IPE(CLK_IPE_LARB8, "ipe_larb8", "ipe_sel", 1),
36 GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2),
37 GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3),
38 GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4),
39 GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5),
40 GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 6),
41};
42
43static const struct of_device_id of_match_clk_mt6779_ipe[] = {
44 { .compatible = "mediatek,mt6779-ipesys", },
45 {}
46};
47
48static int clk_mt6779_ipe_probe(struct platform_device *pdev)
49{
50 struct clk_onecell_data *clk_data;
51 struct device_node *node = pdev->dev.of_node;
52
53 clk_data = mtk_alloc_clk_data(CLK_IPE_NR_CLK);
54
55 mtk_clk_register_gates(node, ipe_clks, ARRAY_SIZE(ipe_clks),
56 clk_data);
57
58 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
59}
60
61static struct platform_driver clk_mt6779_ipe_drv = {
62 .probe = clk_mt6779_ipe_probe,
63 .driver = {
64 .name = "clk-mt6779-ipe",
65 .of_match_table = of_match_clk_mt6779_ipe,
66 },
67};
68
69builtin_platform_driver(clk_mt6779_ipe_drv);