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192.168.1.100 / T800 / 17fc9a38d3e5f827f08b7aa7ea78c8119d9a65fc / . / src / kernel / linux / v4.19 / drivers / interconnect / mediatek / mmqos-mt6779.c
blob: 15f2ab89458f13f520285603827c910933d26bd3 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Ming-Fan Chen <ming-fan.chen@mediatek.com>
5 */
6
7#include <dt-bindings/interconnect/mtk,mmqos.h>
8#include <dt-bindings/interconnect/mtk,mt6779-emi.h>
9#include <dt-bindings/memory/mt6779-larb-port.h>
10#include <linux/module.h>
11#include <linux/of_platform.h>
12
13#include "mmqos-mtk.h"
14
15
16static const struct mtk_node_desc node_descs_mt6779[] = {
17 DEFINE_MNODE(common0,
18 SLAVE_COMMON(0), 0, MMQOS_NO_LINK),
19 DEFINE_MNODE(common0_port0,
20 MASTER_COMMON_PORT(0, 0), 0, SLAVE_COMMON(0)),
21 DEFINE_MNODE(common0_port1,
22 MASTER_COMMON_PORT(0, 1), 0, SLAVE_COMMON(0)),
23 DEFINE_MNODE(common0_port2,
24 MASTER_COMMON_PORT(0, 2), 0, SLAVE_COMMON(0)),
25 DEFINE_MNODE(common0_port3,
26 MASTER_COMMON_PORT(0, 3), 0, SLAVE_COMMON(0)),
27 DEFINE_MNODE(common0_port4,
28 MASTER_COMMON_PORT(0, 4), 0, SLAVE_COMMON(0)),
29 DEFINE_MNODE(common0_port5,
30 MASTER_COMMON_PORT(0, 5), 0, SLAVE_COMMON(0)),
31 DEFINE_MNODE(common0_port6,
32 MASTER_COMMON_PORT(0, 6), 0, SLAVE_COMMON(0)),
33 DEFINE_MNODE(common0_port7,
34 MASTER_COMMON_PORT(0, 7), 0, SLAVE_COMMON(0)),
35 DEFINE_MNODE(common0_port8,
36 MASTER_COMMON_PORT(0, 8), 0, SLAVE_COMMON(0)),
37 DEFINE_MNODE(larb0, SLAVE_LARB(0), 0, MASTER_COMMON_PORT(0, 0)),
38 DEFINE_MNODE(larb1, SLAVE_LARB(1), 0, MASTER_COMMON_PORT(0, 1)),
39 DEFINE_MNODE(larb2, SLAVE_LARB(2), 0, MASTER_COMMON_PORT(0, 2)),
40 DEFINE_MNODE(larb3, SLAVE_LARB(3), 0, MASTER_COMMON_PORT(0, 3)),
41 DEFINE_MNODE(larb5, SLAVE_LARB(5), 0, MASTER_COMMON_PORT(0, 4)),
42 DEFINE_MNODE(larb8, SLAVE_LARB(8), 0, MASTER_COMMON_PORT(0, 5)),
43 DEFINE_MNODE(larb9, SLAVE_LARB(9), 0, MASTER_COMMON_PORT(0, 7)),
44 DEFINE_MNODE(larb10, SLAVE_LARB(10), 0, MASTER_COMMON_PORT(0, 6)),
45 DEFINE_MNODE(larb12, SLAVE_LARB(12), 0, MASTER_COMMON_PORT(0, 8)),
46 DEFINE_MNODE(larb13, SLAVE_LARB(13), 0, MASTER_COMMON_PORT(0, 6)),
47 DEFINE_MNODE(disp_postmask0,
48 MASTER_LARB_PORT(M4U_PORT_DISP_POSTMASK0), 7, SLAVE_LARB(0)),
49 DEFINE_MNODE(disp_ovl0_hdr,
50 MASTER_LARB_PORT(M4U_PORT_DISP_OVL0_HDR), 7, SLAVE_LARB(0)),
51 DEFINE_MNODE(disp_ovl1_hdr,
52 MASTER_LARB_PORT(M4U_PORT_DISP_OVL1_HDR), 7, SLAVE_LARB(0)),
53 DEFINE_MNODE(disp_ovl0,
54 MASTER_LARB_PORT(M4U_PORT_DISP_OVL0), 7, SLAVE_LARB(0)),
55 DEFINE_MNODE(disp_ovl1,
56 MASTER_LARB_PORT(M4U_PORT_DISP_OVL1), 7, SLAVE_LARB(0)),
57 DEFINE_MNODE(disp_pvric0,
58 MASTER_LARB_PORT(M4U_PORT_DISP_PVRIC0), 7, SLAVE_LARB(0)),
59 DEFINE_MNODE(disp_rdma0,
60 MASTER_LARB_PORT(M4U_PORT_DISP_RDMA0), 7, SLAVE_LARB(0)),
61 DEFINE_MNODE(disp_wdma0,
62 MASTER_LARB_PORT(M4U_PORT_DISP_WDMA0), 8, SLAVE_LARB(0)),
63 DEFINE_MNODE(disp_fake0,
64 MASTER_LARB_PORT(M4U_PORT_DISP_FAKE0), 7, SLAVE_LARB(0)),
65
66 DEFINE_MNODE(disp_ovl0_2l_hdr,
67 MASTER_LARB_PORT(M4U_PORT_DISP_OVL0_2L_HDR), 7, SLAVE_LARB(1)),
68 DEFINE_MNODE(disp_ovl1_2l_hdr,
69 MASTER_LARB_PORT(M4U_PORT_DISP_OVL1_2L_HDR), 7, SLAVE_LARB(1)),
70 DEFINE_MNODE(disp_ovl0_2l,
71 MASTER_LARB_PORT(M4U_PORT_DISP_OVL0_2L), 7, SLAVE_LARB(1)),
72 DEFINE_MNODE(disp_ovl1_2l,
73 MASTER_LARB_PORT(M4U_PORT_DISP_OVL1_2L), 7, SLAVE_LARB(1)),
74 DEFINE_MNODE(disp_rdma1,
75 MASTER_LARB_PORT(M4U_PORT_DISP_RDMA1), 7, SLAVE_LARB(1)),
76 DEFINE_MNODE(mdp_pvric0,
77 MASTER_LARB_PORT(M4U_PORT_MDP_PVRIC0), 7, SLAVE_LARB(1)),
78 DEFINE_MNODE(mdp_pvric1,
79 MASTER_LARB_PORT(M4U_PORT_MDP_PVRIC1), 7, SLAVE_LARB(1)),
80 DEFINE_MNODE(mdp_rdma0,
81 MASTER_LARB_PORT(M4U_PORT_MDP_RDMA0), 7, SLAVE_LARB(1)),
82 DEFINE_MNODE(mdp_rdma1,
83 MASTER_LARB_PORT(M4U_PORT_MDP_RDMA1), 7, SLAVE_LARB(1)),
84 DEFINE_MNODE(mdp_wrot0_r,
85 MASTER_LARB_PORT(M4U_PORT_MDP_WROT0_R), 8, SLAVE_LARB(1)),
86 DEFINE_MNODE(mdp_wrot0_w,
87 MASTER_LARB_PORT(M4U_PORT_MDP_WROT0_W), 7, SLAVE_LARB(1)),
88 DEFINE_MNODE(mdp_wrot1_r,
89 MASTER_LARB_PORT(M4U_PORT_MDP_WROT1_R), 8, SLAVE_LARB(1)),
90 DEFINE_MNODE(mdp_wrot1_w,
91 MASTER_LARB_PORT(M4U_PORT_MDP_WROT1_W), 7, SLAVE_LARB(1)),
92 DEFINE_MNODE(disp_fake1,
93 MASTER_LARB_PORT(M4U_PORT_DISP_FAKE1), 7, SLAVE_LARB(1)),
94
95 DEFINE_MNODE(vdec_mc_ext,
96 MASTER_LARB_PORT(M4U_PORT_HW_VDEC_MC_EXT), 7, SLAVE_LARB(2)),
97 DEFINE_MNODE(vdec_ufo_ext,
98 MASTER_LARB_PORT(M4U_PORT_HW_VDEC_UFO_EXT), 7, SLAVE_LARB(2)),
99 DEFINE_MNODE(vdec_pp_ext,
100 MASTER_LARB_PORT(M4U_PORT_HW_VDEC_PP_EXT), 8, SLAVE_LARB(2)),
101 DEFINE_MNODE(vdec_pred_rd_ext,
102 MASTER_LARB_PORT(M4U_PORT_HW_VDEC_PRED_RD_EXT),
103 7, SLAVE_LARB(2)),
104 DEFINE_MNODE(vdec_pred_wr_ext,
105 MASTER_LARB_PORT(M4U_PORT_HW_VDEC_PRED_WR_EXT),
106 7, SLAVE_LARB(2)),
107 DEFINE_MNODE(vdec_ppwrap_ext,
108 MASTER_LARB_PORT(M4U_PORT_HW_VDEC_PPWRAP_EXT),
109 7, SLAVE_LARB(2)),
110 DEFINE_MNODE(vdec_tile_ext,
111 MASTER_LARB_PORT(M4U_PORT_HW_VDEC_TILE_EXT), 7, SLAVE_LARB(2)),
112 DEFINE_MNODE(vdec_vld_ext,
113 MASTER_LARB_PORT(M4U_PORT_HW_VDEC_VLD_EXT), 7, SLAVE_LARB(2)),
114 DEFINE_MNODE(vdec_vld2_ext,
115 MASTER_LARB_PORT(M4U_PORT_HW_VDEC_VLD2_EXT), 7, SLAVE_LARB(2)),
116 DEFINE_MNODE(vdec_avc_mv_ext,
117 MASTER_LARB_PORT(M4U_PORT_HW_VDEC_AVC_MV_EXT),
118 7, SLAVE_LARB(2)),
119 DEFINE_MNODE(vdec_ufo_enc_ext,
120 MASTER_LARB_PORT(M4U_PORT_HW_VDEC_UFO_ENC_EXT),
121 8, SLAVE_LARB(2)),
122 DEFINE_MNODE(vdec_rg_ctrl_dma_ext,
123 MASTER_LARB_PORT(M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT),
124 7, SLAVE_LARB(2)),
125
126 DEFINE_MNODE(venc_rcpu,
127 MASTER_LARB_PORT(M4U_PORT_VENC_RCPU), 7, SLAVE_LARB(3)),
128 DEFINE_MNODE(venc_rec,
129 MASTER_LARB_PORT(M4U_PORT_VENC_REC), 8, SLAVE_LARB(3)),
130 DEFINE_MNODE(venc_bsdma,
131 MASTER_LARB_PORT(M4U_PORT_VENC_BSDMA), 8, SLAVE_LARB(3)),
132 DEFINE_MNODE(venc_sv_comv,
133 MASTER_LARB_PORT(M4U_PORT_VENC_SV_COMV), 8, SLAVE_LARB(3)),
134 DEFINE_MNODE(venc_rd_comv,
135 MASTER_LARB_PORT(M4U_PORT_VENC_RD_COMV), 7, SLAVE_LARB(3)),
136 DEFINE_MNODE(venc_nbm_rdma,
137 MASTER_LARB_PORT(M4U_PORT_VENC_NBM_RDMA), 7, SLAVE_LARB(3)),
138 DEFINE_MNODE(venc_nbm_rdma_lite,
139 MASTER_LARB_PORT(M4U_PORT_VENC_NBM_RDMA_LITE),
140 7, SLAVE_LARB(3)),
141 DEFINE_MNODE(jpgenc_y_rdma,
142 MASTER_LARB_PORT(M4U_PORT_JPGENC_Y_RDMA), 7, SLAVE_LARB(3)),
143 DEFINE_MNODE(jpgenc_c_rdma,
144 MASTER_LARB_PORT(M4U_PORT_JPGENC_C_RDMA), 7, SLAVE_LARB(3)),
145 DEFINE_MNODE(jpgenc_q_table,
146 MASTER_LARB_PORT(M4U_PORT_JPGENC_Q_TABLE), 7, SLAVE_LARB(3)),
147 DEFINE_MNODE(jpgenc_bsdma,
148 MASTER_LARB_PORT(M4U_PORT_JPGENC_BSDMA), 8, SLAVE_LARB(3)),
149 DEFINE_MNODE(jpgedc_wdma,
150 MASTER_LARB_PORT(M4U_PORT_JPGDEC_WDMA), 8, SLAVE_LARB(3)),
151 DEFINE_MNODE(jpgedc_bsdma,
152 MASTER_LARB_PORT(M4U_PORT_JPGDEC_BSDMA), 8, SLAVE_LARB(3)),
153 DEFINE_MNODE(venc_nbm_wdma,
154 MASTER_LARB_PORT(M4U_PORT_VENC_NBM_WDMA), 8, SLAVE_LARB(3)),
155 DEFINE_MNODE(venc_nbm_wdma_lite,
156 MASTER_LARB_PORT(M4U_PORT_VENC_NBM_WDMA_LITE),
157 8, SLAVE_LARB(3)),
158 DEFINE_MNODE(venc_cur_luma,
159 MASTER_LARB_PORT(M4U_PORT_VENC_CUR_LUMA), 7, SLAVE_LARB(3)),
160 DEFINE_MNODE(venc_cur_chroma,
161 MASTER_LARB_PORT(M4U_PORT_VENC_CUR_CHROMA), 7, SLAVE_LARB(3)),
162 DEFINE_MNODE(venc_ref_luma,
163 MASTER_LARB_PORT(M4U_PORT_VENC_REF_LUMA), 7, SLAVE_LARB(3)),
164 DEFINE_MNODE(venc_ref_chroma,
165 MASTER_LARB_PORT(M4U_PORT_VENC_REF_CHROMA), 7, SLAVE_LARB(3)),
166
167 DEFINE_MNODE(img_imgi_d1,
168 MASTER_LARB_PORT(M4U_PORT_IMGI_D1), 7, SLAVE_LARB(5)),
169 DEFINE_MNODE(img_imgbi_d1,
170 MASTER_LARB_PORT(M4U_PORT_IMGBI_D1), 7, SLAVE_LARB(5)),
171 DEFINE_MNODE(img_dmgi_d1,
172 MASTER_LARB_PORT(M4U_PORT_DMGI_D1), 7, SLAVE_LARB(5)),
173 DEFINE_MNODE(img_depi_d1,
174 MASTER_LARB_PORT(M4U_PORT_DEPI_D1), 7, SLAVE_LARB(5)),
175 DEFINE_MNODE(img_lcei_d1,
176 MASTER_LARB_PORT(M4U_PORT_LCEI_D1), 7, SLAVE_LARB(5)),
177 DEFINE_MNODE(img_smti_d1,
178 MASTER_LARB_PORT(M4U_PORT_SMTI_D1), 7, SLAVE_LARB(5)),
179 DEFINE_MNODE(img_smto_d2,
180 MASTER_LARB_PORT(M4U_PORT_SMTO_D2), 8, SLAVE_LARB(5)),
181 DEFINE_MNODE(img_smto_d1,
182 MASTER_LARB_PORT(M4U_PORT_SMTO_D1), 8, SLAVE_LARB(5)),
183 DEFINE_MNODE(img_crzo_d1,
184 MASTER_LARB_PORT(M4U_PORT_CRZO_D1), 8, SLAVE_LARB(5)),
185 DEFINE_MNODE(img_img3o_d1,
186 MASTER_LARB_PORT(M4U_PORT_IMG3O_D1), 8, SLAVE_LARB(5)),
187 DEFINE_MNODE(img_vipi_d1,
188 MASTER_LARB_PORT(M4U_PORT_VIPI_D1), 7, SLAVE_LARB(5)),
189 DEFINE_MNODE(img_wpe_rdma1,
190 MASTER_LARB_PORT(M4U_PORT_WPE_RDMA1), 7, SLAVE_LARB(5)),
191 DEFINE_MNODE(img_wpe_rdma0,
192 MASTER_LARB_PORT(M4U_PORT_WPE_RDMA0), 7, SLAVE_LARB(5)),
193 DEFINE_MNODE(img_wpe_wdma,
194 MASTER_LARB_PORT(M4U_PORT_WPE_WDMA), 8, SLAVE_LARB(5)),
195 DEFINE_MNODE(img_timgo_d1,
196 MASTER_LARB_PORT(M4U_PORT_TIMGO_D1), 8, SLAVE_LARB(5)),
197 DEFINE_MNODE(img_mfb_rdma0,
198 MASTER_LARB_PORT(M4U_PORT_MFB_RDMA0), 7, SLAVE_LARB(5)),
199 DEFINE_MNODE(img_mfb_rdma1,
200 MASTER_LARB_PORT(M4U_PORT_MFB_RDMA1), 7, SLAVE_LARB(5)),
201 DEFINE_MNODE(img_mfb_rdma2,
202 MASTER_LARB_PORT(M4U_PORT_MFB_RDMA2), 6, SLAVE_LARB(5)),
203 DEFINE_MNODE(img_mfb_rdma3,
204 MASTER_LARB_PORT(M4U_PORT_MFB_RDMA3), 6, SLAVE_LARB(5)),
205 DEFINE_MNODE(img_mfb_wdma,
206 MASTER_LARB_PORT(M4U_PORT_MFB_WDMA), 8, SLAVE_LARB(5)),
207 DEFINE_MNODE(img_reserve1,
208 MASTER_LARB_PORT(M4U_PORT_RESERVE1), 7, SLAVE_LARB(5)),
209 DEFINE_MNODE(img_reserve2,
210 MASTER_LARB_PORT(M4U_PORT_RESERVE2), 7, SLAVE_LARB(5)),
211 DEFINE_MNODE(img_reserve3,
212 MASTER_LARB_PORT(M4U_PORT_RESERVE3), 7, SLAVE_LARB(5)),
213 DEFINE_MNODE(img_reserve4,
214 MASTER_LARB_PORT(M4U_PORT_RESERVE4), 7, SLAVE_LARB(5)),
215 DEFINE_MNODE(img_reserve5,
216 MASTER_LARB_PORT(M4U_PORT_RESERVE5), 7, SLAVE_LARB(5)),
217 DEFINE_MNODE(img_reserve6,
218 MASTER_LARB_PORT(M4U_PORT_RESERVE6), 7, SLAVE_LARB(5)),
219
220 DEFINE_MNODE(ipe_fdvt_rda,
221 MASTER_LARB_PORT(M4U_PORT_FDVT_RDA), 7, SLAVE_LARB(8)),
222 DEFINE_MNODE(ipe_fdvt_rdb,
223 MASTER_LARB_PORT(M4U_PORT_FDVT_RDB), 7, SLAVE_LARB(8)),
224 DEFINE_MNODE(ipe_fdvt_wra,
225 MASTER_LARB_PORT(M4U_PORT_FDVT_WRA), 8, SLAVE_LARB(8)),
226 DEFINE_MNODE(ipe_fdvt_wrb,
227 MASTER_LARB_PORT(M4U_PORT_FDVT_WRB), 8, SLAVE_LARB(8)),
228 DEFINE_MNODE(ipe_fe_rd0,
229 MASTER_LARB_PORT(M4U_PORT_FE_RD0), 7, SLAVE_LARB(8)),
230 DEFINE_MNODE(ipe_fe_rd1,
231 MASTER_LARB_PORT(M4U_PORT_FE_RD1), 7, SLAVE_LARB(8)),
232 DEFINE_MNODE(ipe_fe_wr0,
233 MASTER_LARB_PORT(M4U_PORT_FE_WR0), 8, SLAVE_LARB(8)),
234 DEFINE_MNODE(ipe_fe_wr1,
235 MASTER_LARB_PORT(M4U_PORT_FE_WR1), 8, SLAVE_LARB(8)),
236 DEFINE_MNODE(ipe_rsc_rdma0,
237 MASTER_LARB_PORT(M4U_PORT_RSC_RDMA0), 6, SLAVE_LARB(8)),
238 DEFINE_MNODE(ipe_rsc_wdma,
239 MASTER_LARB_PORT(M4U_PORT_RSC_WDMA), 7, SLAVE_LARB(8)),
240
241 DEFINE_MNODE(cam_imgo_r1_c,
242 MASTER_LARB_PORT(M4U_PORT_CAM_IMGO_R1_C), 8, SLAVE_LARB(9)),
243 DEFINE_MNODE(cam_rrzo_r1_c,
244 MASTER_LARB_PORT(M4U_PORT_CAM_RRZO_R1_C), 8, SLAVE_LARB(9)),
245 DEFINE_MNODE(cam_lsci__r1_c,
246 MASTER_LARB_PORT(M4U_PORT_CAM_LSCI_R1_C), 7, SLAVE_LARB(9)),
247 DEFINE_MNODE(cam_bpci_r1_c,
248 MASTER_LARB_PORT(M4U_PORT_CAM_BPCI_R1_C), 7, SLAVE_LARB(9)),
249 DEFINE_MNODE(cam_yuvo_r1_c,
250 MASTER_LARB_PORT(M4U_PORT_CAM_YUVO_R1_C), 8, SLAVE_LARB(9)),
251 DEFINE_MNODE(cam_ufdi_r2_c,
252 MASTER_LARB_PORT(M4U_PORT_CAM_UFDI_R2_C), 7, SLAVE_LARB(9)),
253 DEFINE_MNODE(cam_rawi_r2_c,
254 MASTER_LARB_PORT(M4U_PORT_CAM_RAWI_R2_C), 7, SLAVE_LARB(9)),
255 DEFINE_MNODE(cam_rawi_r5_c,
256 MASTER_LARB_PORT(M4U_PORT_CAM_RAWI_R5_C), 7, SLAVE_LARB(9)),
257 DEFINE_MNODE(cam_camsv_1,
258 MASTER_LARB_PORT(M4U_PORT_CAM_CAMSV_1), 8, SLAVE_LARB(9)),
259 DEFINE_MNODE(cam_camsv_2,
260 MASTER_LARB_PORT(M4U_PORT_CAM_CAMSV_2), 8, SLAVE_LARB(9)),
261 DEFINE_MNODE(cam_camsv_3,
262 MASTER_LARB_PORT(M4U_PORT_CAM_CAMSV_3), 8, SLAVE_LARB(9)),
263 DEFINE_MNODE(cam_camsv_4,
264 MASTER_LARB_PORT(M4U_PORT_CAM_CAMSV_4), 8, SLAVE_LARB(9)),
265 DEFINE_MNODE(cam_camsv_5,
266 MASTER_LARB_PORT(M4U_PORT_CAM_CAMSV_5), 8, SLAVE_LARB(9)),
267 DEFINE_MNODE(cam_camsv_6,
268 MASTER_LARB_PORT(M4U_PORT_CAM_CAMSV_6), 8, SLAVE_LARB(9)),
269 DEFINE_MNODE(cam_aao_r1_c,
270 MASTER_LARB_PORT(M4U_PORT_CAM_AAO_R1_C), 8, SLAVE_LARB(9)),
271 DEFINE_MNODE(cam_afo_r1_c,
272 MASTER_LARB_PORT(M4U_PORT_CAM_AFO_R1_C), 8, SLAVE_LARB(9)),
273 DEFINE_MNODE(cam_flko_r1_c,
274 MASTER_LARB_PORT(M4U_PORT_CAM_FLKO_R1_C), 8, SLAVE_LARB(9)),
275 DEFINE_MNODE(cam_lceso_r1_c,
276 MASTER_LARB_PORT(M4U_PORT_CAM_LCESO_R1_C), 8, SLAVE_LARB(9)),
277 DEFINE_MNODE(cam_crzo_r1_c,
278 MASTER_LARB_PORT(M4U_PORT_CAM_CRZO_R1_C), 8, SLAVE_LARB(9)),
279 DEFINE_MNODE(cam_ltmso_r1_c,
280 MASTER_LARB_PORT(M4U_PORT_CAM_LTMSO_R1_C), 8, SLAVE_LARB(9)),
281 DEFINE_MNODE(cam_rsso_r1_c,
282 MASTER_LARB_PORT(M4U_PORT_CAM_RSSO_R1_C), 8, SLAVE_LARB(9)),
283 DEFINE_MNODE(cam_ccui,
284 MASTER_LARB_PORT(M4U_PORT_CAM_CCUI), 7, SLAVE_LARB(9)),
285 DEFINE_MNODE(cam_ccuo,
286 MASTER_LARB_PORT(M4U_PORT_CAM_CCUO), 8, SLAVE_LARB(9)),
287 DEFINE_MNODE(cam_fake,
288 MASTER_LARB_PORT(M4U_PORT_CAM_FAKE), 8, SLAVE_LARB(9)),
289
290 DEFINE_MNODE(cam_imgo_r1_a,
291 MASTER_LARB_PORT(M4U_PORT_CAM_IMGO_R1_A), 8, SLAVE_LARB(10)),
292 DEFINE_MNODE(cam_rrzo_r1_a,
293 MASTER_LARB_PORT(M4U_PORT_CAM_RRZO_R1_A), 8, SLAVE_LARB(10)),
294 DEFINE_MNODE(cam_lsci_r1_a,
295 MASTER_LARB_PORT(M4U_PORT_CAM_LSCI_R1_A), 7, SLAVE_LARB(10)),
296 DEFINE_MNODE(cam_bpci_r1_a,
297 MASTER_LARB_PORT(M4U_PORT_CAM_BPCI_R1_A), 7, SLAVE_LARB(10)),
298 DEFINE_MNODE(cam_yuvo_r1_a,
299 MASTER_LARB_PORT(M4U_PORT_CAM_YUVO_R1_A), 8, SLAVE_LARB(10)),
300 DEFINE_MNODE(cam_ufdi_r2_a,
301 MASTER_LARB_PORT(M4U_PORT_CAM_UFDI_R2_A), 7, SLAVE_LARB(10)),
302 DEFINE_MNODE(cam_rawi_r2_a,
303 MASTER_LARB_PORT(M4U_PORT_CAM_RAWI_R2_A), 7, SLAVE_LARB(10)),
304 DEFINE_MNODE(cam_rawi_r5_a,
305 MASTER_LARB_PORT(M4U_PORT_CAM_RAWI_R5_A), 7, SLAVE_LARB(10)),
306 DEFINE_MNODE(cam_imgo_r1_b,
307 MASTER_LARB_PORT(M4U_PORT_CAM_IMGO_R1_B), 8, SLAVE_LARB(10)),
308 DEFINE_MNODE(cam_rrzo_r1_b,
309 MASTER_LARB_PORT(M4U_PORT_CAM_RRZO_R1_B), 8, SLAVE_LARB(10)),
310 DEFINE_MNODE(cam_lsci_r1_b,
311 MASTER_LARB_PORT(M4U_PORT_CAM_LSCI_R1_B), 7, SLAVE_LARB(10)),
312 DEFINE_MNODE(cam_bpci_r1_b,
313 MASTER_LARB_PORT(M4U_PORT_CAM_BPCI_R1_B), 7, SLAVE_LARB(10)),
314 DEFINE_MNODE(cam_yuvo_r1_b,
315 MASTER_LARB_PORT(M4U_PORT_CAM_YUVO_R1_B), 8, SLAVE_LARB(10)),
316 DEFINE_MNODE(cam_ufdi_r2_b,
317 MASTER_LARB_PORT(M4U_PORT_CAM_UFDI_R2_B), 7, SLAVE_LARB(10)),
318 DEFINE_MNODE(cam_rawi_r2_b,
319 MASTER_LARB_PORT(M4U_PORT_CAM_RAWI_R2_B), 7, SLAVE_LARB(10)),
320 DEFINE_MNODE(cam_rawi_r5_b,
321 MASTER_LARB_PORT(M4U_PORT_CAM_RAWI_R5_B), 7, SLAVE_LARB(10)),
322 DEFINE_MNODE(cam_camsv_0,
323 MASTER_LARB_PORT(M4U_PORT_CAM_CAMSV_0), 8, SLAVE_LARB(10)),
324 DEFINE_MNODE(cam_aao_r1_a,
325 MASTER_LARB_PORT(M4U_PORT_CAM_AAO_R1_A), 8, SLAVE_LARB(10)),
326 DEFINE_MNODE(cam_afo_r1_a,
327 MASTER_LARB_PORT(M4U_PORT_CAM_AFO_R1_A), 8, SLAVE_LARB(10)),
328 DEFINE_MNODE(cam_flko_r1_a,
329 MASTER_LARB_PORT(M4U_PORT_CAM_FLKO_R1_A), 8, SLAVE_LARB(10)),
330 DEFINE_MNODE(cam_lceso_r1_a,
331 MASTER_LARB_PORT(M4U_PORT_CAM_LCESO_R1_A), 8, SLAVE_LARB(10)),
332 DEFINE_MNODE(cam_crzo_r1_a,
333 MASTER_LARB_PORT(M4U_PORT_CAM_CRZO_R1_A), 8, SLAVE_LARB(10)),
334 DEFINE_MNODE(cam_aao_r1_b,
335 MASTER_LARB_PORT(M4U_PORT_CAM_AAO_R1_B), 8, SLAVE_LARB(10)),
336 DEFINE_MNODE(cam_afo_r1_b,
337 MASTER_LARB_PORT(M4U_PORT_CAM_AFO_R1_B), 8, SLAVE_LARB(10)),
338 DEFINE_MNODE(cam_flko_r1_b,
339 MASTER_LARB_PORT(M4U_PORT_CAM_FLKO_R1_B), 8, SLAVE_LARB(10)),
340 DEFINE_MNODE(cam_lceso_r1_b,
341 MASTER_LARB_PORT(M4U_PORT_CAM_LCESO_R1_B), 8, SLAVE_LARB(10)),
342 DEFINE_MNODE(cam_crzo_r1_b,
343 MASTER_LARB_PORT(M4U_PORT_CAM_CRZO_R1_B), 8, SLAVE_LARB(10)),
344 DEFINE_MNODE(cam_ltmso_r1_a,
345 MASTER_LARB_PORT(M4U_PORT_CAM_LTMSO_R1_A), 8, SLAVE_LARB(10)),
346 DEFINE_MNODE(cam_rsso_r1_a,
347 MASTER_LARB_PORT(M4U_PORT_CAM_RSSO_R1_A), 8, SLAVE_LARB(10)),
348 DEFINE_MNODE(cam_ltmso_r1_b,
349 MASTER_LARB_PORT(M4U_PORT_CAM_LTMSO_R1_B), 8, SLAVE_LARB(10)),
350 DEFINE_MNODE(cam_rsso_r1_b,
351 MASTER_LARB_PORT(M4U_PORT_CAM_RSSO_R1_B), 8, SLAVE_LARB(10)),
352};
353
354static const char * const comm_muxes_mt6779[] = { "mm" };
355
356static const char * const comm_icc_path_names_mt6779[] = { "mmsys_path" };
357
358static const struct mtk_mmqos_desc mmqos_desc_mt6779 = {
359 .nodes = node_descs_mt6779,
360 .num_nodes = ARRAY_SIZE(node_descs_mt6779),
361 .comm_muxes = comm_muxes_mt6779,
362 .comm_icc_path_names = comm_icc_path_names_mt6779,
363 .max_ratio = 40,
364 .hrt = {
365 .hrt_bw = {1600, 0, 0},
366 .hrt_total_bw = 7466, /* Todo: Use DRAMC API */
367 }
368};
369
370
371static const struct of_device_id mtk_mmqos_mt6779_of_ids[] = {
372 {
373 .compatible = "mediatek,mt6779-mmqos",
374 .data = &mmqos_desc_mt6779,
375 },
376 {}
377};
378MODULE_DEVICE_TABLE(of, mtk_mmqos_mt6779_of_ids);
379
380static struct platform_driver mtk_mmqos_mt6779_driver = {
381 .probe = mtk_mmqos_probe,
382 .remove = mtk_mmqos_remove,
383 .driver = {
384 .name = "mtk-mt6779-mmqos",
385 .of_match_table = mtk_mmqos_mt6779_of_ids,
386 },
387};
388module_platform_driver(mtk_mmqos_mt6779_driver);
389
390MODULE_LICENSE("GPL v2");