blob: 6883762ad7cbc61fe4100a7a897892dc0381c117 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +08001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2020 MediaTek Inc.
4 */
5
6#ifndef __DRV_CLK_MTK_H
7#define __DRV_CLK_MTK_H
8/*
9 * This is a private header file. DO NOT include it except clk-*.c.
10 */
11#include <linux/bitops.h>
12#include <linux/clk.h>
13#include <linux/clk-provider.h>
14#define CLK_DEBUG 0
15#define DUMMY_REG_TEST 0
16/* #define Bring_Up */
17#ifdef Bring_Up
18#ifdef pr_debug
19#undef pr_debug
20#define pr_debug pr_warn
21#endif
22#define MT_CCF_DEBUG 1
23#define MT_CCF_BRINGUP 0 /* 1: only for bring up */
24#endif /* Bring_Up */
25extern spinlock_t *get_mtk_clk_lock(void);
26extern spinlock_t *get_mtk_mtcmos_lock(void);
27#define mtk_clk_lock(flags) spin_lock_irqsave(get_mtk_clk_lock(), flags)
28#define mtk_clk_unlock(flags) \
29 spin_unlock_irqrestore(get_mtk_clk_lock(), flags)
30#define mtk_mtcmos_lock(flags) spin_lock_irqsave(get_mtk_mtcmos_lock(), flags)
31#define mtk_mtcmos_unlock(flags) \
32 spin_unlock_irqrestore(get_mtk_mtcmos_lock(), flags)
33#define MAX_MUX_GATE_BIT 31
34#define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
35#if 0
36struct clk *mtk_clk_register_mux(
37 const char *name,
38 const char **parent_names,
39 u8 num_parents,
40 void __iomem *base_addr,
41 u8 shift,
42 u8 width,
43 u8 gate_bit);
44#endif
45#endif /* __DRV_CLK_MTK_H */