| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2020 MediaTek Inc. |
| 4 | */ |
| 5 | |
| 6 | |
| 7 | #ifndef __DRV_CLKDBG_MT6880_H |
| 8 | #define __DRV_CLKDBG_MT6880_H |
| 9 | |
| 10 | enum dbg_sys_id { |
| 11 | top, |
| 12 | dbgsys_dem, |
| 13 | ifrao, |
| 14 | infracfg_ao_bus, |
| 15 | peri, |
| 16 | spm, |
| 17 | apmixed, |
| 18 | gce, |
| 19 | audsys, |
| 20 | impe, |
| 21 | mfgcfg, |
| 22 | mm, |
| 23 | dbg_sys_num, |
| 24 | }; |
| 25 | |
| 26 | extern void subsys_if_on(void); |
| 27 | |
| 28 | extern unsigned int mt_get_ckgen_freq(unsigned int ID); |
| 29 | |
| 30 | /*ram console api*/ |
| 31 | #ifdef CONFIG_MTK_RAM_CONSOLE |
| 32 | extern void aee_rr_rec_clk(int id, u32 val); |
| 33 | #endif |
| 34 | |
| 35 | extern const char * const *get_mt6880_all_clk_names(void); |
| 36 | extern void print_enabled_clks_once(void); |
| 37 | extern void print_subsys_reg(enum dbg_sys_id id); |
| 38 | |
| 39 | #endif /* __DRV_CLKDBG_MT6758_H */ |