| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2019 MediaTek Inc. |
| 4 | */ |
| 5 | |
| 6 | #ifndef MET_POWER |
| 7 | #define MET_POWER |
| 8 | |
| 9 | enum { |
| 10 | _PM_QOS_RESERVED = 0, |
| 11 | _PM_QOS_CPU_DMA_LATENCY, |
| 12 | _PM_QOS_NETWORK_LATENCY, |
| 13 | _PM_QOS_NETWORK_THROUGHPUT, |
| 14 | _PM_QOS_MEMORY_BANDWIDTH, |
| 15 | |
| 16 | _PM_QOS_CPU_MEMORY_BANDWIDTH, |
| 17 | _PM_QOS_GPU_MEMORY_BANDWIDTH, |
| 18 | _PM_QOS_MM_MEMORY_BANDWIDTH, |
| 19 | _PM_QOS_OTHER_MEMORY_BANDWIDTH, |
| 20 | _PM_QOS_MM0_BANDWIDTH_LIMITER, |
| 21 | _PM_QOS_MM1_BANDWIDTH_LIMITER, |
| 22 | |
| 23 | _PM_QOS_DDR_OPP, |
| 24 | _PM_QOS_VCORE_OPP, |
| 25 | _PM_QOS_SCP_VCORE_REQUEST, |
| 26 | _PM_QOS_POWER_MODEL_DDR_REQUEST, |
| 27 | _PM_QOS_POWER_MODEL_VCORE_REQUEST, |
| 28 | _PM_QOS_VCORE_DVFS_FORCE_OPP, |
| 29 | |
| 30 | _PM_QOS_DISP_FREQ, |
| 31 | _PM_QOS_MDP_FREQ, |
| 32 | _PM_QOS_VDEC_FREQ, |
| 33 | _PM_QOS_VENC_FREQ, |
| 34 | _PM_QOS_IMG_FREQ, |
| 35 | _PM_QOS_CAM_FREQ, |
| 36 | _PM_QOS_VVPU_OPP, |
| 37 | _PM_QOS_VMDLA_OPP, |
| 38 | _PM_QOS_ISP_HRT_BANDWIDTH, |
| 39 | _PM_QOS_APU_MEMORY_BANDWIDTH, |
| 40 | /* insert new class ID */ |
| 41 | _PM_QOS_NUM_CLASSES, |
| 42 | }; |
| 43 | /* Action requested to pm_qos_update_target */ |
| 44 | enum _pm_qos_req_action { |
| 45 | _PM_QOS_ADD_REQ, /* Add a new request */ |
| 46 | _PM_QOS_UPDATE_REQ, /* Update an existing request */ |
| 47 | _PM_QOS_REMOVE_REQ /* Remove an existing request */ |
| 48 | }; |
| 49 | |
| 50 | extern void pm_qos_update_request(int pm_qos_class, s32 value); |
| 51 | extern void pm_qos_update_target(unsigned int action, int prev_value, int curr_value); |
| 52 | |
| 53 | #endif /* MET_DRV */ |
| 54 | |