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192.168.1.100 / T800 / 2f45a6900d5d100dd4c723c7ff44bf5a8471665d / . / src / kernel / linux / v4.19 / drivers / usb / host / xhci-mtk.h
blob: cc59d80b663b47513bca11a37c8c4a1c744c696f [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author:
5 * Zhigang.Wei <zhigang.wei@mediatek.com>
6 * Chunfeng.Yun <chunfeng.yun@mediatek.com>
7 */
8
9#ifndef _XHCI_MTK_H_
10#define _XHCI_MTK_H_
11
12#include "xhci.h"
13
14/**
15 * To simplify scheduler algorithm, set a upper limit for ESIT,
16 * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
17 * round down to the limit value, that means allocating more
18 * bandwidth to it.
19 */
20#define XHCI_MTK_MAX_ESIT 64
21
22/**
23 * struct mu3h_sch_bw_info: schedule information for bandwidth domain
24 *
25 * @bus_bw: array to keep track of bandwidth already used at each uframes
26 * @bw_ep_list: eps in the bandwidth domain
27 *
28 * treat a HS root port as a bandwidth domain, but treat a SS root port as
29 * two bandwidth domains, one for IN eps and another for OUT eps.
30 */
31struct mu3h_sch_bw_info {
32 u32 bus_bw[XHCI_MTK_MAX_ESIT];
33 struct list_head bw_ep_list;
34};
35
36/**
37 * struct mu3h_sch_ep_info: schedule information for endpoint
38 *
39 * @esit: unit is 125us, equal to 2 << Interval field in ep-context
40 * @num_budget_microframes: number of continuous uframes
41 * (@repeat==1) scheduled within the interval
42 * @bw_cost_per_microframe: bandwidth cost per microframe
43 * @endpoint: linked into bandwidth domain which it belongs to
44 * @ep: address of usb_host_endpoint struct
45 * @offset: which uframe of the interval that transfer should be
46 * scheduled first time within the interval
47 * @repeat: the time gap between two uframes that transfers are
48 * scheduled within a interval. in the simple algorithm, only
49 * assign 0 or 1 to it; 0 means using only one uframe in a
50 * interval, and 1 means using @num_budget_microframes
51 * continuous uframes
52 * @pkts: number of packets to be transferred in the scheduled uframes
53 * @cs_count: number of CS that host will trigger
54 * @burst_mode: burst mode for scheduling. 0: normal burst mode,
55 * distribute the bMaxBurst+1 packets for a single burst
56 * according to @pkts and @repeat, repeate the burst multiple
57 * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
58 * according to @pkts and @repeat. normal mode is used by
59 * default
60 */
61struct mu3h_sch_ep_info {
62 u32 esit;
63 u32 num_budget_microframes;
64 u32 bw_cost_per_microframe;
65 struct list_head endpoint;
66 void *ep;
67 /*
68 * mtk xHCI scheduling information put into reserved DWs
69 * in ep context
70 */
71 u32 offset;
72 u32 repeat;
73 u32 pkts;
74 u32 cs_count;
75 u32 burst_mode;
76};
77
78#define MU3C_U3_PORT_MAX 4
79#define MU3C_U2_PORT_MAX 5
80
81/**
82 * struct mu3c_ippc_regs: MTK ssusb ip port control registers
83 * @ip_pw_ctr0~3: ip power and clock control registers
84 * @ip_pw_sts1~2: ip power and clock status registers
85 * @ip_xhci_cap: ip xHCI capability register
86 * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
87 * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
88 * @u2_phy_pll: usb2 phy pll control register
89 */
90struct mu3c_ippc_regs {
91 __le32 ip_pw_ctr0;
92 __le32 ip_pw_ctr1;
93 __le32 ip_pw_ctr2;
94 __le32 ip_pw_ctr3;
95 __le32 ip_pw_sts1;
96 __le32 ip_pw_sts2;
97 __le32 reserved0[3];
98 __le32 ip_xhci_cap;
99 __le32 reserved1[2];
100 __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
101 __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
102 __le32 reserved2;
103 __le32 u2_phy_pll;
104 __le32 reserved3[33]; /* 0x80 ~ 0xff */
105};
106
107struct xhci_hcd_mtk {
108 struct device *dev;
109 struct usb_hcd *hcd;
110 struct mu3h_sch_bw_info *sch_array;
111 struct mu3c_ippc_regs __iomem *ippc_regs;
112 bool has_ippc;
113 int num_u2_ports;
114 int num_u3_ports;
115 int u3p_dis_msk;
116 struct regulator *vusb33;
117 struct regulator *vbus;
118 struct clk *sys_clk; /* sys and mac clock */
119 struct clk *ref_clk;
120 struct clk *mcu_clk;
121 struct clk *dma_clk;
122 struct regmap *pericfg;
123 struct phy **phys;
124 int num_phys;
125 bool lpm_support;
126 /* usb remote wakeup */
127 bool uwk_en;
128 struct regmap *uwk;
129 u32 uwk_reg_base;
130 u32 uwk_vers;
131};
132
133static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
134{
135 return dev_get_drvdata(hcd->self.controller);
136}
137
138#if IS_ENABLED(CONFIG_USB_XHCI_MTK)
139int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
140void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
141int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
142 struct usb_host_endpoint *ep);
143void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
144 struct usb_host_endpoint *ep);
145
146#else
147static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd,
148 struct usb_device *udev, struct usb_host_endpoint *ep)
149{
150 return 0;
151}
152
153static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd,
154 struct usb_device *udev, struct usb_host_endpoint *ep)
155{
156}
157
158#endif
159
160#endif /* _XHCI_MTK_H_ */