| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> |
| 3 | * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com> |
| 4 | * Copyright (C) 2002 ARM Ltd. |
| 5 | * All Rights Reserved |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | #include <linux/io.h> |
| 12 | #include <linux/delay.h> |
| 13 | #include <linux/of.h> |
| 14 | #include <linux/of_address.h> |
| 15 | |
| 16 | #include <asm/cacheflush.h> |
| 17 | #include <asm/cp15.h> |
| 18 | #include <asm/smp_plat.h> |
| 19 | #include <asm/smp_scu.h> |
| 20 | |
| 21 | extern void ox820_secondary_startup(void); |
| 22 | extern void ox820_cpu_die(unsigned int cpu); |
| 23 | |
| 24 | static void __iomem *cpu_ctrl; |
| 25 | static void __iomem *gic_cpu_ctrl; |
| 26 | |
| 27 | #define HOLDINGPEN_CPU_OFFSET 0xc8 |
| 28 | #define HOLDINGPEN_LOCATION_OFFSET 0xc4 |
| 29 | |
| 30 | #define GIC_NCPU_OFFSET(cpu) (0x100 + (cpu)*0x100) |
| 31 | #define GIC_CPU_CTRL 0x00 |
| 32 | #define GIC_CPU_CTRL_ENABLE 1 |
| 33 | |
| 34 | int __init ox820_boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 35 | { |
| 36 | /* |
| 37 | * Write the address of secondary startup into the |
| 38 | * system-wide flags register. The BootMonitor waits |
| 39 | * until it receives a soft interrupt, and then the |
| 40 | * secondary CPU branches to this address. |
| 41 | */ |
| 42 | writel(virt_to_phys(ox820_secondary_startup), |
| 43 | cpu_ctrl + HOLDINGPEN_LOCATION_OFFSET); |
| 44 | |
| 45 | writel(cpu, cpu_ctrl + HOLDINGPEN_CPU_OFFSET); |
| 46 | |
| 47 | /* |
| 48 | * Enable GIC cpu interface in CPU Interface Control Register |
| 49 | */ |
| 50 | writel(GIC_CPU_CTRL_ENABLE, |
| 51 | gic_cpu_ctrl + GIC_NCPU_OFFSET(cpu) + GIC_CPU_CTRL); |
| 52 | |
| 53 | /* |
| 54 | * Send the secondary CPU a soft interrupt, thereby causing |
| 55 | * the boot monitor to read the system wide flags register, |
| 56 | * and branch to the address found there. |
| 57 | */ |
| 58 | arch_send_wakeup_ipi_mask(cpumask_of(cpu)); |
| 59 | |
| 60 | return 0; |
| 61 | } |
| 62 | |
| 63 | static void __init ox820_smp_prepare_cpus(unsigned int max_cpus) |
| 64 | { |
| 65 | struct device_node *np; |
| 66 | void __iomem *scu_base; |
| 67 | |
| 68 | np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-scu"); |
| 69 | scu_base = of_iomap(np, 0); |
| 70 | of_node_put(np); |
| 71 | if (!scu_base) |
| 72 | return; |
| 73 | |
| 74 | /* Remap CPU Interrupt Interface Registers */ |
| 75 | np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-gic"); |
| 76 | gic_cpu_ctrl = of_iomap(np, 1); |
| 77 | of_node_put(np); |
| 78 | if (!gic_cpu_ctrl) |
| 79 | goto unmap_scu; |
| 80 | |
| 81 | np = of_find_compatible_node(NULL, NULL, "oxsemi,ox820-sys-ctrl"); |
| 82 | cpu_ctrl = of_iomap(np, 0); |
| 83 | of_node_put(np); |
| 84 | if (!cpu_ctrl) |
| 85 | goto unmap_scu; |
| 86 | |
| 87 | scu_enable(scu_base); |
| 88 | flush_cache_all(); |
| 89 | |
| 90 | unmap_scu: |
| 91 | iounmap(scu_base); |
| 92 | } |
| 93 | |
| 94 | static const struct smp_operations ox820_smp_ops __initconst = { |
| 95 | .smp_prepare_cpus = ox820_smp_prepare_cpus, |
| 96 | .smp_boot_secondary = ox820_boot_secondary, |
| 97 | #ifdef CONFIG_HOTPLUG_CPU |
| 98 | .cpu_die = ox820_cpu_die, |
| 99 | #endif |
| 100 | }; |
| 101 | |
| 102 | CPU_METHOD_OF_DECLARE(ox820_smp, "oxsemi,ox820-smp", &ox820_smp_ops); |