| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2019 MediaTek Inc. |
| 4 | */ |
| 5 | |
| 6 | #ifndef _CPU_DSU_H_ |
| 7 | #define _CPU_DSU_H_ |
| 8 | |
| 9 | #include <linux/device.h> |
| 10 | |
| 11 | #define MODE_DISABLED 0 |
| 12 | #define MODE_INTERRUPT 1 |
| 13 | #define MODE_POLLING 2 |
| 14 | |
| 15 | #define MXNR_CPU NR_CPUS |
| 16 | |
| 17 | #define MXNR_DSU_EVENTS 8 /* max number of pmu counter for armv8 is 6+1 */ |
| 18 | struct met_dsu { |
| 19 | unsigned char mode; |
| 20 | unsigned short event; |
| 21 | unsigned long freq; |
| 22 | struct kobject *kobj_cpu_dsu; |
| 23 | }; |
| 24 | |
| 25 | struct cpu_dsu_hw { |
| 26 | const char *name; |
| 27 | int nr_cnt; |
| 28 | int (*check_event)(struct met_dsu *pmu, int idx, int event); |
| 29 | void (*start)(struct met_dsu *pmu, int count); |
| 30 | void (*stop)(int count); |
| 31 | unsigned int (*polling)(struct met_dsu *pmu, int count, unsigned int *pmu_value); |
| 32 | struct met_dsu *pmu; |
| 33 | int event_count; |
| 34 | }; |
| 35 | |
| 36 | |
| 37 | struct cpu_dsu_hw *cpu_dsu_hw_init(void); |
| 38 | |
| 39 | |
| 40 | |
| 41 | #endif /* _CPU_DSU_H_ */ |