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192.168.1.100 / T800 / 4df0b51fe88b5a322114304ccc36f1b5d6f3df06 / . / src / kernel / linux / v4.19 / drivers / clk / mediatek / clk-mt6880-mm.c
blob: 7cc1f1d94f3837ba7c6c9b7eaa51b5420f3ce944 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2
3/*
4
5 * Copyright (c) 2019 MediaTek Inc.
6
7 */
8
9
10#include <linux/clk-provider.h>
11#include <linux/platform_device.h>
12
13#include "clk-mtk.h"
14#include "clk-gate.h"
15
16#include <dt-bindings/clock/mt6880-clk.h>
17
18#define MT_CLKMGR_MODULE_INIT 0
19
20#define MT_CCF_BRINGUP 1
21
22#define INV_OFS -1
23
24
25
26static const struct mtk_gate_regs mm_cg_regs = {
27 .set_ofs = 0x104,
28 .clr_ofs = 0x108,
29 .sta_ofs = 0x100,
30};
31
32#define GATE_MM(_id, _name, _parent, _shift) { \
33 .id = _id, \
34 .name = _name, \
35 .parent_name = _parent, \
36 .regs = &mm_cg_regs, \
37 .shift = _shift, \
38 .ops = &mtk_clk_gate_ops_setclr, \
39 }
40
41static const struct mtk_gate mm_clks[] = {
42 GATE_MM(CLK_MMSYS_MUTEX0, "mmsys_mutex0",
43 "mm_ck"/* parent */, 0),
44 GATE_MM(CLK_MMSYS_APB_BUS, "mmsys_apb_bus",
45 "mm_ck"/* parent */, 1),
46 GATE_MM(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0",
47 "mm_ck"/* parent */, 2),
48 GATE_MM(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0",
49 "mm_ck"/* parent */, 3),
50 GATE_MM(CLK_MM_MDP_WROT0, "mm_mdp_wrot0",
51 "mm_ck"/* parent */, 4),
52 GATE_MM(CLK_MM_DISP_COLOR0, "mm_disp_color0",
53 "mm_ck"/* parent */, 5),
54 GATE_MM(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0",
55 "mm_ck"/* parent */, 6),
56 GATE_MM(CLK_MM_DISP_AAL0, "mm_disp_aal0",
57 "mm_ck"/* parent */, 7),
58 GATE_MM(CLK_MM_DISP_RDMA0, "mm_disp_rdma0",
59 "mm_ck"/* parent */, 8),
60 GATE_MM(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0",
61 "mm_ck"/* parent */, 9),
62 GATE_MM(CLK_MMSYS_FAKE_ENG0, "mmsys_fake_eng0",
63 "mm_ck"/* parent */, 10),
64 GATE_MM(CLK_MM_DISP_DITHER0, "mm_disp_dither0",
65 "mm_ck"/* parent */, 11),
66 GATE_MM(CLK_MM_DISP_WDMA0, "mm_disp_wdma0",
67 "mm_ck"/* parent */, 12),
68 GATE_MM(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0",
69 "mm_ck"/* parent */, 13),
70 GATE_MM(CLK_MM_DISP_OVL0, "mm_disp_ovl0",
71 "mm_ck"/* parent */, 14),
72 GATE_MM(CLK_MM_DBPI0, "mm_dbpi0",
73 "mm_ck"/* parent */, 15),
74 GATE_MM(CLK_MM_DISP_DSI0, "mm_disp_dsi0",
75 "mm_ck"/* parent */, 16),
76 GATE_MM(CLK_MMSYS_SMI_COMMON, "mmsys_smi_common",
77 "mm_ck"/* parent */, 17),
78};
79
80static int clk_mt6880_mm_probe(struct platform_device *pdev)
81{
82 struct clk_onecell_data *clk_data;
83 int r;
84 struct device_node *node = pdev->dev.of_node;
85
86#if MT_CCF_BRINGUP
87 pr_notice("%s init begin\n", __func__);
88#endif
89
90 clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
91
92 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
93 clk_data);
94
95 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
96
97 if (r)
98 pr_err("%s(): could not register clock provider: %d\n",
99 __func__, r);
100
101#if MT_CCF_BRINGUP
102 pr_notice("%s init end\n", __func__);
103#endif
104
105 return r;
106}
107
108static const struct of_device_id of_match_clk_mt6880_mm[] = {
109 { .compatible = "mediatek,mt6880-mmsys_config", },
110 {}
111};
112
113#if MT_CLKMGR_MODULE_INIT
114
115static struct platform_driver clk_mt6880_mm_drv = {
116 .probe = clk_mt6880_mm_probe,
117 .driver = {
118 .name = "clk-mt6880-mm",
119 .of_match_table = of_match_clk_mt6880_mm,
120 },
121};
122
123builtin_platform_driver(clk_mt6880_mm_drv);
124
125#else
126
127static struct platform_driver clk_mt6880_mm_drv = {
128 .probe = clk_mt6880_mm_probe,
129 .driver = {
130 .name = "clk-mt6880-mm",
131 .of_match_table = of_match_clk_mt6880_mm,
132 },
133};
134static int __init clk_mt6880_mm_platform_init(void)
135{
136 return platform_driver_register(&clk_mt6880_mm_drv);
137}
138arch_initcall(clk_mt6880_mm_platform_init);
139
140#endif /* MT_CLKMGR_MODULE_INIT */