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192.168.1.100 / T800 / 4df0b51fe88b5a322114304ccc36f1b5d6f3df06 / . / src / kernel / linux / v4.19 / drivers / clk / mediatek / clk-mt8168-mm.c
blob: 7ac7f4379e43d3a111c754710ae0edd084792f5d [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 MediaTek Inc.
4 */
5
6#include <linux/clk-provider.h>
7#include <linux/platform_device.h>
8
9#include "clk-mtk.h"
10#include "clk-gate.h"
11
12#include <dt-bindings/clock/mt8168-clk.h>
13
14static const struct mtk_gate_regs mm0_cg_regs = {
15 .set_ofs = 0x104,
16 .clr_ofs = 0x108,
17 .sta_ofs = 0x100,
18};
19
20static const struct mtk_gate_regs mm1_cg_regs = {
21 .set_ofs = 0x114,
22 .clr_ofs = 0x118,
23 .sta_ofs = 0x110,
24};
25
26#define GATE_MM0(_id, _name, _parent, _shift) { \
27 .id = _id, \
28 .name = _name, \
29 .parent_name = _parent, \
30 .regs = &mm0_cg_regs, \
31 .shift = _shift, \
32 .ops = &mtk_clk_gate_ops_setclr, \
33 }
34
35#define GATE_MM1(_id, _name, _parent, _shift) { \
36 .id = _id, \
37 .name = _name, \
38 .parent_name = _parent, \
39 .regs = &mm1_cg_regs, \
40 .shift = _shift, \
41 .ops = &mtk_clk_gate_ops_setclr, \
42 }
43
44static const struct mtk_gate mm_clks[] = {
45 /* MM0 */
46 GATE_MM0(CLK_MM_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 0),
47 GATE_MM0(CLK_MM_MM_MDP_CCORR0, "mm_mdp_ccorr0", "mm_sel", 1),
48 GATE_MM0(CLK_MM_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 2),
49 GATE_MM0(CLK_MM_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 3),
50 GATE_MM0(CLK_MM_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 4),
51 GATE_MM0(CLK_MM_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 5),
52 GATE_MM0(CLK_MM_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_sel", 6),
53 GATE_MM0(CLK_MM_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 7),
54 GATE_MM0(CLK_MM_MM_DISP_OVL0_21, "mm_disp_ovl0_21", "mm_sel", 8),
55 GATE_MM0(CLK_MM_MM_DISP_RSZ0, "mm_disp_rsz0", "mm_sel", 9),
56 GATE_MM0(CLK_MM_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 10),
57 GATE_MM0(CLK_MM_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 11),
58 GATE_MM0(CLK_MM_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 12),
59 GATE_MM0(CLK_MM_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 13),
60 GATE_MM0(CLK_MM_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 14),
61 GATE_MM0(CLK_MM_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 15),
62 GATE_MM0(CLK_MM_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 16),
63 GATE_MM0(CLK_MM_MM_DSI0, "mm_dsi0", "mm_sel", 17),
64 GATE_MM0(CLK_MM_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 18),
65 GATE_MM0(CLK_MM_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 19),
66 GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "vpll_dpix", 20),
67 GATE_MM0(CLK_MM_MM_FAKE, "mm_fake", "mm_sel", 21),
68 GATE_MM0(CLK_MM_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 22),
69 GATE_MM0(CLK_MM_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 23),
70 GATE_MM0(CLK_MM_MM_SMI_COMM0, "mm_smi_comm0", "mm_sel", 24),
71 GATE_MM0(CLK_MM_MM_SMI_COMM1, "mm_smi_comm1", "mm_sel", 25),
72 GATE_MM0(CLK_MM_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 26),
73 GATE_MM0(CLK_MM_MM_SMI_IMG, "mm_smi_img", "mm_sel", 27),
74 GATE_MM0(CLK_MM_MM_SMI_CAM, "mm_smi_cam", "mm_sel", 28),
75 GATE_MM0(CLK_MM_IMG_IMG_DL_RELAY, "mm_dl_relay", "mm_sel", 29),
76 GATE_MM0(CLK_MM_IMG_IMG_DL_ASYNC_TOP, "mm_dl_async_top", "mm_sel", 30),
77 GATE_MM0(CLK_MM_DSI0_DIG_DSI, "mm_dsi0_dig_dsi", "dsi0_lntc_dsick", 31),
78 /* MM1 */
79 GATE_MM1(CLK_MM_26M_HRTWT, "mm_f26m_hrtwt", "clk26m_ck", 0),
80 GATE_MM1(CLK_MM_MM_DPI0, "mm_dpi0", "mm_sel", 1),
81 GATE_MM1(CLK_MM_LVDSTX_PXL, "mm_flvdstx_pxl", "vpll_dpix", 2),
82 GATE_MM1(CLK_MM_LVDSTX_CTS, "mm_flvdstx_cts", "lvdstx_dig_cts", 3),
83};
84
85static int clk_mt8168_mm_probe(struct platform_device *pdev)
86{
87 struct clk_onecell_data *clk_data;
88 int r;
89 struct device_node *node = pdev->dev.of_node;
90
91 clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
92
93 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data);
94
95 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
96
97 if (r)
98 pr_err("%s(): could not register clock provider: %d\n",
99 __func__, r);
100
101 return r;
102}
103
104static const struct of_device_id of_match_clk_mt8168_mm[] = {
105 { .compatible = "mediatek,mt8168-mmsys", },
106 {}
107};
108
109static struct platform_driver clk_mt8168_mm_drv = {
110 .probe = clk_mt8168_mm_probe,
111 .driver = {
112 .name = "clk-mt8168-mm",
113 .of_match_table = of_match_clk_mt8168_mm,
114 },
115};
116
117builtin_platform_driver(clk_mt8168_mm_drv);