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192.168.1.100 / T800 / 4df0b51fe88b5a322114304ccc36f1b5d6f3df06 / . / src / kernel / linux / v4.19 / drivers / clk / mediatek / clkdbg-mt2712.c
blob: 685c1465f77312bc719fe38cd28f4ddbefd8d76b [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/io.h>
9
10#include "clkdbg.h"
11
12#define DUMP_INIT_STATE 0
13
14/*
15 * clkdbg dump_regs
16 */
17
18enum {
19 topckgen,
20 infracfg,
21 pericfg,
22 scpsys,
23 apmixed,
24 fhctl,
25 mfgsys,
26 mmsys,
27 imgsys,
28 bdpsys,
29 vdecsys,
30 vencsys,
31 jpgdecsys,
32};
33
34#define REGBASE_V(_phys, _id_name) { .phys = _phys, .name = #_id_name }
35
36/*
37 * checkpatch.pl ERROR:COMPLEX_MACRO
38 *
39 * #define REGBASE(_phys, _id_name) [_id_name] = REGBASE_V(_phys, _id_name)
40 */
41
42static struct regbase rb[] = {
43 [topckgen] = REGBASE_V(0x10000000, topckgen),
44 [infracfg] = REGBASE_V(0x10001000, infracfg),
45 [pericfg] = REGBASE_V(0x10003000, pericfg),
46 [scpsys] = REGBASE_V(0x10006000, scpsys),
47 [apmixed] = REGBASE_V(0x10209000, apmixed),
48 [fhctl] = REGBASE_V(0x10209e00, fhctl),
49 [mfgsys] = REGBASE_V(0x13000000, mfgsys),
50 [mmsys] = REGBASE_V(0x14000000, mmsys),
51 [imgsys] = REGBASE_V(0x15000000, imgsys),
52 [bdpsys] = REGBASE_V(0x15010000, bdpsys),
53 [vdecsys] = REGBASE_V(0x16000000, vdecsys),
54 [vencsys] = REGBASE_V(0x18000000, vencsys),
55 [jpgdecsys] = REGBASE_V(0x19000000, jpgdecsys),
56};
57
58#define REGNAME(_base, _ofs, _name) \
59 { .base = &rb[_base], .ofs = _ofs, .name = #_name }
60
61static struct regname rn[] = {
62 REGNAME(topckgen, 0x040, CLK_CFG_0),
63 REGNAME(topckgen, 0x050, CLK_CFG_1),
64 REGNAME(topckgen, 0x060, CLK_CFG_2),
65 REGNAME(topckgen, 0x070, CLK_CFG_3),
66 REGNAME(topckgen, 0x080, CLK_CFG_4),
67 REGNAME(topckgen, 0x090, CLK_CFG_5),
68 REGNAME(topckgen, 0x0a0, CLK_CFG_6),
69 REGNAME(topckgen, 0x0b0, CLK_CFG_7),
70 REGNAME(topckgen, 0x0c0, CLK_CFG_8),
71 REGNAME(topckgen, 0x0d0, CLK_CFG_9),
72 REGNAME(topckgen, 0x134, CLK_AUDDIV_4),
73 REGNAME(topckgen, 0x500, CLK_CFG_10),
74 REGNAME(topckgen, 0x510, CLK_CFG_11),
75 REGNAME(topckgen, 0x520, CLK_CFG_12),
76 REGNAME(topckgen, 0x530, CLK_CFG_13),
77 REGNAME(topckgen, 0x540, CLK_CFG_14),
78 REGNAME(topckgen, 0x550, CLK_CFG_15),
79 REGNAME(topckgen, 0x560, CLK_CFG_16),
80 REGNAME(topckgen, 0x570, CLK_CFG_17),
81 REGNAME(scpsys, 0x210, SPM_VDE_PWR_CON),
82 REGNAME(scpsys, 0x214, SPM_MFG_PWR_CON),
83 REGNAME(scpsys, 0x230, SPM_VEN_PWR_CON),
84 REGNAME(scpsys, 0x238, SPM_ISP_PWR_CON),
85 REGNAME(scpsys, 0x23c, SPM_DIS_PWR_CON),
86 REGNAME(scpsys, 0x29c, SPM_AUDIO_PWR_CON),
87 REGNAME(scpsys, 0x2cc, SPM_USB_PWR_CON),
88 REGNAME(scpsys, 0x2d4, SPM_USB2_PWR_CON),
89 REGNAME(scpsys, 0x60c, SPM_PWR_STATUS),
90 REGNAME(scpsys, 0x610, SPM_PWR_STATUS_2ND),
91 REGNAME(apmixed, 0x004, AP_PLL_CON1),
92 REGNAME(apmixed, 0x008, AP_PLL_CON2),
93 REGNAME(apmixed, 0x100, ARMCA35PLL_CON0),
94 REGNAME(apmixed, 0x104, ARMCA35PLL_CON1),
95 REGNAME(apmixed, 0x110, ARMCA35PLL_PWR_CON0),
96 REGNAME(apmixed, 0x210, ARMCA72PLL_CON0),
97 REGNAME(apmixed, 0x214, ARMCA72PLL_CON1),
98 REGNAME(apmixed, 0x210, ARMCA72PLL_PWR_CON0),
99 REGNAME(apmixed, 0x230, MAINPLL_CON0),
100 REGNAME(apmixed, 0x234, MAINPLL_CON1),
101 REGNAME(apmixed, 0x23c, MAINPLL_PWR_CON0),
102 REGNAME(apmixed, 0x240, UNIVPLL_CON0),
103 REGNAME(apmixed, 0x244, UNIVPLL_CON1),
104 REGNAME(apmixed, 0x24c, UNIVPLL_PWR_CON0),
105 REGNAME(apmixed, 0x250, MMPLL_CON0),
106 REGNAME(apmixed, 0x254, MMPLL_CON1),
107 REGNAME(apmixed, 0x260, MMPLL_PWR_CON0),
108 REGNAME(apmixed, 0x270, MSDCPLL_CON0),
109 REGNAME(apmixed, 0x274, MSDCPLL_CON1),
110 REGNAME(apmixed, 0x27c, MSDCPLL_PWR_CON0),
111 REGNAME(apmixed, 0x280, VENCPLL_CON0),
112 REGNAME(apmixed, 0x284, VENCPLL_CON1),
113 REGNAME(apmixed, 0x28c, VENCPLL_PWR_CON0),
114 REGNAME(apmixed, 0x290, TVDPLL_CON0),
115 REGNAME(apmixed, 0x294, TVDPLL_CON1),
116 REGNAME(apmixed, 0x29c, TVDPLL_PWR_CON0),
117 REGNAME(apmixed, 0x300, ETHERPLL_CON0),
118 REGNAME(apmixed, 0x304, ETHERPLL_CON1),
119 REGNAME(apmixed, 0x30c, ETHERPLL_PWR_CON0),
120 REGNAME(apmixed, 0x320, VCODECPLL_CON0),
121 REGNAME(apmixed, 0x324, VCODECPLL_CON1),
122 REGNAME(apmixed, 0x32c, VCODECPLL_PWR_CON0),
123 REGNAME(apmixed, 0x330, APLL1_CON0),
124 REGNAME(apmixed, 0x334, APLL1_CON1),
125 REGNAME(apmixed, 0x340, APLL1_PWR_CON0),
126 REGNAME(apmixed, 0x350, APLL2_CON0),
127 REGNAME(apmixed, 0x354, APLL2_CON1),
128 REGNAME(apmixed, 0x360, APLL2_PWR_CON0),
129 REGNAME(apmixed, 0x370, LVDSPLL_CON0),
130 REGNAME(apmixed, 0x374, LVDSPLL_CON1),
131 REGNAME(apmixed, 0x37c, LVDSPLL_PWR_CON0),
132 REGNAME(apmixed, 0x390, LVDSPLL2_CON0),
133 REGNAME(apmixed, 0x394, LVDSPLL2_CON1),
134 REGNAME(apmixed, 0x39c, LVDSPLL2_PWR_CON0),
135 REGNAME(apmixed, 0x410, MSDCPLL2_CON0),
136 REGNAME(apmixed, 0x414, MSDCPLL2_CON1),
137 REGNAME(apmixed, 0x41c, MSDCPLL2_PWR_CON0),
138 REGNAME(topckgen, 0x120, CLK_AUDDIV_0),
139 REGNAME(infracfg, 0x040, INFRA_PDN_STA),
140 REGNAME(pericfg, 0x018, PERI_PDN0_STA),
141 REGNAME(pericfg, 0x01c, PERI_PDN1_STA),
142 REGNAME(pericfg, 0x42c, PERI_MSDC_CLK_EN),
143 REGNAME(mfgsys, 0x000, MFG_CG_STA),
144 REGNAME(mmsys, 0x100, MMSYS_CG0_STA),
145 REGNAME(mmsys, 0x110, MMSYS_CG1_STA),
146 REGNAME(mmsys, 0x220, MMSYS_CG2_STA),
147 REGNAME(imgsys, 0x000, IMG_CG),
148 REGNAME(bdpsys, 0x100, BDP_DISPSYS_CG_CON0),
149 REGNAME(vdecsys, 0x000, VDEC_CKEN_SET),
150 REGNAME(vdecsys, 0x008, VDEC_LARB1_CKEN_STA),
151 REGNAME(vencsys, 0x000, VENC_CG_STA),
152 REGNAME(jpgdecsys, 0x000, JPGDEC_CG_STA),
153 {}
154};
155
156static const struct regname *get_all_regnames(void)
157{
158 return rn;
159}
160
161static void __init init_regbase(void)
162{
163 size_t i;
164
165 for (i = 0; i < ARRAY_SIZE(rb); i++)
166 rb[i].virt = ioremap(rb[i].phys, PAGE_SIZE);
167}
168
169/*
170 * clkdbg fmeter
171 */
172
173#include <linux/delay.h>
174
175#ifndef GENMASK
176#define GENMASK(h, l) (((1U << ((h) - (l) + 1)) - 1) << (l))
177#endif
178
179#define ALT_BITS(o, h, l, v) \
180 (((o) & ~GENMASK(h, l)) | (((v) << (l)) & GENMASK(h, l)))
181
182#define clk_readl(addr) readl(addr)
183#define clk_writel(addr, val) \
184 do { writel(val, addr); wmb(); } while (0) /* sync write */
185#define clk_writel_mask(addr, mask, val) \
186 clk_writel(addr, (clk_readl(addr) & ~(mask)) | (val))
187
188#define ABS_DIFF(a, b) ((a) > (b) ? (a) - (b) : (b) - (a))
189
190#define FMCLK(_t, _i, _n) { .type = _t, .id = _i, .name = _n }
191
192static const struct fmeter_clk fclks[] = {
193 FMCLK(ABIST, 2, "AD_ARMCA35PLL_600M_CORE_CK"),
194 FMCLK(ABIST, 3, "AD_ARMCA35PLL_400M_CORE_CK"),
195 FMCLK(ABIST, 4, "AD_MAIN_H546M_CK"),
196 FMCLK(ABIST, 5, "AD_MAIN_H364M_CK"),
197 FMCLK(ABIST, 6, "AD_MAIN_H218P4M_CK"),
198 FMCLK(ABIST, 7, "AD_MAIN_H156M_CK"),
199 FMCLK(ABIST, 8, "AD_UNIV_178P3M_CK"),
200 FMCLK(ABIST, 9, "AD_UNIVPLL_UNIV_48M_CK"),
201 FMCLK(ABIST, 10, "AD_UNIV_624M_CK"),
202 FMCLK(ABIST, 11, "AD_UNIV_416M_CK"),
203 FMCLK(ABIST, 12, "AD_UNIV_249P6M_CK"),
204 FMCLK(ABIST, 13, "AD_APLL1_CK"),
205 FMCLK(ABIST, 14, "AD_APLL2_CK"),
206 FMCLK(ABIST, 15, "AD_LTEPLL_FS26M_CK"),
207 FMCLK(ABIST, 16, "rtc32k_ck_i"),
208 FMCLK(ABIST, 17, "AD_MMPLL_500M_CK"),
209 FMCLK(ABIST, 18, "AD_VENCPLL_380M_CK"),
210 FMCLK(ABIST, 19, "AD_VCODEPLL_442M_CK"),
211 FMCLK(ABIST, 20, "AD_TVDPLL_572M_CK"),
212 FMCLK(ABIST, 21, "AD_LVDSPLL_150M_CK"),
213 FMCLK(ABIST, 22, "AD_MSDCPLL_400M_CK"),
214 FMCLK(ABIST, 23, "AD_ETHERPLL_50M_CK"),
215 FMCLK(ABIST, 24, "clkph_MCK_o"),
216 FMCLK(ABIST, 25, "AD_USB_48M_CK"),
217 FMCLK(ABIST, 26, "AD_MSDCPLL2_400M_CK"),
218 FMCLK(ABIST, 27, "AD_CVBSADC_CKOUTA"),
219 FMCLK(ABIST, 30, "AD_TVDPLL_429M_CK"),
220 FMCLK(ABIST, 33, "AD_LVDSPLL2_150M_CK"),
221 FMCLK(ABIST, 34, "AD_ETHERPLL_125M_CK"),
222 FMCLK(ABIST, 35, "AD_MIPI_26M_CK_CKSYS"),
223 FMCLK(ABIST, 36, "AD_LTEPLL_ARMPLL26M_CK_CKSYS"),
224 FMCLK(ABIST, 37, "AD_LETPLL_SSUSB26M_CK_CKSYS"),
225 FMCLK(ABIST, 38, "AD_DSI2_LNTC_DSICLK_CKSYS"),
226 FMCLK(ABIST, 39, "AD_DSI3_LNTC_DSICLK_CKSYS"),
227 FMCLK(ABIST, 40, "AD_DSI2_MPPLL_TST_CK_CKSYS"),
228 FMCLK(ABIST, 41, "AD_DSI3_MPPLL_TST_CK_CKSYS"),
229 FMCLK(ABIST, 42, "AD_LVDSTX3_MONCLK"),
230 FMCLK(ABIST, 43, "AD_PLLGP_TST_CK_CKSYS"),
231 FMCLK(ABIST, 44, "AD_SSUSB_48M_CK_CKSYS"),
232 FMCLK(ABIST, 45, "AD_MONREF3_CK"),
233 FMCLK(ABIST, 46, "AD_MONFBK3_CK"),
234 FMCLK(ABIST, 47, "big_clkmon_o"),
235 FMCLK(ABIST, 48, "DA_ARMCPU_MON_CK"),
236 FMCLK(ABIST, 49, "AD_CSI0_LNRC_BYTE_CLK"),
237 FMCLK(ABIST, 50, "AD_CSI1_LNRC_BYTE_CLK"),
238 FMCLK(ABIST, 51, "AD_CSI0_LNRC_4X_CLK"),
239 FMCLK(ABIST, 52, "AD_CSI1_LNRC_4X_CLK"),
240 FMCLK(ABIST, 53, "AD_CSI0_CAL_CLK"),
241 FMCLK(ABIST, 54, "AD_CSI1_CAL_CLK"),
242 FMCLK(ABIST, 55, "AD_UNIVPL_1248M_CK"),
243 FMCLK(ABIST, 56, "AD_MAINPLL_1092_CORE_CK"),
244 FMCLK(ABIST, 57, "AD_ARMCA15PLL_2002M_CORE_CK"),
245 FMCLK(ABIST, 58, "mcusys_arm_clk_out_all"),
246 FMCLK(ABIST, 59, "AD_ARMCA7PLL_1508M_CORE_CK"),
247 FMCLK(ABIST, 61, "AD_UNIVPLL_USB20_48M_CK"),
248 FMCLK(ABIST, 62, "AD_UNIVPLL_USB20_48M_CK1"),
249 FMCLK(ABIST, 63, "AD_UNIVPLL_USB20_48M_CK2"),
250 FMCLK(ABIST, 65, "AD_UNIVPLL_USB20_48M_CK3"),
251 FMCLK(ABIST, 77, "AD_LVDSTX1_MONCLK"),
252 FMCLK(ABIST, 78, "AD_MONREF1_CK"),
253 FMCLK(ABIST, 79, "AD_MONFBK1_CK"),
254 FMCLK(ABIST, 85, "trng_freq_debug_out0"),
255 FMCLK(ABIST, 86, "trng_freq_debug_out1"),
256 FMCLK(ABIST, 87, "AD_DSI0_LNTC_DSICLK_CKSYS"),
257 FMCLK(ABIST, 88, "AD_DSI0_MPLL_TST_CK_CKSYS"),
258 FMCLK(ABIST, 89, "AD_DSI1_LNTC_DSICLK_CKSYS"),
259 FMCLK(ABIST, 90, "AD_DSI1_MPLL_TST_CK_CKSYS"),
260 FMCLK(ABIST, 91, "ddr_clk_freq_meter[0]"),
261 FMCLK(ABIST, 92, "ddr_clk_freq_meter[1]"),
262 FMCLK(ABIST, 93, "ddr_clk_freq_meter[2]"),
263 FMCLK(ABIST, 94, "ddr_clk_freq_meter[3]"),
264 FMCLK(ABIST, 95, "ddr_clk_freq_meter[4]"),
265 FMCLK(ABIST, 96, "ddr_clk_freq_meter[5]"),
266 FMCLK(ABIST, 97, "ddr_clk_freq_meter[6]"),
267 FMCLK(ABIST, 98, "ddr_clk_freq_meter[7]"),
268 FMCLK(ABIST, 99, "ddr_clk_freq_meter[8]"),
269 FMCLK(ABIST, 100, "ddr_clk_freq_meter[9]"),
270 FMCLK(ABIST, 101, "ddr_clk_freq_meter[10]"),
271 FMCLK(ABIST, 102, "ddr_clk_freq_meter[11]"),
272 FMCLK(ABIST, 103, "ddr_clk_freq_meter[12]"),
273 FMCLK(ABIST, 104, "ddr_clk_freq_meter[13]"),
274 FMCLK(ABIST, 105, "ddr_clk_freq_meter[14]"),
275 FMCLK(ABIST, 106, "ddr_clk_freq_meter[15]"),
276 FMCLK(ABIST, 107, "ddr_clk_freq_meter[16]"),
277 FMCLK(ABIST, 108, "ddr_clk_freq_meter[17]"),
278 FMCLK(ABIST, 109, "ddr_clk_freq_meter[18]"),
279 FMCLK(ABIST, 110, "ddr_clk_freq_meter[19]"),
280 FMCLK(ABIST, 111, "ddr_clk_freq_meter[20]"),
281 FMCLK(ABIST, 112, "ddr_clk_freq_meter[21]"),
282 FMCLK(ABIST, 113, "ddr_clk_freq_meter[22]"),
283 FMCLK(ABIST, 114, "ddr_clk_freq_meter[23]"),
284 FMCLK(ABIST, 115, "ddr_clk_freq_meter[24]"),
285 FMCLK(ABIST, 116, "ddr_clk_freq_meter[25]"),
286 FMCLK(ABIST, 117, "ddr_clk_freq_meter[26]"),
287 FMCLK(ABIST, 118, "ddr_clk_freq_meter[27]"),
288 FMCLK(ABIST, 119, "ddr_clk_freq_meter[28]"),
289 FMCLK(ABIST, 120, "ddr_clk_freq_meter[29]"),
290 FMCLK(ABIST, 121, "ddr_clk_freq_meter[30]"),
291 FMCLK(ABIST, 122, "ddr_clk_freq_meter[31]"),
292 FMCLK(ABIST, 123, "ddr_clk_freq_meter[32]"),
293 FMCLK(ABIST, 124, "ddr_clk_freq_meter[33]"),
294 FMCLK(ABIST, 125, "ddr_clk_freq_meter[34]"),
295 FMCLK(CKGEN, 1, "hf_faxi_ck"),
296 FMCLK(CKGEN, 2, "hd_faxi_ck"),
297 FMCLK(CKGEN, 3, "hf_fscam_ck"),
298 FMCLK(CKGEN, 5, "hf_fmm_ck"),
299 FMCLK(CKGEN, 6, "f_fpwm_ck"),
300 FMCLK(CKGEN, 7, "hf_fvdec_ck"),
301 FMCLK(CKGEN, 8, "hf_fvenc_ck"),
302 FMCLK(CKGEN, 9, "hf_fmfg_ck"),
303 FMCLK(CKGEN, 10, "hf_fcamtg_ck"),
304 FMCLK(CKGEN, 11, "f_fuart_ck"),
305 FMCLK(CKGEN, 12, "hf_fspi_ck"),
306 FMCLK(CKGEN, 13, "f_fusb20_ck"),
307 FMCLK(CKGEN, 14, "f_fusb30_ck"),
308 FMCLK(CKGEN, 15, "hf_fmsdc50_0_hclk_ck"),
309 FMCLK(CKGEN, 16, "hf_fmsdc50_0_ck"),
310 FMCLK(CKGEN, 17, "hf_fmsdc30_1_ck"),
311 FMCLK(CKGEN, 18, "hf_fmsdc30_2_ck"),
312 FMCLK(CKGEN, 19, "hf_fmsdc30_3_ck"),
313 FMCLK(CKGEN, 20, "hf_faudio_ck"),
314 FMCLK(CKGEN, 21, "hf_faud_intbus_ck"),
315 FMCLK(CKGEN, 22, "hf_fpmicspi_ck"),
316 FMCLK(CKGEN, 23, "hf_fdpilvds1_ck"),
317 FMCLK(CKGEN, 24, "hf_fatb_ck"),
318 FMCLK(CKGEN, 25, "hf_fnr_ck"),
319 FMCLK(CKGEN, 26, "hf_firda_ck"),
320 FMCLK(CKGEN, 27, "hf_fcci400_ck"),
321 FMCLK(CKGEN, 28, "hf_faud_1_ck"),
322 FMCLK(CKGEN, 29, "hf_faud_2_ck"),
323 FMCLK(CKGEN, 30, "hf_fmem_mfg_in_as_ck"),
324 FMCLK(CKGEN, 31, "hf_faxi_mfg_in_as_ck"),
325 FMCLK(CKGEN, 32, "f_frtc_ck"),
326 FMCLK(CKGEN, 33, "f_f26m_ck"),
327 FMCLK(CKGEN, 34, "f_f32k_md1_ck"),
328 FMCLK(CKGEN, 35, "f_frtc_conn_ck"),
329 FMCLK(CKGEN, 36, "hg_fmipicfg_ck"),
330 FMCLK(CKGEN, 37, "hd_haxi_nli_ck"),
331 FMCLK(CKGEN, 38, "hd_qaxidcm_ck"),
332 FMCLK(CKGEN, 39, "f_ffpc_ck"),
333 FMCLK(CKGEN, 40, "f_fckbus_ck_scan"),
334 FMCLK(CKGEN, 41, "f_fckrtc_ck_scan"),
335 FMCLK(CKGEN, 42, "hf_flvds_pxl_ck"),
336 FMCLK(CKGEN, 43, "hf_flvds_cts_ck"),
337 FMCLK(CKGEN, 44, "hf_fdpilvds_ck"),
338 FMCLK(CKGEN, 45, "hf_flvds1_pxl_ck"),
339 FMCLK(CKGEN, 46, "hf_flvds1_cts_ck"),
340 FMCLK(CKGEN, 47, "hf_fhdcp_ck"),
341 FMCLK(CKGEN, 48, "hf_fmsdc50_3_hclk_ck"),
342 FMCLK(CKGEN, 49, "hf_fhdcp_24m_ck"),
343 FMCLK(CKGEN, 50, "hf_fmsdc0p_aes_ck"),
344 FMCLK(CKGEN, 51, "hf_fgcpu_ck"),
345 FMCLK(CKGEN, 52, "hf_fmem_ck"),
346 FMCLK(CKGEN, 53, "hf_fi2so1_mck"),
347 FMCLK(CKGEN, 54, "hf_fcam2tg_ck"),
348 FMCLK(CKGEN, 55, "hf_fether_125m_ck"),
349 FMCLK(CKGEN, 56, "hf_fapll2_ck"),
350 FMCLK(CKGEN, 57, "hf_fa2sys_hp_ck"),
351 FMCLK(CKGEN, 58, "hf_fasm_l_ck"),
352 FMCLK(CKGEN, 59, "hf_fspislv_ck"),
353 FMCLK(CKGEN, 60, "hf_ftdmo1_mck"),
354 FMCLK(CKGEN, 61, "hf_fasm_h_ck"),
355 FMCLK(CKGEN, 62, "hf_ftdmo0_mck"),
356 FMCLK(CKGEN, 63, "hf_fa1sys_hp_ck"),
357 FMCLK(CKGEN, 65, "hf_fasm_m_ck"),
358 FMCLK(CKGEN, 66, "hf_fapll_ck"),
359 FMCLK(CKGEN, 67, "hf_fspinor_ck"),
360 FMCLK(CKGEN, 68, "hf_fpe2_mac_p0_ck"),
361 FMCLK(CKGEN, 69, "hf_fjpgdec_ck"),
362 FMCLK(CKGEN, 70, "hf_fpwm_infra_ck"),
363 FMCLK(CKGEN, 71, "hf_fnfiecc_ck"),
364 FMCLK(CKGEN, 72, "hf_fether_50m_rmii_ck"),
365 FMCLK(CKGEN, 73, "hf_fi2c_ck"),
366 FMCLK(CKGEN, 74, "hf_fcmsys_ck"),
367 FMCLK(CKGEN, 75, "hf_fpe2_mac_p1_ck"),
368 FMCLK(CKGEN, 76, "hf_fdi_ck"),
369 FMCLK(CKGEN, 77, "hf_fi2si3_mck"),
370 FMCLK(CKGEN, 78, "hf_fether_50m_ck"),
371 FMCLK(CKGEN, 79, "hf_fi2si2_mck"),
372 FMCLK(CKGEN, 80, "hf_fi2so3_mck"),
373 FMCLK(CKGEN, 81, "hf_ftvd_ck"),
374 FMCLK(CKGEN, 82, "hf_fnfi2x_ck"),
375 FMCLK(CKGEN, 83, "hf_fi2si1_mck"),
376 FMCLK(CKGEN, 84, "hf_fi2so2_mck"),
377 {}
378};
379
380#define FHCTL_HP_EN (rb[fhctl].virt + 0x000)
381#define CLK_CFG_M0 (rb[topckgen].virt + 0x100)
382#define CLK_CFG_M1 (rb[topckgen].virt + 0x104)
383#define CLK_MISC_CFG_1 (rb[topckgen].virt + 0x214)
384#define CLK_MISC_CFG_2 (rb[topckgen].virt + 0x218)
385#define CLK26CALI_0 (rb[topckgen].virt + 0x220)
386#define CLK26CALI_1 (rb[topckgen].virt + 0x224)
387#define CLK26CALI_2 (rb[topckgen].virt + 0x228)
388#define PLL_TEST_CON0 (rb[apmixed].virt + 0x040)
389#define CVBSPLL_CON1 (rb[apmixed].virt + 0x314)
390#define CVBSREFPLL_CON1 (rb[apmixed].virt + 0x31c)
391
392#define RG_FRMTR_WINDOW 1023U
393
394static void set_fmeter_divider_ca35(u32 k1)
395{
396 u32 val = clk_readl(CLK_MISC_CFG_1);
397
398 val = ALT_BITS(val, 15, 8, k1);
399 clk_writel(CLK_MISC_CFG_1, val);
400}
401
402static void set_fmeter_divider_ca72(u32 k1)
403{
404 u32 val = clk_readl(CLK_MISC_CFG_2);
405
406 val = ALT_BITS(val, 7, 0, k1);
407 clk_writel(CLK_MISC_CFG_2, val);
408}
409
410static void set_fmeter_divider(u32 k1)
411{
412 u32 val = clk_readl(CLK_MISC_CFG_1);
413
414 val = ALT_BITS(val, 7, 0, k1);
415 val = ALT_BITS(val, 31, 24, k1);
416 clk_writel(CLK_MISC_CFG_1, val);
417}
418
419static u8 wait_fmeter_done(u32 tri_bit)
420{
421 static int max_wait_count;
422 int wait_count = (max_wait_count > 0) ? (max_wait_count * 2 + 2) : 100;
423 int i;
424
425 /* wait fmeter */
426 for (i = 0; i < wait_count &&
427 (clk_readl(CLK26CALI_0) & tri_bit) != 0U; i++)
428 udelay(20);
429
430 if ((clk_readl(CLK26CALI_0) & tri_bit) == 0U) {
431 max_wait_count = max(max_wait_count, i);
432 return 1;
433 }
434
435 return 0;
436}
437
438static u32 fmeter_freq(enum FMETER_TYPE type, u32 k1, u32 clk)
439{
440 void __iomem *clk_cfg_reg = (type == CKGEN) ? CLK_CFG_M1 : CLK_CFG_M0;
441 void __iomem *cnt_reg = (type == CKGEN) ? CLK26CALI_2 : CLK26CALI_1;
442 u32 cksw_mask = (type == CKGEN) ? GENMASK(22, 16) : GENMASK(14, 8);
443 u32 cksw_val = (type == CKGEN) ? (clk << 16) : (clk << 8);
444 u32 tri_bit = (type == CKGEN) ? BIT(4) : BIT(0);
445 u32 clk_exc = (type == CKGEN) ? BIT(5) : BIT(2);
446 u32 clk_misc_cfg_1, clk_misc_cfg_2, clk_cfg_val, cnt, freq = 0;
447
448 /* setup fmeter */
449 clk_setl(CLK26CALI_0, BIT(7)); /* enable fmeter_en */
450 clk_clrl(CLK26CALI_0, clk_exc); /* set clk_exc */
451 /* load_cnt */
452 clk_writel_mask(cnt_reg, GENMASK(25, 16), RG_FRMTR_WINDOW << 16);
453
454 /* backup CLK_MISC_CFG_1 value */
455 clk_misc_cfg_1 = clk_readl(CLK_MISC_CFG_1);
456 /* backup CLK_MISC_CFG_2 value */
457 clk_misc_cfg_2 = clk_readl(CLK_MISC_CFG_2);
458 /* backup clk_cfg_reg value */
459 clk_cfg_val = clk_readl(clk_cfg_reg);
460
461 set_fmeter_divider(k1); /* set divider (0 = /1) */
462 set_fmeter_divider_ca35(k1);
463 set_fmeter_divider_ca72(k1);
464 /* select cksw */
465 clk_writel_mask(clk_cfg_reg, cksw_mask, cksw_val);
466
467 clk_setl(CLK26CALI_0, tri_bit); /* start fmeter */
468
469 if (wait_fmeter_done(tri_bit) == 1U) {
470 cnt = clk_readl(cnt_reg) & 0xFFFF;
471 /* (KHz) ; freq = counter * 26M / 1024 */
472 freq = (cnt * 26000U) * (k1 + 1U) / (RG_FRMTR_WINDOW + 1U);
473 }
474
475 /* restore register settings */
476 clk_writel(clk_cfg_reg, clk_cfg_val);
477 clk_writel(CLK_MISC_CFG_2, clk_misc_cfg_2);
478 clk_writel(CLK_MISC_CFG_1, clk_misc_cfg_1);
479
480 clk_clrl(CLK26CALI_0, BIT(7)); /* disable fmeter_en */
481
482 return freq;
483}
484
485static u32 measure_stable_fmeter_freq(enum FMETER_TYPE type, u32 k1, u32 clk)
486{
487 u32 last_freq = 0;
488 u32 freq = fmeter_freq(type, k1, clk);
489 u32 maxfreq = max(freq, last_freq);
490
491 while (maxfreq != 0U &&
492 ABS_DIFF(freq, last_freq) * 100U / maxfreq > 10U) {
493 last_freq = freq;
494 freq = fmeter_freq(type, k1, clk);
495 maxfreq = max(freq, last_freq);
496 }
497
498 return freq;
499}
500
501static const struct fmeter_clk *get_all_fmeter_clks(void)
502{
503 return fclks;
504}
505
506struct bak {
507 u32 fhctl_hp_en;
508};
509
510static void *prepare_fmeter(void)
511{
512 static struct bak regs;
513
514 regs.fhctl_hp_en = clk_readl(FHCTL_HP_EN);
515
516 clk_writel(FHCTL_HP_EN, 0x0); /* disable PLL hopping */
517 udelay(10);
518
519 /* use AD_PLLGP_TST_CK_CKSYS to measure CVBSPLL */
520 /* [9:8]:TST_SEL, [3:0]:TSTOD_EN, A2DCK_EN, TSTCK_EN, TST_EN */
521 clk_setl(PLL_TEST_CON0, 0x30F);
522 /* [4]:CVBS_MONCK_EN, [3:0]:CVBSREFPLL_TESTMUX */
523 clk_setl(CVBSREFPLL_CON1, 0x11);
524 clk_setl(CVBSPLL_CON1, 0x20); /* [5]: CVBSPLL_MONCK_EN */
525
526 return &regs;
527}
528
529static void unprepare_fmeter(void *data)
530{
531 struct bak *regs = data;
532
533 /* [9:8]:TST_SEL, [3:0]:TSTOD_EN, A2DCK_EN, TSTCK_EN, TST_EN */
534 clk_clrl(PLL_TEST_CON0, 0x30F);
535 /* [4]:CVBS_MONCK_EN, [3:0]:CVBSREFPLL_TESTMUX */
536 clk_clrl(CVBSREFPLL_CON1, 0x11);
537 clk_clrl(CVBSPLL_CON1, 0x20); /* [5]: CVBSPLL_MONCK_EN */
538
539 /* restore old setting */
540 clk_writel(FHCTL_HP_EN, regs->fhctl_hp_en);
541}
542
543static u32 fmeter_freq_op(const struct fmeter_clk *fclk)
544{
545 if (fclk->type != FT_NULL)
546 return measure_stable_fmeter_freq(fclk->type, 0, fclk->id);
547
548 return 0;
549}
550
551/*
552 * clkdbg dump_state
553 */
554
555static const char * const *get_all_clk_names(void)
556{
557 static const char * const clks[] = {
558 /* plls */
559 "mainpll",
560 "univpll",
561 "vcodecpll",
562 "vencpll",
563 "apll1",
564 "apll2",
565 "lvdspll",
566 "lvdspll2",
567 "msdcpll",
568 "msdcpll2",
569 "tvdpll",
570 "mmpll",
571 "armca35pll",
572 "armca72pll",
573 "etherpll",
574 "cvbspll",
575 /* topckgen */
576 "armca35pll_ck",
577 "armca35pll_600m",
578 "armca35pll_400m",
579 "armca72pll_ck",
580 "syspll_ck",
581 "syspll_d2",
582 "syspll1_d2",
583 "syspll1_d4",
584 "syspll1_d8",
585 "syspll1_d16",
586 "syspll_d3",
587 "syspll2_d2",
588 "syspll2_d4",
589 "syspll_d5",
590 "syspll3_d2",
591 "syspll3_d4",
592 "syspll_d7",
593 "syspll4_d2",
594 "syspll4_d4",
595 "univpll_ck",
596 "univpll_d7",
597 "univpll_d26",
598 "univpll_d52",
599 "univpll_d104",
600 "univpll_d208",
601 "univpll_d2",
602 "univpll1_d2",
603 "univpll1_d4",
604 "univpll1_d8",
605 "univpll_d3",
606 "univpll2_d2",
607 "univpll2_d4",
608 "univpll2_d8",
609 "univpll_d5",
610 "univpll3_d2",
611 "univpll3_d4",
612 "univpll3_d8",
613 "f_mp0_pll1_ck",
614 "f_mp0_pll2_ck",
615 "f_big_pll1_ck",
616 "f_big_pll2_ck",
617 "f_bus_pll1_ck",
618 "f_bus_pll2_ck",
619 "apll1_ck",
620 "apll1_d2",
621 "apll1_d3",
622 "apll1_d4",
623 "apll1_d8",
624 "apll1_d16",
625 "apll2_ck",
626 "apll2_d2",
627 "apll2_d4",
628 "apll2_d8",
629 "apll2_d16",
630 "lvdspll_ck",
631 "lvdspll_d2",
632 "lvdspll_d4",
633 "lvdspll_d8",
634 "lvdspll2_ck",
635 "lvdspll2_d2",
636 "lvdspll2_d4",
637 "lvdspll2_d8",
638 "etherpll_125m",
639 "etherpll_50m",
640 "cvbs",
641 "cvbs_d2",
642 "sys_26m",
643 "mmpll_ck",
644 "mmpll_d2",
645 "vencpll_ck",
646 "vencpll_d2",
647 "vcodecpll_ck",
648 "vcodecpll_d2",
649 "tvdpll_ck",
650 "tvdpll_d2",
651 "tvdpll_d4",
652 "tvdpll_d8",
653 "tvdpll_429m",
654 "tvdpll_429m_d2",
655 "tvdpll_429m_d4",
656 "msdcpll_ck",
657 "msdcpll_d2",
658 "msdcpll_d4",
659 "msdcpll2_ck",
660 "msdcpll2_d2",
661 "msdcpll2_d4",
662 "clk26m_d2",
663 "d2a_ulclk_6p5m",
664 "vpll3_dpix",
665 "vpll_dpix",
666 "ltepll_fs26m",
667 "dmpll_ck",
668 "dsi0_lntc",
669 "dsi1_lntc",
670 "lvdstx3",
671 "lvdstx",
672 "clkrtc_ext",
673 "clkrtc_int",
674 "csi0",
675 "apll_div0",
676 "apll_div1",
677 "apll_div2",
678 "apll_div3",
679 "apll_div4",
680 "apll_div5",
681 "apll_div6",
682 "apll_div7",
683 "apll_div_pdn0",
684 "apll_div_pdn1",
685 "apll_div_pdn2",
686 "apll_div_pdn3",
687 "apll_div_pdn4",
688 "apll_div_pdn5",
689 "apll_div_pdn6",
690 "apll_div_pdn7",
691 "nfi2x_en",
692 "nfiecc_en",
693 "nfi1x_ck_en",
694 "axi_sel",
695 "mem_sel",
696 "mm_sel",
697 "pwm_sel",
698 "vdec_sel",
699 "venc_sel",
700 "mfg_sel",
701 "camtg_sel",
702 "uart_sel",
703 "spi_sel",
704 "usb20_sel",
705 "usb30_sel",
706 "msdc50_0_h_sel",
707 "msdc50_0_sel",
708 "msdc30_1_sel",
709 "msdc30_2_sel",
710 "msdc30_3_sel",
711 "audio_sel",
712 "aud_intbus_sel",
713 "pmicspi_sel",
714 "dpilvds1_sel",
715 "atb_sel",
716 "nr_sel",
717 "nfi2x_sel",
718 "irda_sel",
719 "cci400_sel",
720 "aud_1_sel",
721 "aud_2_sel",
722 "mem_mfg_sel",
723 "axi_mfg_sel",
724 "scam_sel",
725 "nfiecc_sel",
726 "pe2_mac_p0_sel",
727 "pe2_mac_p1_sel",
728 "dpilvds_sel",
729 "msdc50_3_h_sel",
730 "hdcp_sel",
731 "hdcp_24m_sel",
732 "rtc_sel",
733 "spinor_sel",
734 "apll_sel",
735 "apll2_sel",
736 "a1sys_hp_sel",
737 "a2sys_hp_sel",
738 "asm_l_sel",
739 "asm_m_sel",
740 "asm_h_sel",
741 "i2so1_sel",
742 "i2so2_sel",
743 "i2so3_sel",
744 "tdmo0_sel",
745 "tdmo1_sel",
746 "i2si1_sel",
747 "i2si2_sel",
748 "i2si3_sel",
749 "ether_125m_sel",
750 "ether_50m_sel",
751 "jpgdec_sel",
752 "spislv_sel",
753 "ether_sel",
754 "cam2tg_sel",
755 "di_sel",
756 "tvd_sel",
757 "i2c_sel",
758 "pwm_infra_sel",
759 "msdc0p_aes_sel",
760 "cmsys_sel",
761 "gcpu_sel",
762 "aud_apll1_sel",
763 "aud_apll2_sel",
764 "apll1_ref_sel",
765 "apll2_ref_sel",
766 "audull_vtx_sel",
767 /* mcucfg */
768 "mcu_mp0_sel",
769 "mcu_mp2_sel",
770 "mcu_bus_sel",
771 /* bdpsys */
772 "bdp_bridge_b",
773 "bdp_bridge_d",
774 "bdp_larb_d",
775 "bdp_vdi_pxl",
776 "bdp_vdi_d",
777 "bdp_vdi_b",
778 "bdp_fmt_b",
779 "bdp_27m",
780 "bdp_27m_vdout",
781 "bdp_27_74_74",
782 "bdp_2fs",
783 "bdp_2fs74_148",
784 "bdp_b",
785 "bdp_vdo_d",
786 "bdp_vdo_2fs",
787 "bdp_vdo_b",
788 "bdp_di_pxl",
789 "bdp_di_d",
790 "bdp_di_b",
791 "bdp_nr_agent",
792 "bdp_nr_d",
793 "bdp_nr_b",
794 "bdp_bridge_rt_b",
795 "bdp_bridge_rt_d",
796 "bdp_larb_rt_d",
797 "bdp_tvd_tdc",
798 "bdp_tvd_clk_54",
799 "bdp_tvd_cbus",
800 /* infracfg */
801 "infra_dbgclk",
802 "infra_gce",
803 "infra_m4u",
804 "infra_kp",
805 "infra_ao_spi0",
806 "infra_ao_spi1",
807 "infra_ao_uart5",
808 /* imgsys */
809 "img_smi_larb2",
810 "img_scam_en",
811 "img_cam_en",
812 "img_cam_sv_en",
813 "img_cam_sv1_en",
814 "img_cam_sv2_en",
815 /* jpgdecsys */
816 "jpgdec_jpgdec1",
817 "jpgdec_jpgdec",
818 /* mfgcfg */
819 "mfg_bg3d",
820 /* mmsys */
821 "mm_smi_common",
822 "mm_smi_larb0",
823 "mm_cam_mdp",
824 "mm_mdp_rdma0",
825 "mm_mdp_rdma1",
826 "mm_mdp_rsz0",
827 "mm_mdp_rsz1",
828 "mm_mdp_rsz2",
829 "mm_mdp_tdshp0",
830 "mm_mdp_tdshp1",
831 "mm_mdp_crop",
832 "mm_mdp_wdma",
833 "mm_mdp_wrot0",
834 "mm_mdp_wrot1",
835 "mm_fake_eng",
836 "mm_mutex_32k",
837 "mm_disp_ovl0",
838 "mm_disp_ovl1",
839 "mm_disp_rdma0",
840 "mm_disp_rdma1",
841 "mm_disp_rdma2",
842 "mm_disp_wdma0",
843 "mm_disp_wdma1",
844 "mm_disp_color0",
845 "mm_disp_color1",
846 "mm_disp_aal",
847 "mm_disp_gamma",
848 "mm_disp_ufoe",
849 "mm_disp_split0",
850 "mm_disp_od",
851 "mm_pwm0_mm",
852 "mm_pwm0_26m",
853 "mm_pwm1_mm",
854 "mm_pwm1_26m",
855 "mm_dsi0_engine",
856 "mm_dsi0_digital",
857 "mm_dsi1_engine",
858 "mm_dsi1_digital",
859 "mm_dpi_pixel",
860 "mm_dpi_engine",
861 "mm_dpi1_pixel",
862 "mm_dpi1_engine",
863 "mm_lvds_pixel",
864 "mm_lvds_cts",
865 "mm_smi_larb4",
866 "mm_smi_common1",
867 "mm_smi_larb5",
868 "mm_mdp_rdma2",
869 "mm_mdp_tdshp2",
870 "mm_disp_ovl2",
871 "mm_disp_wdma2",
872 "mm_disp_color2",
873 "mm_disp_aal1",
874 "mm_disp_od1",
875 "mm_lvds1_pixel",
876 "mm_lvds1_cts",
877 "mm_smi_larb7",
878 "mm_mdp_rdma3",
879 "mm_mdp_wrot2",
880 "mm_dsi2",
881 "mm_dsi2_digital",
882 "mm_dsi3",
883 "mm_dsi3_digital",
884 /* pericfg */
885 "per_nfi",
886 "per_therm",
887 "per_pwm0",
888 "per_pwm1",
889 "per_pwm2",
890 "per_pwm3",
891 "per_pwm4",
892 "per_pwm5",
893 "per_pwm6",
894 "per_pwm7",
895 "per_pwm",
896 "per_ap_dma",
897 "per_msdc30_0",
898 "per_msdc30_1",
899 "per_msdc30_2",
900 "per_msdc30_3",
901 "per_uart0",
902 "per_uart1",
903 "per_uart2",
904 "per_uart3",
905 "per_i2c0",
906 "per_i2c1",
907 "per_i2c2",
908 "per_i2c3",
909 "per_i2c4",
910 "per_auxadc",
911 "per_spi0",
912 "per_spi",
913 "per_i2c5",
914 "per_spi2",
915 "per_spi3",
916 "per_spi5",
917 "per_uart4",
918 "per_sflash",
919 "per_gmac",
920 "per_pcie0",
921 "per_pcie1",
922 "per_gmac_pclk",
923 "per_msdc50_0_en",
924 "per_msdc30_1_en",
925 "per_msdc30_2_en",
926 "per_msdc30_3_en",
927 "per_msdc50_0_h",
928 "per_msdc50_3_h",
929 "per_msdc30_0_q",
930 "per_msdc30_3_q",
931 /* vdecsys */
932 "vdec_cken",
933 "vdec_larb1_cken",
934 "vdec_imgrz_cken",
935 /* vencsys */
936 "venc_smi",
937 "venc_venc",
938 "venc_smi_larb6",
939 /* end */
940 NULL
941 };
942
943 return clks;
944}
945
946/*
947 * clkdbg pwr_status
948 */
949
950static const char * const *get_pwr_names(void)
951{
952 static const char * const pwr_names[] = {
953 [0] = "MD",
954 [1] = "CONN",
955 [2] = "DDRPHY0",
956 [3] = "DISP",
957 [4] = "MFG",
958 [5] = "ISP",
959 [6] = "INFRA",
960 [7] = "VDEC",
961 [8] = "MP0_CPUTOP",
962 [9] = "MP0_CPU0",
963 [10] = "MP0_CPU1",
964 [11] = "MP0_CPU2",
965 [12] = "MP0_CPU3",
966 [13] = "",
967 [14] = "MCUSYS",
968 [15] = "MP1_CPUTOP",
969 [16] = "MP1_CPU0",
970 [17] = "MP1_CPU1",
971 [18] = "",
972 [19] = "USB2",
973 [20] = "",
974 [21] = "VENC",
975 [22] = "MFG_SC1",
976 [23] = "MFG_SC2",
977 [24] = "AUDIO",
978 [25] = "USB",
979 [26] = "",
980 [27] = "DDRPHY1",
981 [28] = "DDRPHY2",
982 [29] = "DDRPHY3",
983 [30] = "MFG_SC3",
984 [31] = "",
985 };
986
987 return pwr_names;
988}
989
990/*
991 * clkdbg dump_clks
992 */
993
994static void setup_provider_clk(struct provider_clk *pvdck)
995{
996 static const struct {
997 const char *pvdname;
998 u32 pwr_mask;
999 } pvd_pwr_mask[] = {
1000 {"mfgcfg", BIT(4)},
1001 {"mmsys", BIT(3)},
1002 {"imgsys", BIT(3) | BIT(5)},
1003 {"bdpsys", BIT(3) | BIT(5)},
1004 {"vdecsys", BIT(3) | BIT(7)},
1005 {"vencsys", BIT(3) | BIT(21)},
1006 {"jpgdecsys", BIT(3) | BIT(21)},
1007 {"audsys", BIT(24)},
1008 };
1009
1010 size_t i;
1011 const char *pvdname = pvdck->provider_name;
1012
1013 if (pvdname == NULL)
1014 return;
1015
1016 for (i = 0; i < ARRAY_SIZE(pvd_pwr_mask); i++) {
1017 if (strcmp(pvdname, pvd_pwr_mask[i].pvdname) == 0) {
1018 pvdck->pwr_mask = pvd_pwr_mask[i].pwr_mask;
1019 return;
1020 }
1021 }
1022}
1023
1024/*
1025 * init functions
1026 */
1027
1028static struct clkdbg_ops clkdbg_mt2712_ops = {
1029 .get_all_fmeter_clks = get_all_fmeter_clks,
1030 .prepare_fmeter = prepare_fmeter,
1031 .unprepare_fmeter = unprepare_fmeter,
1032 .fmeter_freq = fmeter_freq_op,
1033 .get_all_regnames = get_all_regnames,
1034 .get_all_clk_names = get_all_clk_names,
1035 .get_pwr_names = get_pwr_names,
1036 .setup_provider_clk = setup_provider_clk,
1037};
1038
1039static void __init init_custom_cmds(void)
1040{
1041 static const struct cmd_fn cmds[] = {
1042 {}
1043 };
1044
1045 set_custom_cmds(cmds);
1046}
1047
1048static int __init clkdbg_mt2712_init(void)
1049{
1050 if (of_machine_is_compatible("mediatek,mt2712") == 0)
1051 return -ENODEV;
1052
1053 init_regbase();
1054
1055 init_custom_cmds();
1056 set_clkdbg_ops(&clkdbg_mt2712_ops);
1057
1058#if DUMP_INIT_STATE
1059 print_regs();
1060 print_fmeter_all();
1061#endif /* DUMP_INIT_STATE */
1062
1063 return 0;
1064}
1065device_initcall(clkdbg_mt2712_init);