| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | ============ | 
|  | 2 | Introduction | 
|  | 3 | ============ | 
|  | 4 |  | 
|  | 5 |  | 
|  | 6 | GPIO Interfaces | 
|  | 7 | =============== | 
|  | 8 |  | 
|  | 9 | The documents in this directory give detailed instructions on how to access | 
|  | 10 | GPIOs in drivers, and how to write a driver for a device that provides GPIOs | 
|  | 11 | itself. | 
|  | 12 |  | 
|  | 13 | Due to the history of GPIO interfaces in the kernel, there are two different | 
|  | 14 | ways to obtain and use GPIOs: | 
|  | 15 |  | 
|  | 16 | - The descriptor-based interface is the preferred way to manipulate GPIOs, | 
|  | 17 | and is described by all the files in this directory excepted gpio-legacy.txt. | 
|  | 18 | - The legacy integer-based interface which is considered deprecated (but still | 
|  | 19 | usable for compatibility reasons) is documented in gpio-legacy.txt. | 
|  | 20 |  | 
|  | 21 | The remainder of this document applies to the new descriptor-based interface. | 
|  | 22 | gpio-legacy.txt contains the same information applied to the legacy | 
|  | 23 | integer-based interface. | 
|  | 24 |  | 
|  | 25 |  | 
|  | 26 | What is a GPIO? | 
|  | 27 | =============== | 
|  | 28 |  | 
|  | 29 | A "General Purpose Input/Output" (GPIO) is a flexible software-controlled | 
|  | 30 | digital signal. They are provided from many kinds of chip, and are familiar | 
|  | 31 | to Linux developers working with embedded and custom hardware. Each GPIO | 
|  | 32 | represents a bit connected to a particular pin, or "ball" on Ball Grid Array | 
|  | 33 | (BGA) packages. Board schematics show which external hardware connects to | 
|  | 34 | which GPIOs. Drivers can be written generically, so that board setup code | 
|  | 35 | passes such pin configuration data to drivers. | 
|  | 36 |  | 
|  | 37 | System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every | 
|  | 38 | non-dedicated pin can be configured as a GPIO; and most chips have at least | 
|  | 39 | several dozen of them. Programmable logic devices (like FPGAs) can easily | 
|  | 40 | provide GPIOs; multifunction chips like power managers, and audio codecs | 
|  | 41 | often have a few such pins to help with pin scarcity on SOCs; and there are | 
|  | 42 | also "GPIO Expander" chips that connect using the I2C or SPI serial buses. | 
|  | 43 | Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS | 
|  | 44 | firmware knowing how they're used). | 
|  | 45 |  | 
|  | 46 | The exact capabilities of GPIOs vary between systems. Common options: | 
|  | 47 |  | 
|  | 48 | - Output values are writable (high=1, low=0). Some chips also have | 
|  | 49 | options about how that value is driven, so that for example only one | 
|  | 50 | value might be driven, supporting "wire-OR" and similar schemes for the | 
|  | 51 | other value (notably, "open drain" signaling). | 
|  | 52 |  | 
|  | 53 | - Input values are likewise readable (1, 0). Some chips support readback | 
|  | 54 | of pins configured as "output", which is very useful in such "wire-OR" | 
|  | 55 | cases (to support bidirectional signaling). GPIO controllers may have | 
|  | 56 | input de-glitch/debounce logic, sometimes with software controls. | 
|  | 57 |  | 
|  | 58 | - Inputs can often be used as IRQ signals, often edge triggered but | 
|  | 59 | sometimes level triggered. Such IRQs may be configurable as system | 
|  | 60 | wakeup events, to wake the system from a low power state. | 
|  | 61 |  | 
|  | 62 | - Usually a GPIO will be configurable as either input or output, as needed | 
|  | 63 | by different product boards; single direction ones exist too. | 
|  | 64 |  | 
|  | 65 | - Most GPIOs can be accessed while holding spinlocks, but those accessed | 
|  | 66 | through a serial bus normally can't. Some systems support both types. | 
|  | 67 |  | 
|  | 68 | On a given board each GPIO is used for one specific purpose like monitoring | 
|  | 69 | MMC/SD card insertion/removal, detecting card write-protect status, driving | 
|  | 70 | a LED, configuring a transceiver, bit-banging a serial bus, poking a hardware | 
|  | 71 | watchdog, sensing a switch, and so on. | 
|  | 72 |  | 
|  | 73 |  | 
|  | 74 | Common GPIO Properties | 
|  | 75 | ====================== | 
|  | 76 |  | 
|  | 77 | These properties are met through all the other documents of the GPIO interface | 
|  | 78 | and it is useful to understand them, especially if you need to define GPIO | 
|  | 79 | mappings. | 
|  | 80 |  | 
|  | 81 | Active-High and Active-Low | 
|  | 82 | -------------------------- | 
|  | 83 | It is natural to assume that a GPIO is "active" when its output signal is 1 | 
|  | 84 | ("high"), and inactive when it is 0 ("low"). However in practice the signal of a | 
|  | 85 | GPIO may be inverted before is reaches its destination, or a device could decide | 
|  | 86 | to have different conventions about what "active" means. Such decisions should | 
|  | 87 | be transparent to device drivers, therefore it is possible to define a GPIO as | 
|  | 88 | being either active-high ("1" means "active", the default) or active-low ("0" | 
|  | 89 | means "active") so that drivers only need to worry about the logical signal and | 
|  | 90 | not about what happens at the line level. | 
|  | 91 |  | 
|  | 92 | Open Drain and Open Source | 
|  | 93 | -------------------------- | 
|  | 94 | Sometimes shared signals need to use "open drain" (where only the low signal | 
|  | 95 | level is actually driven), or "open source" (where only the high signal level is | 
|  | 96 | driven) signaling. That term applies to CMOS transistors; "open collector" is | 
|  | 97 | used for TTL. A pullup or pulldown resistor causes the high or low signal level. | 
|  | 98 | This is sometimes called a "wire-AND"; or more practically, from the negative | 
|  | 99 | logic (low=true) perspective this is a "wire-OR". | 
|  | 100 |  | 
|  | 101 | One common example of an open drain signal is a shared active-low IRQ line. | 
|  | 102 | Also, bidirectional data bus signals sometimes use open drain signals. | 
|  | 103 |  | 
|  | 104 | Some GPIO controllers directly support open drain and open source outputs; many | 
|  | 105 | don't. When you need open drain signaling but your hardware doesn't directly | 
|  | 106 | support it, there's a common idiom you can use to emulate it with any GPIO pin | 
|  | 107 | that can be used as either an input or an output: | 
|  | 108 |  | 
|  | 109 | LOW:	gpiod_direction_output(gpio, 0) ... this drives the signal and overrides | 
|  | 110 | the pullup. | 
|  | 111 |  | 
|  | 112 | HIGH:	gpiod_direction_input(gpio) ... this turns off the output, so the pullup | 
|  | 113 | (or some other device) controls the signal. | 
|  | 114 |  | 
|  | 115 | The same logic can be applied to emulate open source signaling, by driving the | 
|  | 116 | high signal and configuring the GPIO as input for low. This open drain/open | 
|  | 117 | source emulation can be handled transparently by the GPIO framework. | 
|  | 118 |  | 
|  | 119 | If you are "driving" the signal high but gpiod_get_value(gpio) reports a low | 
|  | 120 | value (after the appropriate rise time passes), you know some other component is | 
|  | 121 | driving the shared signal low. That's not necessarily an error. As one common | 
|  | 122 | example, that's how I2C clocks are stretched:  a slave that needs a slower clock | 
|  | 123 | delays the rising edge of SCK, and the I2C master adjusts its signaling rate | 
|  | 124 | accordingly. |