| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2020 MediaTek Inc. |
| 4 | */ |
| 5 | |
| 6 | #ifndef _DT_BINDINGS_MT635X_AUXADC_H |
| 7 | #define _DT_BINDINGS_MT635X_AUXADC_H |
| 8 | |
| 9 | /* PMIC MT635x AUXADC channels */ |
| 10 | #define AUXADC_BATADC 0x00 |
| 11 | #define AUXADC_ISENSE 0x01 |
| 12 | #define AUXADC_VCDT 0x02 |
| 13 | #define AUXADC_BAT_TEMP 0x03 |
| 14 | #define AUXADC_BATID 0x04 |
| 15 | #define AUXADC_CHIP_TEMP 0x05 |
| 16 | #define AUXADC_VCORE_TEMP 0x06 |
| 17 | #define AUXADC_VPROC_TEMP 0x07 |
| 18 | #define AUXADC_VGPU_TEMP 0x08 |
| 19 | #define AUXADC_ACCDET 0x09 |
| 20 | #define AUXADC_VDCXO 0x0a |
| 21 | #define AUXADC_TSX_TEMP 0x0b |
| 22 | #define AUXADC_HPOFS_CAL 0x0c |
| 23 | #define AUXADC_DCXO_TEMP 0x0d |
| 24 | #define AUXADC_VBIF 0x0e |
| 25 | #define AUXADC_IMP 0x0f |
| 26 | #define AUXADC_IMIX_R 0x10 |
| 27 | #define AUXADC_TYPEL 0x11 |
| 28 | #define AUXADC_DRDI 0x12 |
| 29 | |
| 30 | #define AUXADC_CHAN_MIN AUXADC_BATADC |
| xj | 112b967 | 2022-01-25 16:13:48 +0800 | [diff] [blame] | 31 | #define AUXADC_CHAN_MAX AUXADC_DRDI |
| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 32 | |
| 33 | #endif /* _DT_BINDINGS_MT635X_AUXADC_H */ |