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192.168.1.100 / T800 / 92e4c03aba06aead9562a9675b860fb6ec4c828c / . / src / kernel / linux / v4.19 / arch / arm / mach-davinci / dm365.c
blob: 83ca89a353002a9a02955bc8e1410c8b55edc461 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1/*
2 * TI DaVinci DM365 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/clk/davinci.h>
18#include <linux/clkdev.h>
19#include <linux/dma-mapping.h>
20#include <linux/dmaengine.h>
21#include <linux/init.h>
22#include <linux/platform_data/edma.h>
23#include <linux/platform_data/gpio-davinci.h>
24#include <linux/platform_data/keyscan-davinci.h>
25#include <linux/platform_data/spi-davinci.h>
26#include <linux/platform_device.h>
27#include <linux/serial_8250.h>
28#include <linux/spi/spi.h>
29
30#include <asm/mach/map.h>
31
32#include <mach/common.h>
33#include <mach/cputype.h>
34#include <mach/irqs.h>
35#include <mach/mux.h>
36#include <mach/serial.h>
37#include <mach/time.h>
38
39#include "asp.h"
40#include "davinci.h"
41#include "mux.h"
42
43#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
44#define DM365_RTC_BASE 0x01c69000
45#define DM365_KEYSCAN_BASE 0x01c69400
46#define DM365_OSD_BASE 0x01c71c00
47#define DM365_VENC_BASE 0x01c71e00
48#define DAVINCI_DM365_VC_BASE 0x01d0c000
49#define DAVINCI_DMA_VC_TX 2
50#define DAVINCI_DMA_VC_RX 3
51#define DM365_EMAC_BASE 0x01d07000
52#define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
53#define DM365_EMAC_CNTRL_OFFSET 0x0000
54#define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
55#define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
56#define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
57
58#define INTMUX 0x18
59#define EVTMUX 0x1c
60
61
62static const struct mux_config dm365_pins[] = {
63#ifdef CONFIG_DAVINCI_MUX
64MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
65
66MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
67MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
68MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
69MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
70MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
71MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
72
73MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
74MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
75
76MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
77MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
78MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
79MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
80MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
81MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
82MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
83MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
84
85MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
86MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
87MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
88MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
89MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
90MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
91
92MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
93MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
94MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
95MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
96MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
97
98MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
99MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
100MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
101MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
102MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
103MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
104
105MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
106MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
107MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
108MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
109MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
110MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
111MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
112MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
113MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
114MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
115MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
116MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
117MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
118MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
119MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
120MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
121MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
122
123MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
124
125MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
126MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
127MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
128MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
129MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
130MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
131MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
132MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
133MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
134MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
135MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
136MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
137
138MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
139MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
140MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
141MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
142MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
143
144MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
145MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
146MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
147MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
148MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
149
150MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
151MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
152MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
153MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
154MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
155
156MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
157MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
158MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
159MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
160MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
161
162MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
163MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
164MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
165
166MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
167MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
168MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
169MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
170MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
171MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
172MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
173
174MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
175MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
176MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
177MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
178MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
179MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
180MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
181MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
182MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
183MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
184
185INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
186INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
187INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
188INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
189INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
190INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
191INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
192INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
193INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
194INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
195INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
196INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
197INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
198INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
199INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
200INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
201INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
202INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
203
204EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
205EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
206EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
207EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
208#endif
209};
210
211static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
212
213static struct davinci_spi_platform_data dm365_spi0_pdata = {
214 .version = SPI_VERSION_1,
215 .num_chipselect = 2,
216 .dma_event_q = EVENTQ_3,
217 .prescaler_limit = 1,
218};
219
220static struct resource dm365_spi0_resources[] = {
221 {
222 .start = 0x01c66000,
223 .end = 0x01c667ff,
224 .flags = IORESOURCE_MEM,
225 },
226 {
227 .start = IRQ_DM365_SPIINT0_0,
228 .flags = IORESOURCE_IRQ,
229 },
230};
231
232static struct platform_device dm365_spi0_device = {
233 .name = "spi_davinci",
234 .id = 0,
235 .dev = {
236 .dma_mask = &dm365_spi0_dma_mask,
237 .coherent_dma_mask = DMA_BIT_MASK(32),
238 .platform_data = &dm365_spi0_pdata,
239 },
240 .num_resources = ARRAY_SIZE(dm365_spi0_resources),
241 .resource = dm365_spi0_resources,
242};
243
244void __init dm365_init_spi0(unsigned chipselect_mask,
245 const struct spi_board_info *info, unsigned len)
246{
247 davinci_cfg_reg(DM365_SPI0_SCLK);
248 davinci_cfg_reg(DM365_SPI0_SDI);
249 davinci_cfg_reg(DM365_SPI0_SDO);
250
251 /* not all slaves will be wired up */
252 if (chipselect_mask & BIT(0))
253 davinci_cfg_reg(DM365_SPI0_SDENA0);
254 if (chipselect_mask & BIT(1))
255 davinci_cfg_reg(DM365_SPI0_SDENA1);
256
257 spi_register_board_info(info, len);
258
259 platform_device_register(&dm365_spi0_device);
260}
261
262static struct resource dm365_gpio_resources[] = {
263 { /* registers */
264 .start = DAVINCI_GPIO_BASE,
265 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
266 .flags = IORESOURCE_MEM,
267 },
268 { /* interrupt */
269 .start = IRQ_DM365_GPIO0,
270 .end = IRQ_DM365_GPIO0,
271 .flags = IORESOURCE_IRQ,
272 },
273 {
274 .start = IRQ_DM365_GPIO1,
275 .end = IRQ_DM365_GPIO1,
276 .flags = IORESOURCE_IRQ,
277 },
278 {
279 .start = IRQ_DM365_GPIO2,
280 .end = IRQ_DM365_GPIO2,
281 .flags = IORESOURCE_IRQ,
282 },
283 {
284 .start = IRQ_DM365_GPIO3,
285 .end = IRQ_DM365_GPIO3,
286 .flags = IORESOURCE_IRQ,
287 },
288 {
289 .start = IRQ_DM365_GPIO4,
290 .end = IRQ_DM365_GPIO4,
291 .flags = IORESOURCE_IRQ,
292 },
293 {
294 .start = IRQ_DM365_GPIO5,
295 .end = IRQ_DM365_GPIO5,
296 .flags = IORESOURCE_IRQ,
297 },
298 {
299 .start = IRQ_DM365_GPIO6,
300 .end = IRQ_DM365_GPIO6,
301 .flags = IORESOURCE_IRQ,
302 },
303 {
304 .start = IRQ_DM365_GPIO7,
305 .end = IRQ_DM365_GPIO7,
306 .flags = IORESOURCE_IRQ,
307 },
308};
309
310static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
311 .ngpio = 104,
312 .gpio_unbanked = 8,
313};
314
315int __init dm365_gpio_register(void)
316{
317 return davinci_gpio_register(dm365_gpio_resources,
318 ARRAY_SIZE(dm365_gpio_resources),
319 &dm365_gpio_platform_data);
320}
321
322static struct emac_platform_data dm365_emac_pdata = {
323 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
324 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
325 .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
326 .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
327 .version = EMAC_VERSION_2,
328};
329
330static struct resource dm365_emac_resources[] = {
331 {
332 .start = DM365_EMAC_BASE,
333 .end = DM365_EMAC_BASE + SZ_16K - 1,
334 .flags = IORESOURCE_MEM,
335 },
336 {
337 .start = IRQ_DM365_EMAC_RXTHRESH,
338 .end = IRQ_DM365_EMAC_RXTHRESH,
339 .flags = IORESOURCE_IRQ,
340 },
341 {
342 .start = IRQ_DM365_EMAC_RXPULSE,
343 .end = IRQ_DM365_EMAC_RXPULSE,
344 .flags = IORESOURCE_IRQ,
345 },
346 {
347 .start = IRQ_DM365_EMAC_TXPULSE,
348 .end = IRQ_DM365_EMAC_TXPULSE,
349 .flags = IORESOURCE_IRQ,
350 },
351 {
352 .start = IRQ_DM365_EMAC_MISCPULSE,
353 .end = IRQ_DM365_EMAC_MISCPULSE,
354 .flags = IORESOURCE_IRQ,
355 },
356};
357
358static struct platform_device dm365_emac_device = {
359 .name = "davinci_emac",
360 .id = 1,
361 .dev = {
362 .platform_data = &dm365_emac_pdata,
363 },
364 .num_resources = ARRAY_SIZE(dm365_emac_resources),
365 .resource = dm365_emac_resources,
366};
367
368static struct resource dm365_mdio_resources[] = {
369 {
370 .start = DM365_EMAC_MDIO_BASE,
371 .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
372 .flags = IORESOURCE_MEM,
373 },
374};
375
376static struct platform_device dm365_mdio_device = {
377 .name = "davinci_mdio",
378 .id = 0,
379 .num_resources = ARRAY_SIZE(dm365_mdio_resources),
380 .resource = dm365_mdio_resources,
381};
382
383static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
384 [IRQ_VDINT0] = 2,
385 [IRQ_VDINT1] = 6,
386 [IRQ_VDINT2] = 6,
387 [IRQ_HISTINT] = 6,
388 [IRQ_H3AINT] = 6,
389 [IRQ_PRVUINT] = 6,
390 [IRQ_RSZINT] = 6,
391 [IRQ_DM365_INSFINT] = 7,
392 [IRQ_VENCINT] = 6,
393 [IRQ_ASQINT] = 6,
394 [IRQ_IMXINT] = 6,
395 [IRQ_DM365_IMCOPINT] = 4,
396 [IRQ_USBINT] = 4,
397 [IRQ_DM365_RTOINT] = 7,
398 [IRQ_DM365_TINT5] = 7,
399 [IRQ_DM365_TINT6] = 5,
400 [IRQ_CCINT0] = 5,
401 [IRQ_CCERRINT] = 5,
402 [IRQ_TCERRINT0] = 5,
403 [IRQ_TCERRINT] = 7,
404 [IRQ_PSCIN] = 4,
405 [IRQ_DM365_SPINT2_1] = 7,
406 [IRQ_DM365_TINT7] = 7,
407 [IRQ_DM365_SDIOINT0] = 7,
408 [IRQ_MBXINT] = 7,
409 [IRQ_MBRINT] = 7,
410 [IRQ_MMCINT] = 7,
411 [IRQ_DM365_MMCINT1] = 7,
412 [IRQ_DM365_PWMINT3] = 7,
413 [IRQ_AEMIFINT] = 2,
414 [IRQ_DM365_SDIOINT1] = 2,
415 [IRQ_TINT0_TINT12] = 7,
416 [IRQ_TINT0_TINT34] = 7,
417 [IRQ_TINT1_TINT12] = 7,
418 [IRQ_TINT1_TINT34] = 7,
419 [IRQ_PWMINT0] = 7,
420 [IRQ_PWMINT1] = 3,
421 [IRQ_PWMINT2] = 3,
422 [IRQ_I2C] = 3,
423 [IRQ_UARTINT0] = 3,
424 [IRQ_UARTINT1] = 3,
425 [IRQ_DM365_RTCINT] = 3,
426 [IRQ_DM365_SPIINT0_0] = 3,
427 [IRQ_DM365_SPIINT3_0] = 3,
428 [IRQ_DM365_GPIO0] = 3,
429 [IRQ_DM365_GPIO1] = 7,
430 [IRQ_DM365_GPIO2] = 4,
431 [IRQ_DM365_GPIO3] = 4,
432 [IRQ_DM365_GPIO4] = 7,
433 [IRQ_DM365_GPIO5] = 7,
434 [IRQ_DM365_GPIO6] = 7,
435 [IRQ_DM365_GPIO7] = 7,
436 [IRQ_DM365_EMAC_RXTHRESH] = 7,
437 [IRQ_DM365_EMAC_RXPULSE] = 7,
438 [IRQ_DM365_EMAC_TXPULSE] = 7,
439 [IRQ_DM365_EMAC_MISCPULSE] = 7,
440 [IRQ_DM365_GPIO12] = 7,
441 [IRQ_DM365_GPIO13] = 7,
442 [IRQ_DM365_GPIO14] = 7,
443 [IRQ_DM365_GPIO15] = 7,
444 [IRQ_DM365_KEYINT] = 7,
445 [IRQ_DM365_TCERRINT2] = 7,
446 [IRQ_DM365_TCERRINT3] = 7,
447 [IRQ_DM365_EMUINT] = 7,
448};
449
450/* Four Transfer Controllers on DM365 */
451static s8 dm365_queue_priority_mapping[][2] = {
452 /* {event queue no, Priority} */
453 {0, 7},
454 {1, 7},
455 {2, 7},
456 {3, 0},
457 {-1, -1},
458};
459
460static const struct dma_slave_map dm365_edma_map[] = {
461 { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
462 { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
463 { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
464 { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
465 { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
466 { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
467 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
468 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
469 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
470 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
471 { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
472 { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
473 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
474 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
475 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
476 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
477};
478
479static struct edma_soc_info dm365_edma_pdata = {
480 .queue_priority_mapping = dm365_queue_priority_mapping,
481 .default_queue = EVENTQ_3,
482 .slave_map = dm365_edma_map,
483 .slavecnt = ARRAY_SIZE(dm365_edma_map),
484};
485
486static struct resource edma_resources[] = {
487 {
488 .name = "edma3_cc",
489 .start = 0x01c00000,
490 .end = 0x01c00000 + SZ_64K - 1,
491 .flags = IORESOURCE_MEM,
492 },
493 {
494 .name = "edma3_tc0",
495 .start = 0x01c10000,
496 .end = 0x01c10000 + SZ_1K - 1,
497 .flags = IORESOURCE_MEM,
498 },
499 {
500 .name = "edma3_tc1",
501 .start = 0x01c10400,
502 .end = 0x01c10400 + SZ_1K - 1,
503 .flags = IORESOURCE_MEM,
504 },
505 {
506 .name = "edma3_tc2",
507 .start = 0x01c10800,
508 .end = 0x01c10800 + SZ_1K - 1,
509 .flags = IORESOURCE_MEM,
510 },
511 {
512 .name = "edma3_tc3",
513 .start = 0x01c10c00,
514 .end = 0x01c10c00 + SZ_1K - 1,
515 .flags = IORESOURCE_MEM,
516 },
517 {
518 .name = "edma3_ccint",
519 .start = IRQ_CCINT0,
520 .flags = IORESOURCE_IRQ,
521 },
522 {
523 .name = "edma3_ccerrint",
524 .start = IRQ_CCERRINT,
525 .flags = IORESOURCE_IRQ,
526 },
527 /* not using TC*_ERR */
528};
529
530static const struct platform_device_info dm365_edma_device __initconst = {
531 .name = "edma",
532 .id = 0,
533 .dma_mask = DMA_BIT_MASK(32),
534 .res = edma_resources,
535 .num_res = ARRAY_SIZE(edma_resources),
536 .data = &dm365_edma_pdata,
537 .size_data = sizeof(dm365_edma_pdata),
538};
539
540static struct resource dm365_asp_resources[] = {
541 {
542 .name = "mpu",
543 .start = DAVINCI_DM365_ASP0_BASE,
544 .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
545 .flags = IORESOURCE_MEM,
546 },
547 {
548 .start = DAVINCI_DMA_ASP0_TX,
549 .end = DAVINCI_DMA_ASP0_TX,
550 .flags = IORESOURCE_DMA,
551 },
552 {
553 .start = DAVINCI_DMA_ASP0_RX,
554 .end = DAVINCI_DMA_ASP0_RX,
555 .flags = IORESOURCE_DMA,
556 },
557};
558
559static struct platform_device dm365_asp_device = {
560 .name = "davinci-mcbsp",
561 .id = -1,
562 .num_resources = ARRAY_SIZE(dm365_asp_resources),
563 .resource = dm365_asp_resources,
564};
565
566static struct resource dm365_vc_resources[] = {
567 {
568 .start = DAVINCI_DM365_VC_BASE,
569 .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
570 .flags = IORESOURCE_MEM,
571 },
572 {
573 .start = DAVINCI_DMA_VC_TX,
574 .end = DAVINCI_DMA_VC_TX,
575 .flags = IORESOURCE_DMA,
576 },
577 {
578 .start = DAVINCI_DMA_VC_RX,
579 .end = DAVINCI_DMA_VC_RX,
580 .flags = IORESOURCE_DMA,
581 },
582};
583
584static struct platform_device dm365_vc_device = {
585 .name = "davinci_voicecodec",
586 .id = -1,
587 .num_resources = ARRAY_SIZE(dm365_vc_resources),
588 .resource = dm365_vc_resources,
589};
590
591static struct resource dm365_rtc_resources[] = {
592 {
593 .start = DM365_RTC_BASE,
594 .end = DM365_RTC_BASE + SZ_1K - 1,
595 .flags = IORESOURCE_MEM,
596 },
597 {
598 .start = IRQ_DM365_RTCINT,
599 .flags = IORESOURCE_IRQ,
600 },
601};
602
603static struct platform_device dm365_rtc_device = {
604 .name = "rtc_davinci",
605 .id = 0,
606 .num_resources = ARRAY_SIZE(dm365_rtc_resources),
607 .resource = dm365_rtc_resources,
608};
609
610static struct map_desc dm365_io_desc[] = {
611 {
612 .virtual = IO_VIRT,
613 .pfn = __phys_to_pfn(IO_PHYS),
614 .length = IO_SIZE,
615 .type = MT_DEVICE
616 },
617};
618
619static struct resource dm365_ks_resources[] = {
620 {
621 /* registers */
622 .start = DM365_KEYSCAN_BASE,
623 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
624 .flags = IORESOURCE_MEM,
625 },
626 {
627 /* interrupt */
628 .start = IRQ_DM365_KEYINT,
629 .end = IRQ_DM365_KEYINT,
630 .flags = IORESOURCE_IRQ,
631 },
632};
633
634static struct platform_device dm365_ks_device = {
635 .name = "davinci_keyscan",
636 .id = 0,
637 .num_resources = ARRAY_SIZE(dm365_ks_resources),
638 .resource = dm365_ks_resources,
639};
640
641/* Contents of JTAG ID register used to identify exact cpu type */
642static struct davinci_id dm365_ids[] = {
643 {
644 .variant = 0x0,
645 .part_no = 0xb83e,
646 .manufacturer = 0x017,
647 .cpu_id = DAVINCI_CPU_ID_DM365,
648 .name = "dm365_rev1.1",
649 },
650 {
651 .variant = 0x8,
652 .part_no = 0xb83e,
653 .manufacturer = 0x017,
654 .cpu_id = DAVINCI_CPU_ID_DM365,
655 .name = "dm365_rev1.2",
656 },
657};
658
659static struct davinci_timer_info dm365_timer_info = {
660 .timers = davinci_timer_instance,
661 .clockevent_id = T0_BOT,
662 .clocksource_id = T0_TOP,
663};
664
665#define DM365_UART1_BASE (IO_PHYS + 0x106000)
666
667static struct plat_serial8250_port dm365_serial0_platform_data[] = {
668 {
669 .mapbase = DAVINCI_UART0_BASE,
670 .irq = IRQ_UARTINT0,
671 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
672 UPF_IOREMAP,
673 .iotype = UPIO_MEM,
674 .regshift = 2,
675 },
676 {
677 .flags = 0,
678 }
679};
680static struct plat_serial8250_port dm365_serial1_platform_data[] = {
681 {
682 .mapbase = DM365_UART1_BASE,
683 .irq = IRQ_UARTINT1,
684 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
685 UPF_IOREMAP,
686 .iotype = UPIO_MEM,
687 .regshift = 2,
688 },
689 {
690 .flags = 0,
691 }
692};
693
694struct platform_device dm365_serial_device[] = {
695 {
696 .name = "serial8250",
697 .id = PLAT8250_DEV_PLATFORM,
698 .dev = {
699 .platform_data = dm365_serial0_platform_data,
700 }
701 },
702 {
703 .name = "serial8250",
704 .id = PLAT8250_DEV_PLATFORM1,
705 .dev = {
706 .platform_data = dm365_serial1_platform_data,
707 }
708 },
709 {
710 }
711};
712
713static const struct davinci_soc_info davinci_soc_info_dm365 = {
714 .io_desc = dm365_io_desc,
715 .io_desc_num = ARRAY_SIZE(dm365_io_desc),
716 .jtag_id_reg = 0x01c40028,
717 .ids = dm365_ids,
718 .ids_num = ARRAY_SIZE(dm365_ids),
719 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
720 .pinmux_pins = dm365_pins,
721 .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
722 .intc_base = DAVINCI_ARM_INTC_BASE,
723 .intc_type = DAVINCI_INTC_TYPE_AINTC,
724 .intc_irq_prios = dm365_default_priorities,
725 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
726 .timer_info = &dm365_timer_info,
727 .emac_pdata = &dm365_emac_pdata,
728 .sram_dma = 0x00010000,
729 .sram_len = SZ_32K,
730};
731
732void __init dm365_init_asp(void)
733{
734 davinci_cfg_reg(DM365_MCBSP0_BDX);
735 davinci_cfg_reg(DM365_MCBSP0_X);
736 davinci_cfg_reg(DM365_MCBSP0_BFSX);
737 davinci_cfg_reg(DM365_MCBSP0_BDR);
738 davinci_cfg_reg(DM365_MCBSP0_R);
739 davinci_cfg_reg(DM365_MCBSP0_BFSR);
740 davinci_cfg_reg(DM365_EVT2_ASP_TX);
741 davinci_cfg_reg(DM365_EVT3_ASP_RX);
742 platform_device_register(&dm365_asp_device);
743}
744
745void __init dm365_init_vc(void)
746{
747 davinci_cfg_reg(DM365_EVT2_VC_TX);
748 davinci_cfg_reg(DM365_EVT3_VC_RX);
749 platform_device_register(&dm365_vc_device);
750}
751
752void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
753{
754 dm365_ks_device.dev.platform_data = pdata;
755 platform_device_register(&dm365_ks_device);
756}
757
758void __init dm365_init_rtc(void)
759{
760 davinci_cfg_reg(DM365_INT_PRTCSS);
761 platform_device_register(&dm365_rtc_device);
762}
763
764void __init dm365_init(void)
765{
766 davinci_common_init(&davinci_soc_info_dm365);
767 davinci_map_sysmod();
768}
769
770void __init dm365_init_time(void)
771{
772 void __iomem *pll1, *pll2, *psc;
773 struct clk *clk;
774
775 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
776
777 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
778 dm365_pll1_init(NULL, pll1, NULL);
779
780 pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K);
781 dm365_pll2_init(NULL, pll2, NULL);
782
783 psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
784 dm365_psc_init(NULL, psc);
785
786 clk = clk_get(NULL, "timer0");
787
788 davinci_timer_init(clk);
789}
790
791void __init dm365_register_clocks(void)
792{
793 /* all clocks are currently registered in dm365_init_time() */
794}
795
796static struct resource dm365_vpss_resources[] = {
797 {
798 /* VPSS ISP5 Base address */
799 .name = "isp5",
800 .start = 0x01c70000,
801 .end = 0x01c70000 + 0xff,
802 .flags = IORESOURCE_MEM,
803 },
804 {
805 /* VPSS CLK Base address */
806 .name = "vpss",
807 .start = 0x01c70200,
808 .end = 0x01c70200 + 0xff,
809 .flags = IORESOURCE_MEM,
810 },
811};
812
813static struct platform_device dm365_vpss_device = {
814 .name = "vpss",
815 .id = -1,
816 .dev.platform_data = "dm365_vpss",
817 .num_resources = ARRAY_SIZE(dm365_vpss_resources),
818 .resource = dm365_vpss_resources,
819};
820
821static struct resource vpfe_resources[] = {
822 {
823 .start = IRQ_VDINT0,
824 .end = IRQ_VDINT0,
825 .flags = IORESOURCE_IRQ,
826 },
827 {
828 .start = IRQ_VDINT1,
829 .end = IRQ_VDINT1,
830 .flags = IORESOURCE_IRQ,
831 },
832};
833
834static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
835static struct platform_device vpfe_capture_dev = {
836 .name = CAPTURE_DRV_NAME,
837 .id = -1,
838 .num_resources = ARRAY_SIZE(vpfe_resources),
839 .resource = vpfe_resources,
840 .dev = {
841 .dma_mask = &vpfe_capture_dma_mask,
842 .coherent_dma_mask = DMA_BIT_MASK(32),
843 },
844};
845
846static void dm365_isif_setup_pinmux(void)
847{
848 davinci_cfg_reg(DM365_VIN_CAM_WEN);
849 davinci_cfg_reg(DM365_VIN_CAM_VD);
850 davinci_cfg_reg(DM365_VIN_CAM_HD);
851 davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
852 davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
853}
854
855static struct resource isif_resource[] = {
856 /* ISIF Base address */
857 {
858 .start = 0x01c71000,
859 .end = 0x01c71000 + 0x1ff,
860 .flags = IORESOURCE_MEM,
861 },
862 /* ISIF Linearization table 0 */
863 {
864 .start = 0x1C7C000,
865 .end = 0x1C7C000 + 0x2ff,
866 .flags = IORESOURCE_MEM,
867 },
868 /* ISIF Linearization table 1 */
869 {
870 .start = 0x1C7C400,
871 .end = 0x1C7C400 + 0x2ff,
872 .flags = IORESOURCE_MEM,
873 },
874};
875static struct platform_device dm365_isif_dev = {
876 .name = "isif",
877 .id = -1,
878 .num_resources = ARRAY_SIZE(isif_resource),
879 .resource = isif_resource,
880 .dev = {
881 .dma_mask = &vpfe_capture_dma_mask,
882 .coherent_dma_mask = DMA_BIT_MASK(32),
883 .platform_data = dm365_isif_setup_pinmux,
884 },
885};
886
887static struct resource dm365_osd_resources[] = {
888 {
889 .start = DM365_OSD_BASE,
890 .end = DM365_OSD_BASE + 0xff,
891 .flags = IORESOURCE_MEM,
892 },
893};
894
895static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
896
897static struct platform_device dm365_osd_dev = {
898 .name = DM365_VPBE_OSD_SUBDEV_NAME,
899 .id = -1,
900 .num_resources = ARRAY_SIZE(dm365_osd_resources),
901 .resource = dm365_osd_resources,
902 .dev = {
903 .dma_mask = &dm365_video_dma_mask,
904 .coherent_dma_mask = DMA_BIT_MASK(32),
905 },
906};
907
908static struct resource dm365_venc_resources[] = {
909 {
910 .start = IRQ_VENCINT,
911 .end = IRQ_VENCINT,
912 .flags = IORESOURCE_IRQ,
913 },
914 /* venc registers io space */
915 {
916 .start = DM365_VENC_BASE,
917 .end = DM365_VENC_BASE + 0x177,
918 .flags = IORESOURCE_MEM,
919 },
920 /* vdaccfg registers io space */
921 {
922 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
923 .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
924 .flags = IORESOURCE_MEM,
925 },
926};
927
928static struct resource dm365_v4l2_disp_resources[] = {
929 {
930 .start = IRQ_VENCINT,
931 .end = IRQ_VENCINT,
932 .flags = IORESOURCE_IRQ,
933 },
934 /* venc registers io space */
935 {
936 .start = DM365_VENC_BASE,
937 .end = DM365_VENC_BASE + 0x177,
938 .flags = IORESOURCE_MEM,
939 },
940};
941
942static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
943{
944 switch (if_type) {
945 case MEDIA_BUS_FMT_SGRBG8_1X8:
946 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
947 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
948 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
949 break;
950 case MEDIA_BUS_FMT_YUYV10_1X20:
951 if (field)
952 davinci_cfg_reg(DM365_VOUT_FIELD);
953 else
954 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
955 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
956 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
957 break;
958 default:
959 return -EINVAL;
960 }
961
962 return 0;
963}
964
965static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
966 unsigned int pclock)
967{
968 void __iomem *vpss_clkctl_reg;
969 u32 val;
970
971 vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
972
973 switch (type) {
974 case VPBE_ENC_STD:
975 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
976 break;
977 case VPBE_ENC_DV_TIMINGS:
978 if (pclock <= 27000000) {
979 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
980 } else {
981 /* set sysclk4 to output 74.25 MHz from pll1 */
982 val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
983 VPSS_VENCCLKEN_ENABLE;
984 }
985 break;
986 default:
987 return -EINVAL;
988 }
989 writel(val, vpss_clkctl_reg);
990
991 return 0;
992}
993
994static struct platform_device dm365_vpbe_display = {
995 .name = "vpbe-v4l2",
996 .id = -1,
997 .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources),
998 .resource = dm365_v4l2_disp_resources,
999 .dev = {
1000 .dma_mask = &dm365_video_dma_mask,
1001 .coherent_dma_mask = DMA_BIT_MASK(32),
1002 },
1003};
1004
1005static struct venc_platform_data dm365_venc_pdata = {
1006 .setup_pinmux = dm365_vpbe_setup_pinmux,
1007 .setup_clock = dm365_venc_setup_clock,
1008};
1009
1010static struct platform_device dm365_venc_dev = {
1011 .name = DM365_VPBE_VENC_SUBDEV_NAME,
1012 .id = -1,
1013 .num_resources = ARRAY_SIZE(dm365_venc_resources),
1014 .resource = dm365_venc_resources,
1015 .dev = {
1016 .dma_mask = &dm365_video_dma_mask,
1017 .coherent_dma_mask = DMA_BIT_MASK(32),
1018 .platform_data = (void *)&dm365_venc_pdata,
1019 },
1020};
1021
1022static struct platform_device dm365_vpbe_dev = {
1023 .name = "vpbe_controller",
1024 .id = -1,
1025 .dev = {
1026 .dma_mask = &dm365_video_dma_mask,
1027 .coherent_dma_mask = DMA_BIT_MASK(32),
1028 },
1029};
1030
1031int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
1032 struct vpbe_config *vpbe_cfg)
1033{
1034 if (vpfe_cfg || vpbe_cfg)
1035 platform_device_register(&dm365_vpss_device);
1036
1037 if (vpfe_cfg) {
1038 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1039 platform_device_register(&dm365_isif_dev);
1040 platform_device_register(&vpfe_capture_dev);
1041 }
1042 if (vpbe_cfg) {
1043 dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
1044 platform_device_register(&dm365_osd_dev);
1045 platform_device_register(&dm365_venc_dev);
1046 platform_device_register(&dm365_vpbe_dev);
1047 platform_device_register(&dm365_vpbe_display);
1048 }
1049
1050 return 0;
1051}
1052
1053static int __init dm365_init_devices(void)
1054{
1055 struct platform_device *edma_pdev;
1056 int ret = 0;
1057
1058 if (!cpu_is_davinci_dm365())
1059 return 0;
1060
1061 davinci_cfg_reg(DM365_INT_EDMA_CC);
1062 edma_pdev = platform_device_register_full(&dm365_edma_device);
1063 if (IS_ERR(edma_pdev)) {
1064 pr_warn("%s: Failed to register eDMA\n", __func__);
1065 return PTR_ERR(edma_pdev);
1066 }
1067
1068 platform_device_register(&dm365_mdio_device);
1069 platform_device_register(&dm365_emac_device);
1070
1071 ret = davinci_init_wdt();
1072 if (ret)
1073 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1074
1075 return ret;
1076}
1077postcore_initcall(dm365_init_devices);