| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2020 MediaTek Inc. |
| 4 | */ |
| 5 | |
| 6 | |
| 7 | #ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT6873_EMI_H |
| 8 | #define __DT_BINDINGS_INTERCONNECT_MTK_MT6873_EMI_H |
| 9 | |
| 10 | #define MT6873_SLAVE_DDR_EMI 0 |
| 11 | #define MT6873_MASTER_MCUSYS 1 |
| 12 | #define MT6873_MASTER_GPUSYS 2 |
| 13 | #define MT6873_MASTER_MMSYS 3 |
| 14 | #define MT6873_MASTER_MM_VPU 4 |
| 15 | #define MT6873_MASTER_MM_DISP 5 |
| 16 | #define MT6873_MASTER_MM_VDEC 6 |
| 17 | #define MT6873_MASTER_MM_VENC 7 |
| 18 | #define MT6873_MASTER_MM_CAM 8 |
| 19 | #define MT6873_MASTER_MM_IMG 9 |
| 20 | #define MT6873_MASTER_MM_MDP 10 |
| 21 | #define MT6873_MASTER_VPUSYS 11 |
| 22 | #define MT6873_MASTER_VPU_0 12 |
| 23 | #define MT6873_MASTER_VPU_1 13 |
| 24 | #define MT6873_MASTER_MDLASYS 14 |
| 25 | #define MT6873_MASTER_MDLA_0 15 |
| 26 | #define MT6873_MASTER_UFS 16 |
| 27 | #define MT6873_MASTER_PCIE 17 |
| 28 | #define MT6873_MASTER_USB 18 |
| 29 | #define MT6873_MASTER_DBGIF 19 |
| 30 | #define MT6873_SLAVE_HRT_DDR_EMI 20 |
| 31 | #define MT6873_MASTER_HRT_MMSYS 21 |
| 32 | #define MT6873_MASTER_HRT_MM_DISP 22 |
| 33 | #define MT6873_MASTER_HRT_MM_VDEC 23 |
| 34 | #define MT6873_MASTER_HRT_MM_VENC 24 |
| 35 | #define MT6873_MASTER_HRT_MM_CAM 25 |
| 36 | #define MT6873_MASTER_HRT_MM_IMG 26 |
| 37 | #define MT6873_MASTER_HRT_MM_MDP 27 |
| 38 | #define MT6873_MASTER_HRT_DBGIF 28 |
| 39 | #define MT6873_MASTER_WIFI 29 |
| 40 | #define MT6873_MASTER_BT 30 |
| 41 | #define MT6873_MASTER_NETSYS 31 |
| 42 | #endif |