| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2019 MediaTek Inc. |
| 4 | */ |
| 5 | |
| 6 | #ifndef __SND_SOC_MT6660_H |
| 7 | #define __SND_SOC_MT6660_H |
| 8 | |
| 9 | #include <linux/mutex.h> |
| 10 | |
| 11 | struct dbg_internal { |
| 12 | struct dentry *rt_root; |
| 13 | struct dentry *ic_root; |
| 14 | bool rt_dir_create; |
| 15 | struct mutex io_lock; |
| 16 | u16 reg; |
| 17 | u16 size; |
| 18 | u16 data_buffer_size; |
| 19 | void *data_buffer; |
| 20 | }; |
| 21 | |
| 22 | struct dbg_info { |
| 23 | const char *dirname; |
| 24 | const char *devname; |
| 25 | const char *typestr; |
| 26 | void *io_drvdata; |
| 27 | int (*io_read)(void *drvdata, u16 reg, void *val, u16 size); |
| 28 | int (*io_write)(void *drvdata, u16 reg, const void *val, u16 size); |
| 29 | struct dbg_internal internal; |
| 30 | }; |
| 31 | |
| 32 | struct mt6660_chip { |
| 33 | struct i2c_client *i2c; |
| 34 | struct device *dev; |
| 35 | struct snd_soc_component *component; |
| 36 | struct platform_device *param_dev; |
| 37 | struct mutex var_lock; |
| 38 | struct mutex io_lock; |
| 39 | struct dbg_info dbg_info; |
| 40 | u16 chip_rev; |
| 41 | int pwr_cnt; |
| 42 | }; |
| 43 | |
| 44 | #define MT6660_REG_DEVID (0x00) |
| 45 | #define MT6660_REG_SYSTEM_CTRL (0x03) |
| 46 | #define MT6660_REG_IRQ_STATUS1 (0x05) |
| 47 | #define MT6660_REG_ADDA_CLOCK (0x07) |
| 48 | #define MT6660_REG_SERIAL_CFG1 (0x10) |
| 49 | #define MT6660_REG_DATAO_SEL (0x12) |
| 50 | #define MT6660_REG_TDM_CFG3 (0x15) |
| 51 | #define MT6660_REG_HPF_CTRL (0x18) |
| 52 | #define MT6660_REG_HPF1_COEF (0x1A) |
| 53 | #define MT6660_REG_HPF2_COEF (0x1B) |
| 54 | #define MT6660_REG_PATH_BYPASS (0x1E) |
| 55 | #define MT6660_REG_WDT_CTRL (0x20) |
| 56 | #define MT6660_REG_HCLIP_CTRL (0x24) |
| 57 | #define MT6660_REG_VOL_CTRL (0x29) |
| 58 | #define MT6660_REG_SPS_CTRL (0x30) |
| 59 | #define MT6660_REG_SIGMAX (0x33) |
| 60 | #define MT6660_REG_CALI_T0 (0x3F) |
| 61 | #define MT6660_REG_BST_CTRL (0x40) |
| 62 | #define MT6660_REG_PROTECTION_CFG (0x46) |
| 63 | #define MT6660_REG_DA_GAIN (0x4c) |
| 64 | #define MT6660_REG_AUDIO_IN2_SEL (0x50) |
| 65 | #define MT6660_REG_SIG_GAIN (0x51) |
| 66 | #define MT6660_REG_PLL_CFG1 (0x60) |
| 67 | #define MT6660_REG_DRE_CTRL (0x68) |
| 68 | #define MT6660_REG_DRE_THDMODE (0x69) |
| 69 | #define MT6660_REG_DRE_CORASE (0x6B) |
| 70 | #define MT6660_REG_PWM_CTRL (0x70) |
| 71 | #define MT6660_REG_DC_PROTECT_CTRL (0x74) |
| 72 | #define MT6660_REG_ADC_USB_MODE (0x7c) |
| 73 | #define MT6660_REG_INTERNAL_CFG (0x88) |
| 74 | #define MT6660_REG_RESV0 (0x98) |
| 75 | #define MT6660_REG_RESV1 (0x99) |
| 76 | #define MT6660_REG_RESV2 (0x9A) |
| 77 | #define MT6660_REG_RESV3 (0x9B) |
| 78 | #define MT6660_REG_RESV6 (0xA2) |
| 79 | #define MT6660_REG_RESV7 (0xA3) |
| 80 | #define MT6660_REG_RESV10 (0xB0) |
| 81 | #define MT6660_REG_RESV11 (0xB1) |
| 82 | #define MT6660_REG_RESV16 (0xB6) |
| 83 | #define MT6660_REG_RESV17 (0xB7) |
| 84 | #define MT6660_REG_RESV19 (0xB9) |
| 85 | #define MT6660_REG_RESV21 (0xBB) |
| 86 | #define MT6660_REG_RESV23 (0xBD) |
| 87 | #define MT6660_REG_RESV31 (0xD3) |
| 88 | #define MT6660_REG_RESV40 (0xE0) |
| 89 | |
| 90 | #endif /* __SND_SOC_MT6660_H */ |