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xjb04a4022021-11-25 15:01:52 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9#include <dt-bindings/clock/mt6779-clk.h>
10
11#include "clk-mtk.h"
12#include "clk-gate.h"
13
14static const struct mtk_gate_regs img_cg_regs = {
15 .set_ofs = 0x0004,
16 .clr_ofs = 0x0008,
17 .sta_ofs = 0x0000,
18};
19
20#define GATE_IMG(_id, _name, _parent, _shift) \
21 GATE_IMG_FLAGS(_id, _name, _parent, _shift, 0)
22
23#define GATE_IMG_FLAGS(_id, _name, _parent, _shift, _flags) { \
24 .id = _id, \
25 .name = _name, \
26 .parent_name = _parent, \
27 .regs = &img_cg_regs, \
28 .shift = _shift, \
29 .ops = &mtk_clk_gate_ops_setclr, \
30 .flags = _flags, \
31 }
32
33static const struct mtk_gate img_clks[] = {
34 GATE_IMG(CLK_IMG_LARB5, "imgsys_larb5", "img_sel", 0),
35 GATE_IMG(CLK_IMG_LARB6, "imgsys_larb6", "img_sel", 1),
36 GATE_IMG(CLK_IMG_DIP, "imgsys_dip", "img_sel", 2),
37 GATE_IMG(CLK_IMG_MFB, "imgsys_mfb", "img_sel", 6),
38 GATE_IMG(CLK_IMG_WPE_A, "imgsys_wpe_a", "img_sel", 7),
39};
40
41static const struct of_device_id of_match_clk_mt6779_img[] = {
42 { .compatible = "mediatek,mt6779-imgsys", },
43 {}
44};
45
46static int clk_mt6779_img_probe(struct platform_device *pdev)
47{
48 struct clk_onecell_data *clk_data;
49 struct device_node *node = pdev->dev.of_node;
50
51 clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
52
53 mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
54 clk_data);
55
56 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
57}
58
59static struct platform_driver clk_mt6779_img_drv = {
60 .probe = clk_mt6779_img_probe,
61 .driver = {
62 .name = "clk-mt6779-img",
63 .of_match_table = of_match_clk_mt6779_img,
64 },
65};
66
67builtin_platform_driver(clk_mt6779_img_drv);