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192.168.1.100 / T800 / 9df30f9abefda8fcaa429767402f65df8f57c01c / . / src / kernel / linux / v4.19 / drivers / iommu / mtk_iommu.h
blob: 9a75f8e177ab738d1d6275e2dc62d723a50dcd92 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2015-2016 MediaTek Inc.
4 * Author: Honghui Zhang <honghui.zhang@mediatek.com>
5 */
6
7#ifndef _MTK_IOMMU_H_
8#define _MTK_IOMMU_H_
9
10#include <linux/clk.h>
11#include <linux/component.h>
12#include <linux/device.h>
13#include <linux/io.h>
14#include <linux/io-pgtable.h>
15#include <linux/iommu.h>
16#include <linux/list.h>
17#include <linux/spinlock.h>
18#include <soc/mediatek/smi.h>
19
20struct mtk_iommu_suspend_reg {
21 u32 standard_axi_mode;
22 u32 dcm_dis;
23 u32 ctrl_reg;
24 u32 int_control0;
25 u32 int_main_control;
26 u32 ivrp_paddr;
27 u32 vld_pa_rng;
28 u32 wr_len;
29 u32 pt_base;
30};
31
32enum mtk_iommu_plat {
33 M4U_MT2701,
34 M4U_MT2712,
35 M4U_MT6779,
36 M4U_MT8173,
37 M4U_MT8183,
38 M4U_MT6880,
39};
40
41enum mtk_power_type {
42 M4U_POWER_NONE,
43 M4U_POWER_V1,
44 M4U_POWER_V2,
45 M4U_POWER_TYPE_COUNT
46};
47
48#if defined(CONFIG_MTK_IOMMU) || defined(CONFIG_MTK_IOMMU_V2)
49struct mtk_iommu_resv_iova_region;
50#ifdef CONFIG_MTK_IOMMU_V2
51struct mtk_domain_data;
52#endif
53#endif
54
55#define MTK_MAX_IOMMU_COUNT (2)
56struct mtk_iommu_plat_data {
57 enum mtk_iommu_plat m4u_plat;
58 bool has_4gb_mode;
59#if defined(CONFIG_MTK_IOMMU) || defined(CONFIG_MTK_IOMMU_V2)
60 /*
61 * reserve/dir-mapping iova region data
62 * todo: for different reserve needs on multiple iommu domains
63 */
64 const unsigned int resv_cnt;
65 const struct mtk_iommu_resv_iova_region *resv_region;
66#ifdef CONFIG_MTK_IOMMU_V2
67 const struct mtk_domain_data *dom_data;
68#endif
69#endif
70
71 /* HW will use the EMI clock if there isn't the "bclk". */
72 enum mtk_power_type has_bclk;
73 bool reset_axi;
74 bool has_vld_pa_rng;
75 unsigned char larbid_remap[2][MTK_LARB_NR_MAX];
76 bool has_sub_comm[2];
77 bool has_wr_len;
78 bool has_misc_ctrl[2];
79 u32 inv_sel_reg;
80 u32 m4u1_mask;
81#ifdef CONFIG_MTK_IOMMU_V2
82 unsigned char dom_cnt;
83#endif
84};
85
86struct mtk_iommu_domain;
87
88struct mtk_iommu_data {
89 void __iomem *base;
90 int irq;
91 struct device *dev;
92 struct clk *bclk;
93 phys_addr_t protect_base; /* protect memory base */
94 struct mtk_iommu_suspend_reg reg;
95#ifdef CONFIG_MTK_IOMMU_V2
96 struct mtk_iommu_pgtable *pgtable;
97 struct timer_list iommu_isr_pause_timer;
98 bool power_initialized;
99 spinlock_t reg_lock;
100 bool poweron;
101 unsigned long isr_ref;
102#endif
103 struct mtk_iommu_domain *m4u_dom;
104 struct iommu_group *m4u_group;
105 struct mtk_smi_iommu smi_imu; /* SMI larb iommu info */
106 bool dram_is_4gb;
107 bool tlb_flush_active;
108
109 struct iommu_device iommu;
110 const struct mtk_iommu_plat_data *plat_data;
111#if defined(CONFIG_MTK_IOMMU) || defined(CONFIG_MTK_IOMMU_V2)
112 unsigned int m4u_id;
113#endif
114
115 struct list_head list;
116};
117
118static inline int compare_of(struct device *dev, void *data)
119{
120 return dev->of_node == data;
121}
122
123static inline void release_of(struct device *dev, void *data)
124{
125 of_node_put(data);
126}
127
128static inline int mtk_iommu_bind(struct device *dev)
129{
130 struct mtk_iommu_data *data = dev_get_drvdata(dev);
131
132 return component_bind_all(dev, &data->smi_imu);
133}
134
135static inline void mtk_iommu_unbind(struct device *dev)
136{
137 struct mtk_iommu_data *data = dev_get_drvdata(dev);
138
139 component_unbind_all(dev, &data->smi_imu);
140}
141
142#endif