| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* | 
 | 2 |  * TI DaVinci clock definitions | 
 | 3 |  * | 
 | 4 |  * Copyright (C) 2006-2007 Texas Instruments. | 
 | 5 |  * Copyright (C) 2008-2009 Deep Root Systems, LLC | 
 | 6 |  * | 
 | 7 |  * This program is free software; you can redistribute it and/or modify | 
 | 8 |  * it under the terms of the GNU General Public License version 2 as | 
 | 9 |  * published by the Free Software Foundation. | 
 | 10 |  */ | 
 | 11 |  | 
 | 12 | #ifndef __ARCH_ARM_DAVINCI_CLOCK_H | 
 | 13 | #define __ARCH_ARM_DAVINCI_CLOCK_H | 
 | 14 |  | 
 | 15 | /* PLL/Reset register offsets */ | 
 | 16 | #define PLLCTL          0x100 | 
 | 17 | #define PLLCTL_PLLEN    BIT(0) | 
 | 18 | #define PLLCTL_PLLPWRDN	BIT(1) | 
 | 19 | #define PLLCTL_PLLRST	BIT(3) | 
 | 20 | #define PLLCTL_PLLDIS	BIT(4) | 
 | 21 | #define PLLCTL_PLLENSRC	BIT(5) | 
 | 22 | #define PLLCTL_CLKMODE  BIT(8) | 
 | 23 |  | 
 | 24 | #define PLLM		0x110 | 
 | 25 | #define PLLM_PLLM_MASK  0xff | 
 | 26 |  | 
 | 27 | #define PREDIV          0x114 | 
 | 28 | #define PLLDIV1         0x118 | 
 | 29 | #define PLLDIV2         0x11c | 
 | 30 | #define PLLDIV3         0x120 | 
 | 31 | #define POSTDIV         0x128 | 
 | 32 | #define BPDIV           0x12c | 
 | 33 | #define PLLCMD		0x138 | 
 | 34 | #define PLLSTAT		0x13c | 
 | 35 | #define PLLALNCTL	0x140 | 
 | 36 | #define PLLDCHANGE	0x144 | 
 | 37 | #define PLLCKEN		0x148 | 
 | 38 | #define PLLCKSTAT	0x14c | 
 | 39 | #define PLLSYSTAT	0x150 | 
 | 40 | #define PLLDIV4         0x160 | 
 | 41 | #define PLLDIV5         0x164 | 
 | 42 | #define PLLDIV6         0x168 | 
 | 43 | #define PLLDIV7         0x16c | 
 | 44 | #define PLLDIV8         0x170 | 
 | 45 | #define PLLDIV9         0x174 | 
 | 46 | #define PLLDIV_EN       BIT(15) | 
 | 47 | #define PLLDIV_RATIO_MASK 0x1f | 
 | 48 |  | 
 | 49 | /* | 
 | 50 |  * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN | 
 | 51 |  * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us | 
 | 52 |  * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input | 
 | 53 |  * is ~25MHz. Units are micro seconds. | 
 | 54 |  */ | 
 | 55 | #define PLL_BYPASS_TIME		1 | 
 | 56 | /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */ | 
 | 57 | #define PLL_RESET_TIME		1 | 
 | 58 | /* | 
 | 59 |  * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4 | 
 | 60 |  * Units are micro seconds. | 
 | 61 |  */ | 
 | 62 | #define PLL_LOCK_TIME		20 | 
 | 63 |  | 
 | 64 | #endif |