| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file contains the processor specific definitions |
| 3 | * of the TI OMAP24XX. |
| 4 | * |
| 5 | * Copyright (C) 2007 Texas Instruments. |
| 6 | * Copyright (C) 2007 Nokia Corporation. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #ifndef __ASM_ARCH_OMAP2_H |
| 25 | #define __ASM_ARCH_OMAP2_H |
| 26 | |
| 27 | /* |
| 28 | * Please place only base defines here and put the rest in device |
| 29 | * specific headers. Note also that some of these defines are needed |
| 30 | * for omap1 to compile without adding ifdefs. |
| 31 | */ |
| 32 | |
| 33 | #define L4_24XX_BASE 0x48000000 |
| 34 | #define L4_WK_243X_BASE 0x49000000 |
| 35 | #define L3_24XX_BASE 0x68000000 |
| 36 | |
| 37 | /* interrupt controller */ |
| 38 | #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) |
| 39 | #define OMAP24XX_IVA_INTC_BASE 0x40000000 |
| 40 | |
| 41 | #define OMAP242X_CTRL_BASE L4_24XX_BASE |
| 42 | #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) |
| 43 | #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000) |
| 44 | #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000) |
| 45 | #define OMAP2420_PRM_BASE OMAP2420_CM_BASE |
| 46 | #define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000) |
| 47 | #define OMAP2420_SMS_BASE 0x68008000 |
| 48 | #define OMAP2420_GPMC_BASE 0x6800a000 |
| 49 | |
| 50 | #define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000) |
| 51 | #define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000) |
| 52 | #define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000) |
| 53 | #define OMAP2430_PRM_BASE OMAP2430_CM_BASE |
| 54 | |
| 55 | #define OMAP243X_SMS_BASE 0x6C000000 |
| 56 | #define OMAP243X_SDRC_BASE 0x6D000000 |
| 57 | #define OMAP243X_GPMC_BASE 0x6E000000 |
| 58 | #define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000) |
| 59 | #define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE |
| 60 | #define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000) |
| 61 | |
| 62 | /* DSP SS */ |
| 63 | #define OMAP2420_DSP_BASE 0x58000000 |
| 64 | #define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0) |
| 65 | #define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000) |
| 66 | #define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000) |
| 67 | |
| 68 | #define OMAP243X_DSP_BASE 0x5C000000 |
| 69 | #define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0) |
| 70 | #define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000) |
| 71 | |
| 72 | /* Mailbox */ |
| 73 | #define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000) |
| 74 | |
| 75 | /* Camera */ |
| 76 | #define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000) |
| 77 | |
| 78 | /* Security */ |
| 79 | #define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000) |
| 80 | #define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000) |
| 81 | #define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000) |
| 82 | #define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000) |
| 83 | #define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000) |
| 84 | #define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000) |
| 85 | |
| 86 | #endif /* __ASM_ARCH_OMAP2_H */ |
| 87 | |