| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | */ |
| 9 | |
| 10 | #include <linux/irqchip.h> |
| 11 | #include <linux/of.h> |
| 12 | #include <linux/of_platform.h> |
| 13 | #include <linux/mfd/syscon.h> |
| 14 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> |
| 15 | #include <linux/regmap.h> |
| 16 | #include <asm/mach/arch.h> |
| 17 | #include <asm/mach/map.h> |
| 18 | |
| 19 | #include "common.h" |
| 20 | #include "cpuidle.h" |
| 21 | #include "hardware.h" |
| 22 | |
| 23 | static void __init imx6sl_fec_init(void) |
| 24 | { |
| 25 | struct regmap *gpr; |
| 26 | |
| 27 | /* set FEC clock from internal PLL clock source */ |
| 28 | gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sl-iomuxc-gpr"); |
| 29 | if (!IS_ERR(gpr)) { |
| 30 | regmap_update_bits(gpr, IOMUXC_GPR1, |
| 31 | IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK, 0); |
| 32 | regmap_update_bits(gpr, IOMUXC_GPR1, |
| 33 | IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK, 0); |
| 34 | } else { |
| 35 | pr_err("failed to find fsl,imx6sl-iomux-gpr regmap\n"); |
| 36 | } |
| 37 | } |
| 38 | |
| 39 | static void __init imx6sl_init_late(void) |
| 40 | { |
| 41 | /* imx6sl reuses imx6q cpufreq driver */ |
| 42 | if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) |
| 43 | platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); |
| 44 | |
| 45 | if (IS_ENABLED(CONFIG_SOC_IMX6SL) && cpu_is_imx6sl()) |
| 46 | imx6sl_cpuidle_init(); |
| 47 | else if (IS_ENABLED(CONFIG_SOC_IMX6SLL)) |
| 48 | imx6sx_cpuidle_init(); |
| 49 | } |
| 50 | |
| 51 | static void __init imx6sl_init_machine(void) |
| 52 | { |
| 53 | struct device *parent; |
| 54 | |
| 55 | parent = imx_soc_device_init(); |
| 56 | if (parent == NULL) |
| 57 | pr_warn("failed to initialize soc device\n"); |
| 58 | |
| 59 | of_platform_default_populate(NULL, NULL, parent); |
| 60 | |
| 61 | if (cpu_is_imx6sl()) |
| 62 | imx6sl_fec_init(); |
| 63 | imx_anatop_init(); |
| 64 | imx6sl_pm_init(); |
| 65 | } |
| 66 | |
| 67 | static void __init imx6sl_init_irq(void) |
| 68 | { |
| 69 | imx_gpc_check_dt(); |
| 70 | imx_init_revision_from_anatop(); |
| 71 | imx_init_l2cache(); |
| 72 | imx_src_init(); |
| 73 | irqchip_init(); |
| 74 | if (cpu_is_imx6sl()) |
| 75 | imx6_pm_ccm_init("fsl,imx6sl-ccm"); |
| 76 | else |
| 77 | imx6_pm_ccm_init("fsl,imx6sll-ccm"); |
| 78 | } |
| 79 | |
| 80 | static const char * const imx6sl_dt_compat[] __initconst = { |
| 81 | "fsl,imx6sl", |
| 82 | "fsl,imx6sll", |
| 83 | NULL, |
| 84 | }; |
| 85 | |
| 86 | DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)") |
| 87 | .l2c_aux_val = 0, |
| 88 | .l2c_aux_mask = ~0, |
| 89 | .init_irq = imx6sl_init_irq, |
| 90 | .init_machine = imx6sl_init_machine, |
| 91 | .init_late = imx6sl_init_late, |
| 92 | .dt_compat = imx6sl_dt_compat, |
| 93 | MACHINE_END |