| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* | 
|  | 2 | * Copyright 2008 Openmoko, Inc. | 
|  | 3 | * Copyright 2008 Simtec Electronics | 
|  | 4 | *      http://armlinux.simtec.co.uk/ | 
|  | 5 | *      Ben Dooks <ben@simtec.co.uk> | 
|  | 6 | * | 
|  | 7 | * S3C - USB2.0 Highspeed/OtG device PHY registers | 
|  | 8 | * | 
|  | 9 | * This program is free software; you can redistribute it and/or modify | 
|  | 10 | * it under the terms of the GNU General Public License version 2 as | 
|  | 11 | * published by the Free Software Foundation. | 
|  | 12 | */ | 
|  | 13 |  | 
|  | 14 | /* Note, this is a separate header file as some of the clock framework | 
|  | 15 | * needs to touch this if the clk_48m is used as the USB OHCI or other | 
|  | 16 | * peripheral source. | 
|  | 17 | */ | 
|  | 18 |  | 
|  | 19 | #ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H | 
|  | 20 | #define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__ | 
|  | 21 |  | 
|  | 22 | /* S3C64XX_PA_USB_HSPHY */ | 
|  | 23 |  | 
|  | 24 | #define S3C_HSOTG_PHYREG(x)	((x) + S3C_VA_USB_HSPHY) | 
|  | 25 |  | 
|  | 26 | #define S3C_PHYPWR				S3C_HSOTG_PHYREG(0x00) | 
|  | 27 | #define S3C_PHYPWR_NORMAL_MASK			(0x19 << 0) | 
|  | 28 | #define S3C_PHYPWR_OTG_DISABLE			(1 << 4) | 
|  | 29 | #define S3C_PHYPWR_ANALOG_POWERDOWN		(1 << 3) | 
|  | 30 | #define SRC_PHYPWR_FORCE_SUSPEND		(1 << 1) | 
|  | 31 |  | 
|  | 32 | #define S3C_PHYCLK				S3C_HSOTG_PHYREG(0x04) | 
|  | 33 | #define S3C_PHYCLK_MODE_USB11			(1 << 6) | 
|  | 34 | #define S3C_PHYCLK_EXT_OSC			(1 << 5) | 
|  | 35 | #define S3C_PHYCLK_CLK_FORCE			(1 << 4) | 
|  | 36 | #define S3C_PHYCLK_ID_PULL			(1 << 2) | 
|  | 37 | #define S3C_PHYCLK_CLKSEL_MASK			(0x3 << 0) | 
|  | 38 | #define S3C_PHYCLK_CLKSEL_SHIFT			(0) | 
|  | 39 | #define S3C_PHYCLK_CLKSEL_48M			(0x0 << 0) | 
|  | 40 | #define S3C_PHYCLK_CLKSEL_12M			(0x2 << 0) | 
|  | 41 | #define S3C_PHYCLK_CLKSEL_24M			(0x3 << 0) | 
|  | 42 |  | 
|  | 43 | #define S3C_RSTCON				S3C_HSOTG_PHYREG(0x08) | 
|  | 44 | #define S3C_RSTCON_PHYCLK			(1 << 2) | 
|  | 45 | #define S3C_RSTCON_HCLK				(1 << 1) | 
|  | 46 | #define S3C_RSTCON_PHY				(1 << 0) | 
|  | 47 |  | 
|  | 48 | #define S3C_PHYTUNE				S3C_HSOTG_PHYREG(0x20) | 
|  | 49 |  | 
|  | 50 | #endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */ |