| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | #include <linux/types.h> |
| 3 | #include <linux/errno.h> |
| 4 | #include <linux/uaccess.h> |
| 5 | |
| 6 | #include <asm/sfp-machine.h> |
| 7 | #include <math-emu/soft-fp.h> |
| 8 | |
| 9 | int |
| 10 | mtfsf(unsigned int FM, u32 *frB) |
| 11 | { |
| 12 | u32 mask; |
| 13 | u32 fpscr; |
| 14 | |
| 15 | if (likely(FM == 1)) |
| 16 | mask = 0x0f; |
| 17 | else if (likely(FM == 0xff)) |
| 18 | mask = ~0; |
| 19 | else { |
| 20 | mask = ((FM & 1) | |
| 21 | ((FM << 3) & 0x10) | |
| 22 | ((FM << 6) & 0x100) | |
| 23 | ((FM << 9) & 0x1000) | |
| 24 | ((FM << 12) & 0x10000) | |
| 25 | ((FM << 15) & 0x100000) | |
| 26 | ((FM << 18) & 0x1000000) | |
| 27 | ((FM << 21) & 0x10000000)) * 15; |
| 28 | } |
| 29 | |
| 30 | fpscr = ((__FPU_FPSCR & ~mask) | (frB[1] & mask)) & |
| 31 | ~(FPSCR_VX | FPSCR_FEX | 0x800); |
| 32 | |
| 33 | if (fpscr & (FPSCR_VXSNAN | FPSCR_VXISI | FPSCR_VXIDI | |
| 34 | FPSCR_VXZDZ | FPSCR_VXIMZ | FPSCR_VXVC | |
| 35 | FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI)) |
| 36 | fpscr |= FPSCR_VX; |
| 37 | |
| 38 | /* The bit order of exception enables and exception status |
| 39 | * is the same. Simply shift and mask to check for enabled |
| 40 | * exceptions. |
| 41 | */ |
| 42 | if (fpscr & (fpscr >> 22) & 0xf8) |
| 43 | fpscr |= FPSCR_FEX; |
| 44 | |
| 45 | __FPU_FPSCR = fpscr; |
| 46 | |
| 47 | #ifdef DEBUG |
| 48 | printk("%s: %02x %p: %08lx\n", __func__, FM, frB, __FPU_FPSCR); |
| 49 | #endif |
| 50 | |
| 51 | return 0; |
| 52 | } |