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192.168.1.100 / T800 / ae7cf9c1566c697c2ba616a120c7ff3e90d20dfd / . / src / kernel / linux / v4.19 / drivers / i2c / busses / i2c-mtk.h
blob: b4e46b4d2d9c092fc4838e49b5ff0c67763a6be0 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Camo Xiao <camo.xiao@mediatek.com>
5 *
6 */
7
8#ifndef __I2C_MTK_H__
9#define __I2C_MTK_H__
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <linux/i2c.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/sched/clock.h>
18//#include <linux/sched.h>
19#include <linux/delay.h>
20#include <linux/errno.h>
21#include <linux/err.h>
22#include <linux/device.h>
23#include <linux/platform_device.h>
24#include <linux/wait.h>
25#include <linux/mm.h>
26#include <linux/dma-mapping.h>
27#include <linux/scatterlist.h>
28#include <linux/io.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/clk.h>
32
33#define I2C_DEBUG_FS
34
35#define I3C_EN (0x01 << 15)
36#define I3C_UNLOCK_HFIFO (0x01 << 15)
37#define I3C_NINTH_BIT (0x02 << 8)
38#define MASTER_CODE 0x08
39#define I2C_HFIFO_ADDR_CLR 0x2
40
41#define I2C_HS_HOLD_SEL (0x01 << 15)
42#define I2C_HS_HOLD_TIME (0x01 << 2)
43
44#define I2C_BUS_ERR (0x01 << 8)
45#define I2C_IBI (0x01 << 7)
46#define I2C_DMAERR (0x01 << 6)
47#define I2C_TIMEOUT (0x01 << 5)
48#define I2C_RS_MULTI (0x01 << 4)
49#define I2C_ARB_LOST (0x01 << 3)
50#define I2C_HS_NACKERR (0x01 << 2)
51#define I2C_ACKERR (0x01 << 1)
52#define I2C_TRANSAC_COMP (0x01 << 0)
53#define I2C_INTR_ALL (I2C_BUS_ERR | I2C_IBI | I2C_DMAERR | \
54 I2C_TIMEOUT | I2C_RS_MULTI | \
55 I2C_ARB_LOST | I2C_HS_NACKERR | \
56 I2C_ACKERR | I2C_TRANSAC_COMP)
57#define I2C_TRANSAC_START (0x01 << 0)
58#define I2C_RESUME_ARBIT (0x01 << 1)
59#define I2C_TIMING_STEP_DIV_MASK (0x3f << 0)
60#define I2C_TIMING_SAMPLE_COUNT_MASK (0x7 << 0)
61#define I2C_TIMING_SAMPLE_DIV_MASK (0x7 << 8)
62#define I2C_TIMING_DATA_READ_MASK (0x7 << 12)
63#define I2C_DCM_DISABLE 0x0000
64#define I2C_DCM_ENABLE 0x0007
65#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
66#define I2C_IO_CONFIG_PUSH_PULL 0x0000
67#define I2C_IO_CONFIG_OPEN_DRAIN_AED 0x0000
68#define I2C_IO_CONFIG_PUSH_PULL_AED 0x0000
69#define I2C_IO_CONFIG_AED_MASK (0xfff << 4)
70#define I2C_SOFT_RST 0x0001
71#define I2C_FIFO_ADDR_CLR 0x0001
72#define I2C_FIFO_ADDR_CLR_MCH 0x0004
73#define I2C_DELAY_LEN 0x000A/* not use 0x02 */
74#define I2C_ST_START_CON 0x8001
75#define I2C_FS_START_CON 0x1800
76#define I2C_FS_PLUS_START_CON 0xa0f
77#define I2C_TIME_CLR_VALUE 0x0000
78#define I2C_TIME_DEFAULT_VALUE 0x0001
79#define I2C_HS_SPEED 0x0080
80#define I2C_TIMEOUT_EN 0x0001
81#define I2C_ROLLBACK 0x0001
82#define I2C_SHADOW_REG_MODE 0x0002
83
84#define I2C_HS_NACK_DET_EN (0x1 << 1)
85
86#define I2C_DMA_CON_TX 0x0000
87#define I2C_DMA_CON_RX 0x0001
88#define I2C_DMA_START_EN 0x0001
89#define I2C_DMA_INT_FLAG_NONE 0x0000
90#define I2C_DMA_CLR_FLAG 0x0000
91#define I2C_DMA_WARM_RST 0x0001
92#define I2C_DMA_4G_MODE 0x0001
93
94#define I2C_DMA_DIR_CHANGE (0x1 << 9)
95#define I2C_DMA_SKIP_CONFIG (0x1 << 4)
96#define I2C_DMA_ASYNC_MODE (0x1 << 2)
97
98#define I2C_DEFAUT_SPEED 100000/* hz */
99#define MAX_FS_MODE_SPEED 400000/* hz */
100#define MAX_FS_PLUS_MODE_SPEED 1000000/* hz */
101#define MAX_HS_MODE_SPEED 3400000/* hz */
102#define MAX_DMA_TRANS_SIZE 4096/* 255 */
103#define MAX_CLOCK_DIV 8
104#define MAX_SAMPLE_CNT_DIV 8
105#define MAX_STEP_CNT_DIV 64
106#define MAX_HS_STEP_CNT_DIV 8
107
108#define HALF_DUTY_CYCLE 50
109#define DUTY_CYCLE 45
110
111#define I2C_CONTROL_RS (0x1 << 1)
112#define I2C_CONTROL_DMA_EN (0x1 << 2)
113#define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
114#define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
115#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
116#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
117#define I2C_CONTROL_IRQ_SEL (0x1 << 7)
118#define I2C_CONTROL_DMAACK_EN (0x1 << 8)
119#define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
120#define I2C_CONTROL_WRAPPER (0x1 << 0)
121#define I2C_MCU_INTR_EN 0x1
122#define I2C_CCU_INTR_EN 0x2
123
124#define I2C_RECORD_LEN 10
125#define I2C_MAX_CHANNEL 10
126
127#define MAX_SCL_LOW_TIME 2/* unit: milli-second */
128#define LSAMPLE_MSK 0x1C0
129#define LSTEP_MSK 0x3F
130
131#define I2C_DRV_NAME "mt-i2c"
132#define I2CTAG "[I2C]"
133
134enum {
135 DMA_HW_VERSION0 = 0,
136 DMA_HW_VERSION1 = 1,
137 MDA_SUPPORT_8G = 2,
138 DMA_SUPPORT_64G = 3,
139};
140
141enum DMA_REGS_OFFSET {
142 OFFSET_INT_FLAG = 0x0,
143 OFFSET_INT_EN = 0x04,
144 OFFSET_EN = 0x08,
145 OFFSET_RST = 0x0C,
146 OFFSET_STOP = 0x10,
147 OFFSET_FLUSH = 0x14,
148 OFFSET_CON = 0x18,
149 OFFSET_TX_MEM_ADDR = 0x1C,
150 OFFSET_RX_MEM_ADDR = 0x20,
151 OFFSET_TX_LEN = 0x24,
152 OFFSET_RX_LEN = 0x28,
153 OFFSET_INT_BUF_SIZE = 0x38,
154 OFFSET_DEBUG_STA = 0x50,
155 OFFSET_TX_MEM_ADDR2 = 0x54,
156 OFFSET_RX_MEM_ADDR2 = 0x58,
157 OFFSET_USR_DEF_ADDR = 0x5C,
158 OFFSET_USR_DEF_CTRL = 0x60,
159};
160
161struct i2c_dma_info {
162 unsigned long base;
163 unsigned int int_flag;
164 unsigned int int_en;
165 unsigned int en;
166 unsigned int rst;
167 unsigned int stop;
168 unsigned int flush;
169 unsigned int con;
170 unsigned int tx_mem_addr;
171 unsigned int rx_mem_addr;
172 unsigned int tx_len;
173 unsigned int rx_len;
174 unsigned int int_buf_size;
175 unsigned int debug_sta;
176 unsigned int tx_mem_addr2;
177 unsigned int rx_mem_addr2;
178 unsigned int usr_def_addr;
179 unsigned int use_def_addr;
180};
181
182enum i2c_trans_st_rs {
183 I2C_TRANS_STOP = 0,
184 I2C_TRANS_REPEATED_START,
185};
186
187enum {
188 FS_MODE,
189 HS_MODE,
190};
191
192enum mt_trans_op {
193 I2C_MASTER_WR = 1,
194 I2C_MASTER_RD,
195 I2C_MASTER_WRRD,
196 I2C_MASTER_MULTI_WR,
197};
198
199enum I2C_REGS_OFFSET {
200 OFFSET_DATA_PORT = 0x0,
201 OFFSET_SLAVE_ADDR = 0x04,
202 OFFSET_INTR_MASK = 0x08,
203 OFFSET_INTR_STAT = 0x0c,
204 OFFSET_CONTROL = 0x10,
205 OFFSET_TRANSFER_LEN = 0x14,
206 OFFSET_TRANSAC_LEN = 0x18,
207 OFFSET_DELAY_LEN = 0x1c,
208 OFFSET_TIMING = 0x20,
209 OFFSET_START = 0x24,
210 OFFSET_EXT_CONF = 0x28,
211 OFFSET_LTIMING = 0x2c,
212 OFFSET_FIFO_STAT = 0x30,
213 OFFSET_FIFO_THRESH = 0x34,
214 OFFSET_FIFO_ADDR_CLR = 0x38,
215 OFFSET_IO_CONFIG = 0x40,
216 OFFSET_RSV_DEBUG = 0x44,
217 OFFSET_HS = 0x48,
218 OFFSET_SOFTRESET = 0x50,
219 OFFSET_DCM_EN = 0x54,
220 OFFSET_PATH_DIR = 0x60,
221 OFFSET_DEBUGSTAT = 0x64,
222 OFFSET_DEBUGCTRL = 0x68,
223 OFFSET_TRANSFER_LEN_AUX = 0x6c,
224 OFFSET_CLOCK_DIV = 0x70,
225
226 /* v2 add */
227 OFFSET_HW_TIMEOUT = 0xfff,
228 OFFSET_MCU_INTR = 0xfff,
229 OFFSET_TRAFFIC = 0xfff,
230 OFFSET_COMMAND = 0xfff,
231 OFFSET_CRC_CODE_ = 0xfff,
232 OFFSET_TERNARY = 0xfff,
233 OFFSET_IBI_TIMING = 0xfff,
234 OFFSET_SHAPE = 0xfff,
235 OFFSET_HFIFO_DATA = 0xfff,
236 OFFSET_ERROR = 0xfff,
237 OFFSET_DELAY_STEP = 0xfff,
238 OFFSET_DELAY_SAMPLE = 0xfff,
239 OFFSET_DMA_INFO = 0xfff,
240 OFFSET_IRQ_INFO = 0xfff,
241 OFFSET_DMA_FSM_DEBUG = 0xfff,
242 OFFSET_HFIFO_STAT = 0xfff,
243 OFFSET_MULTI_DMA = 0xfff,
244 OFFSET_ROLLBACK = 0xfff,
245};
246
247enum I2C_REGS_OFFSET_V2 {
248 V2_OFFSET_DATA_PORT = 0x0,
249 V2_OFFSET_SLAVE_ADDR = 0x04,
250 V2_OFFSET_INTR_MASK = 0x08,
251 V2_OFFSET_INTR_STAT = 0x0c,
252 V2_OFFSET_CONTROL = 0x10,
253 V2_OFFSET_TRANSFER_LEN = 0x14,
254 V2_OFFSET_TRANSAC_LEN = 0x18,
255 V2_OFFSET_DELAY_LEN = 0x1c,
256 V2_OFFSET_TIMING = 0x20,
257 V2_OFFSET_START = 0x24,
258 V2_OFFSET_EXT_CONF = 0x28,
259 V2_OFFSET_LTIMING = 0x2c,
260 V2_OFFSET_FIFO_ADDR_CLR = 0x38,
261 V2_OFFSET_SOFTRESET = 0x50,
262
263 /* v2 use different offset */
264 V2_OFFSET_HS = 0x30,
265 V2_OFFSET_IO_CONFIG = 0x34,
266 V2_OFFSET_TRANSFER_LEN_AUX = 0x44,
267 V2_OFFSET_CLOCK_DIV = 0x48,
268 V2_OFFSET_HW_TIMEOUT = 0x4c,
269 V2_OFFSET_DEBUGSTAT = 0xe4,
270 V2_OFFSET_DEBUGCTRL = 0xe8,
271 V2_OFFSET_FIFO_STAT = 0xf4,
272 V2_OFFSET_FIFO_THRESH = 0xf8,
273 V2_OFFSET_AED_PATCH = 0x80,
274
275 /* v2 add */
276 V2_OFFSET_MCU_INTR = 0x40,
277 V2_OFFSET_TRAFFIC = 0x54,
278 V2_OFFSET_COMMAND = 0x58,
279 V2_OFFSET_CRC_CODE_ = 0x5c,
280 V2_OFFSET_TERNARY = 0x60,
281 V2_OFFSET_IBI_TIMING = 0x64,
282 V2_OFFSET_SHAPE = 0x6c,
283 V2_OFFSET_HFIFO_DATA = 0x70,
284 V2_OFFSET_ERROR = 0x84,
285 V2_OFFSET_DELAY_STEP = 0xd4,
286 V2_OFFSET_DELAY_SAMPLE = 0xd8,
287 V2_OFFSET_DMA_INFO = 0xdc,
288 V2_OFFSET_IRQ_INFO = 0xe0,
289 V2_OFFSET_DMA_FSM_DEBUG = 0xec,
290 V2_OFFSET_HFIFO_STAT = 0xfc,
291 V2_OFFSET_MULTI_DMA = 0xf8c,
292 V2_OFFSET_ROLLBACK = 0xf98,
293
294 /* not in v2 */
295 V2_OFFSET_DCM_EN = 0xfff,/*0x54*/
296 V2_OFFSET_PATH_DIR = 0xfff,/*0x60*/
297};
298
299struct i2c_info {
300 unsigned int slave_addr;
301 unsigned int intr_stat;
302 unsigned int control;
303 unsigned int fifo_stat;
304 unsigned int debug_stat;
305 unsigned int tmo;
306 unsigned long long end_time;
307};
308
309enum PERICFG_OFFSET {
310 OFFSET_PERI_I2C_MODE_ENABLE = 0x0410,
311};
312
313struct mt_i2c_data {
314 unsigned int clk_frequency; /* bus speed in Hz */
315 unsigned int flags;
316 unsigned int clk_src_div;
317};
318
319struct i2c_dma_buf {
320 u8 *vaddr;
321 dma_addr_t paddr;
322};
323
324struct mt_i2c_ext {
325#define I2C_A_FILTER_MSG 0x00000001
326 bool isEnable;
327 bool isFilterMsg;
328 bool is_ch_offset;
329 u32 timing;
330 u16 ch_offset;
331 u16 ch_offset_dma;
332};
333
334struct mtk_i2c_compatible {
335 unsigned char dma_support;
336 /* 0 : original; 1: 4gb support 2: 33bit support; 3: 36 bit support */
337 unsigned char idvfs_i2c;
338 /* compatible before chip, set 1 if no TRANSFER_LEN_AUX */
339 unsigned char set_dt_div;/* use dt to set div */
340 unsigned char check_max_freq;/* check max freq */
341 unsigned char set_ltiming;/* need to set LTIMING */
342 unsigned char set_aed;/* need to set AED */
343 unsigned char ver;/* controller version */
344 unsigned char dma_ver;/* dma controller version */
345 /* for constraint of SAMPLE_CNT_DIV and STEP_CNT_DIV of mt6765 */
346 /* 1, has-a-constraint; 0, no constraint */
347 unsigned char cnt_constraint;
348 /* only for MT6768 */
349 /* this option control defined when nack error or ack error occurs */
350 /* 0 : disable, 1 : enable*/
351 unsigned char control_irq_sel;
352 u16 ext_time_config;
353 char clk_compatible[128];
354 u16 clk_sta_offset[I2C_MAX_CHANNEL];/* I2C clock status register */
355 u8 cg_bit[I2C_MAX_CHANNEL];/* i2c clock bit */
356 u32 clk_sel_offset;
357 u32 arbit_offset;
358};
359
360struct mt_i2c {
361 struct i2c_adapter adap;/* i2c host adapter */
362 struct device *dev;
363 wait_queue_head_t wait;/* i2c transfer wait queue */
364 /* set in i2c probe */
365 void __iomem *base;/* i2c base addr */
366 void __iomem *pdmabase;/* dma base address*/
367 void __iomem *gpiobase;/* gpio base address */
368 int irqnr; /* i2c interrupt number */
369 int id;
370 int scl_gpio_id; /* SCL GPIO number */
371 int sda_gpio_id; /* SDA GPIO number */
372 unsigned int gpio_start;
373 unsigned int mem_len;
374 unsigned int offset_eh_cfg;
375 unsigned int offset_pu_cfg;
376 unsigned int offset_rsel_cfg;
377 struct i2c_dma_buf dma_buf;/* memory alloc for DMA mode */
378 struct clk *clk_main;/* main clock for i2c bus */
379 struct clk *clk_dma;/* DMA clock for i2c via DMA */
380 struct clk *clk_pmic;/* PMIC clock for i2c from PMIC */
381 struct clk *clk_arb;/* Arbitrator clock for i2c */
382 struct clk *clk_pal;
383 bool have_pmic;/* can use i2c pins form PMIC */
384 bool have_dcm;/* HW DCM function */
385 bool use_push_pull;/* IO config push-pull mode */
386 bool appm;/* I2C for APPM */
387 bool gpupm;/* I2C for GPUPM */
388 bool buffermode; /* I2C Buffer mode support */
389 bool hs_only; /* I2C HS only */
390 bool fifo_only; /* i2c fifo mode only, does not have dma HW support */
391 /* set when doing the transfer */
392 u16 irq_stat; /* interrupt status */
393 u16 i3c_en; /* i3c enalbe */
394 unsigned int speed_hz;/* The speed in transfer */
395 unsigned int clk_src_div;
396 unsigned int aed;/* aed value from dt */
397 spinlock_t cg_lock;
398 int cg_cnt;
399 bool trans_stop;/* i2c transfer stop */
400 enum mt_trans_op op;
401 u16 total_len;
402 u16 msg_len;
403 u8 *msg_buf; /* pointer to msg data */
404 u16 msg_aux_len;/* WRRD mode to set AUX_LEN register */
405 u16 addr;/* 7bit slave address, without read/write bit */
406 u16 timing_reg;
407 u16 ltiming_reg;
408 u16 high_speed_reg;
409 u16 clk_sta_offset;
410 u8 cg_bit;
411 bool is_hw_trig;
412 bool is_ccu_trig;
413 bool suspended;
414 int rec_idx;/* next record idx */
415 u32 ch_offset_default;
416 u32 ch_offset;
417 u32 ch_offset_dma_default;
418 u32 ch_offset_dma;
419 bool skip_scp_sema;
420 bool has_ccu;
421 u32 ccu_offset;
422 unsigned long main_clk;
423 struct mutex i2c_mutex;
424 struct mt_i2c_ext ext_data;
425 const struct mtk_i2c_compatible *dev_comp;
426 struct i2c_info rec_info[I2C_RECORD_LEN];
427};
428
429#if defined(CONFIG_MTK_FPGA) || defined(CONFIG_FPGA_EARLY_PORTING)
430#define CONFIG_MT_I2C_FPGA_ENABLE
431#endif
432
433#if (defined(CONFIG_MT_I2C_FPGA_ENABLE))
434#define FPGA_CLOCK 12000/* FPGA crystal frequency (KHz) */
435#define I2C_CLK_DIV (5)/* frequency divider */
436#define I2C_CLK_RATE ((FPGA_CLOCK / I2C_CLK_DIV) * 1000)
437/* Hz for FPGA I2C work frequency */
438#endif
439
440extern void gpio_dump_regs_range(int start, int end);
441extern void i2c_dump_info(struct mt_i2c *i2c);
442#if defined(CONFIG_MTK_GIC_EXT)
443extern void mt_irq_dump_status(unsigned int irq);
444#endif
445extern unsigned int enable_4G(void);
446extern int mtk_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
447 int num, u32 ext_flag, u32 timing);
448extern void mt_irq_dump_status(unsigned int irq);
449extern int hw_trig_i2c_enable(struct i2c_adapter *adap);
450extern int hw_trig_i2c_disable(struct i2c_adapter *adap);
451extern int hw_trig_i2c_transfer(struct i2c_adapter *adap,
452 struct i2c_msg *msgs, int num);
453extern int i2c_ccu_enable(struct i2c_adapter *adap, u16 ch_offset);
454extern int i2c_ccu_disable(struct i2c_adapter *adap);
455
456#endif