| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* z0194a.h Sharp z0194a tuner support |
| 2 | * |
| 3 | * Copyright (C) 2008 Igor M. Liplianin (liplianin@me.by) |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the |
| 7 | * Free Software Foundation, version 2. |
| 8 | * |
| 9 | * see Documentation/media/dvb-drivers/dvb-usb.rst for more information |
| 10 | */ |
| 11 | |
| 12 | #ifndef Z0194A |
| 13 | #define Z0194A |
| 14 | |
| 15 | static int sharp_z0194a_set_symbol_rate(struct dvb_frontend *fe, |
| 16 | u32 srate, u32 ratio) |
| 17 | { |
| 18 | u8 aclk = 0; |
| 19 | u8 bclk = 0; |
| 20 | |
| 21 | if (srate < 1500000) { |
| 22 | aclk = 0xb7; bclk = 0x47; } |
| 23 | else if (srate < 3000000) { |
| 24 | aclk = 0xb7; bclk = 0x4b; } |
| 25 | else if (srate < 7000000) { |
| 26 | aclk = 0xb7; bclk = 0x4f; } |
| 27 | else if (srate < 14000000) { |
| 28 | aclk = 0xb7; bclk = 0x53; } |
| 29 | else if (srate < 30000000) { |
| 30 | aclk = 0xb6; bclk = 0x53; } |
| 31 | else if (srate < 45000000) { |
| 32 | aclk = 0xb4; bclk = 0x51; } |
| 33 | |
| 34 | stv0299_writereg(fe, 0x13, aclk); |
| 35 | stv0299_writereg(fe, 0x14, bclk); |
| 36 | stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff); |
| 37 | stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff); |
| 38 | stv0299_writereg(fe, 0x21, (ratio) & 0xf0); |
| 39 | |
| 40 | return 0; |
| 41 | } |
| 42 | |
| 43 | static u8 sharp_z0194a_inittab[] = { |
| 44 | 0x01, 0x15, |
| 45 | 0x02, 0x30, |
| 46 | 0x03, 0x00, |
| 47 | 0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */ |
| 48 | 0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */ |
| 49 | 0x06, 0x40, /* DAC not used, set to high impendance mode */ |
| 50 | 0x07, 0x00, /* DAC LSB */ |
| 51 | 0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */ |
| 52 | 0x09, 0x00, /* FIFO */ |
| 53 | 0x0c, 0x51, /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */ |
| 54 | 0x0d, 0x82, /* DC offset compensation = ON, beta_agc1 = 2 */ |
| 55 | 0x0e, 0x23, /* alpha_tmg = 2, beta_tmg = 3 */ |
| 56 | 0x10, 0x3f, /* AGC2 0x3d */ |
| 57 | 0x11, 0x84, |
| 58 | 0x12, 0xb9, |
| 59 | 0x15, 0xc9, /* lock detector threshold */ |
| 60 | 0x16, 0x00, |
| 61 | 0x17, 0x00, |
| 62 | 0x18, 0x00, |
| 63 | 0x19, 0x00, |
| 64 | 0x1a, 0x00, |
| 65 | 0x1f, 0x50, |
| 66 | 0x20, 0x00, |
| 67 | 0x21, 0x00, |
| 68 | 0x22, 0x00, |
| 69 | 0x23, 0x00, |
| 70 | 0x28, 0x00, /* out imp: normal out type: parallel FEC mode:0 */ |
| 71 | 0x29, 0x1e, /* 1/2 threshold */ |
| 72 | 0x2a, 0x14, /* 2/3 threshold */ |
| 73 | 0x2b, 0x0f, /* 3/4 threshold */ |
| 74 | 0x2c, 0x09, /* 5/6 threshold */ |
| 75 | 0x2d, 0x05, /* 7/8 threshold */ |
| 76 | 0x2e, 0x01, |
| 77 | 0x31, 0x1f, /* test all FECs */ |
| 78 | 0x32, 0x19, /* viterbi and synchro search */ |
| 79 | 0x33, 0xfc, /* rs control */ |
| 80 | 0x34, 0x93, /* error control */ |
| 81 | 0x0f, 0x52, |
| 82 | 0xff, 0xff |
| 83 | }; |
| 84 | |
| 85 | #endif |