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192.168.1.100 / T800 / ae7cf9c1566c697c2ba616a120c7ff3e90d20dfd / . / src / kernel / linux / v4.19 / drivers / phy / mediatek / phy-mtk-fpga.c
blob: 0facb18f247351ae1e7f7975b3530d98c86007ca [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
5 *
6 */
7
8#include <dt-bindings/phy/phy.h>
9#include <linux/debugfs.h>
10#include <linux/delay.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/of_address.h>
14#include <linux/platform_device.h>
15#include <linux/seq_file.h>
16#include <linux/uaccess.h>
17#include <mtu3.h>
18#include "phy-mtk-fpga.h"
19
20/* ------------------------ I2C IO API ------------------------------ */
21
22#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
23static inline void i2c_dummy_delay(int count)
24{
25 udelay(count);
26}
27
28static void gpio_set_direction(void __iomem *port,
29 enum i2c_pin pin, enum i2c_dir dir)
30{
31 void __iomem *addr;
32 u32 temp;
33
34 addr = port + SSUSB_FPGA_I2C_OUT;
35 temp = readl(addr);
36
37 if (pin == I2C_SDA) {
38 if (dir == I2C_OUTPUT)
39 temp |= SSUSB_FPGA_I2C_SDA_OEN;
40 else
41 temp &= ~SSUSB_FPGA_I2C_SDA_OEN;
42 } else {
43 if (dir == I2C_OUTPUT)
44 temp |= SSUSB_FPGA_I2C_SCL_OEN;
45 else
46 temp &= ~SSUSB_FPGA_I2C_SCL_OEN;
47 }
48 writel(temp, addr);
49}
50
51static void gpio_set_value(void __iomem *port,
52 enum i2c_pin pin, bool value)
53{
54 void __iomem *addr;
55 u32 temp;
56
57 addr = port + SSUSB_FPGA_I2C_OUT;
58 temp = readl(addr);
59
60 if (pin == I2C_SDA) {
61 if (value)
62 temp |= SSUSB_FPGA_I2C_SDA_OUT;
63 else
64 temp &= ~SSUSB_FPGA_I2C_SDA_OUT;
65 } else {
66 if (value)
67 temp |= SSUSB_FPGA_I2C_SCL_OUT;
68 else
69 temp &= ~SSUSB_FPGA_I2C_SCL_OUT;
70 }
71 writel(temp, addr);
72}
73
74static int gpio_get_value(void __iomem *port, enum i2c_pin pin)
75{
76 void __iomem *addr;
77 u32 temp;
78
79 addr = port + SSUSB_FPGA_I2C_IN;
80 temp = readl(addr);
81
82 if (pin == I2C_SDA)
83 temp &= SSUSB_FPGA_I2C_SDA_IN;
84 else
85 temp &= SSUSB_FPGA_I2C_SCL_IN;
86
87 return !!temp;
88}
89
90static void i2c_stop(void __iomem *port)
91{
92 gpio_set_direction(port, I2C_SDA, I2C_OUTPUT);
93 gpio_set_value(port, I2C_SCL, 0);
94 i2c_dummy_delay(I2C_DELAY);
95 gpio_set_value(port, I2C_SDA, 0);
96 i2c_dummy_delay(I2C_DELAY);
97 gpio_set_value(port, I2C_SCL, 1);
98 i2c_dummy_delay(I2C_DELAY);
99 gpio_set_value(port, I2C_SDA, 1);
100 i2c_dummy_delay(I2C_DELAY);
101 gpio_set_direction(port, I2C_SCL, I2C_INPUT);
102 gpio_set_direction(port, I2C_SDA, I2C_INPUT);
103}
104
105/* Prepare the I2C_SDA and I2C_SCL for sending/receiving */
106static void i2c_start(void __iomem *port)
107{
108 gpio_set_direction(port, I2C_SCL, I2C_OUTPUT);
109 gpio_set_direction(port, I2C_SDA, I2C_OUTPUT);
110 gpio_set_value(port, I2C_SDA, 1);
111 i2c_dummy_delay(I2C_DELAY);
112 gpio_set_value(port, I2C_SCL, 1);
113 i2c_dummy_delay(I2C_DELAY);
114 gpio_set_value(port, I2C_SDA, 0);
115 i2c_dummy_delay(I2C_DELAY);
116 gpio_set_value(port, I2C_SCL, 0);
117 i2c_dummy_delay(I2C_DELAY);
118}
119
120/* return 0 --> ack */
121static u32 i2c_send_byte(void __iomem *port, u8 data)
122{
123 int i, ack;
124
125 gpio_set_direction(port, I2C_SDA, I2C_OUTPUT);
126
127 for (i = 8; --i > 0;) {
128 gpio_set_value(port, I2C_SDA, (data >> i) & 0x1);
129 i2c_dummy_delay(I2C_DELAY);
130 gpio_set_value(port, I2C_SCL, 1);
131 i2c_dummy_delay(I2C_DELAY);
132 gpio_set_value(port, I2C_SCL, 0);
133 i2c_dummy_delay(I2C_DELAY);
134 }
135 gpio_set_value(port, I2C_SDA, (data >> i) & 0x1);
136 i2c_dummy_delay(I2C_DELAY);
137 gpio_set_value(port, I2C_SCL, 1);
138 i2c_dummy_delay(I2C_DELAY);
139 gpio_set_value(port, I2C_SCL, 0);
140 i2c_dummy_delay(I2C_DELAY);
141
142 gpio_set_value(port, I2C_SDA, 0);
143 i2c_dummy_delay(I2C_DELAY);
144 gpio_set_direction(port, I2C_SDA, I2C_INPUT);
145 i2c_dummy_delay(I2C_DELAY);
146 gpio_set_value(port, I2C_SCL, 1);
147 i2c_dummy_delay(I2C_DELAY);
148 /* ack 1: error, 0:ok */
149 ack = gpio_get_value(port, I2C_SDA);
150 gpio_set_value(port, I2C_SCL, 0);
151 i2c_dummy_delay(I2C_DELAY);
152
153 return (ack == 1) ? PHY_FALSE : PHY_TRUE;
154}
155
156static void i2c_receive_byte(void __iomem *port, u8 *data, u8 ack)
157{
158 int i;
159 u32 dataCache = 0;
160
161 gpio_set_direction(port, I2C_SDA, I2C_INPUT);
162
163 for (i = 8; --i >= 0;) {
164 dataCache <<= 1;
165 i2c_dummy_delay(I2C_DELAY);
166 gpio_set_value(port, I2C_SCL, 1);
167 i2c_dummy_delay(I2C_DELAY);
168 dataCache |= gpio_get_value(port, I2C_SDA);
169 gpio_set_value(port, I2C_SCL, 0);
170 i2c_dummy_delay(I2C_DELAY);
171 }
172 gpio_set_direction(port, I2C_SDA, I2C_OUTPUT);
173 gpio_set_value(port, I2C_SDA, ack);
174 i2c_dummy_delay(I2C_DELAY);
175 gpio_set_value(port, I2C_SCL, 1);
176 i2c_dummy_delay(I2C_DELAY);
177 gpio_set_value(port, I2C_SCL, 0);
178 i2c_dummy_delay(I2C_DELAY);
179 *data = (u8)dataCache;
180}
181
182static int i2c_write_reg(void __iomem *port, u8 i2c_addr, u8 addr, u8 data)
183{
184 int ack = 0;
185
186 i2c_start(port);
187
188 ack = i2c_send_byte(port, (i2c_addr << 1) & 0xff);
189 if (ack)
190 ack = i2c_send_byte(port, addr);
191 else
192 return PHY_FALSE;
193
194 ack = i2c_send_byte(port, data);
195 if (ack) {
196 i2c_stop(port);
197 return PHY_FALSE;
198 } else {
199 return PHY_TRUE;
200 }
201}
202
203static int i2c_read_reg(void __iomem *port, u8 i2c_addr, u8 addr, u8 *data)
204{
205 int ack = 0;
206
207 i2c_start(port);
208
209 ack = i2c_send_byte(port, (i2c_addr << 1) & 0xff);
210 if (ack)
211 ack = i2c_send_byte(port, addr);
212 else
213 return PHY_FALSE;
214
215 i2c_start(port);
216
217 ack = i2c_send_byte(port, ((i2c_addr << 1) & 0xff) | 0x1);
218 /* ack 0: ok, 1 error */
219 if (ack)
220 i2c_receive_byte(port, data, 1);
221 else
222 return PHY_FALSE;
223
224 i2c_stop(port);
225 return ack;
226}
227
228int phy_writeb(void __iomem *port, u8 i2c_addr, u8 addr, u8 value)
229{
230 i2c_write_reg(port, i2c_addr, addr, value);
231 return PHY_TRUE;
232}
233
234u8 phy_readb(void __iomem *port, u8 i2c_addr, u8 addr)
235{
236 u8 buf;
237 int ret;
238
239 ret = i2c_read_reg(port, i2c_addr, addr, &buf);
240 if (ret == PHY_FALSE) {
241 pr_err("Read failed(i2c_addr: %d, addr: 0x%x)\n",
242 i2c_addr, addr);
243 return ret;
244 }
245
246 return buf;
247}
248
249static int phy_writel(void __iomem *port, u8 i2c_addr, u32 addr, u32 data)
250{
251 u8 addr8;
252 u8 data_0, data_1, data_2, data_3;
253
254 addr8 = addr & 0xff;
255 data_0 = data & 0xff;
256 data_1 = (data >> 8) & 0xff;
257 data_2 = (data >> 16) & 0xff;
258 data_3 = (data >> 24) & 0xff;
259
260 phy_writeb(port, i2c_addr, addr8, data_0);
261 phy_writeb(port, i2c_addr, addr8 + 1, data_1);
262 phy_writeb(port, i2c_addr, addr8 + 2, data_2);
263 phy_writeb(port, i2c_addr, addr8 + 3, data_3);
264
265 return 0;
266}
267
268static u32 phy_readl(void __iomem *port, u8 i2c_addr, u32 addr)
269{
270 u8 addr8;
271 u32 data;
272
273 addr8 = addr & 0xff;
274
275 data = phy_readb(port, i2c_addr, addr8);
276 data |= (phy_readb(port, i2c_addr, addr8 + 1) << 8);
277 data |= (phy_readb(port, i2c_addr, addr8 + 2) << 16);
278 data |= (phy_readb(port, i2c_addr, addr8 + 3) << 24);
279
280 return data;
281}
282
283static u32 __maybe_unused phy_readlmsk(void __iomem *port, u8 i2c_addr,
284 u32 reg_addr32, u32 offset, u32 mask)
285{
286 u32 value;
287
288 value = phy_readl(port, i2c_addr, reg_addr32);
289 return ((value & mask) >> offset);
290}
291
292static int phy_writelmsk(void __iomem *port, u8 i2c_addr,
293 u32 reg_addr32, u32 offset, u32 mask, u32 data)
294{
295 u32 cur_value;
296 u32 new_value;
297
298 cur_value = phy_readl(port, i2c_addr, reg_addr32);
299 new_value = (cur_value & (~mask)) | ((data << offset) & mask);
300 phy_writel(port, i2c_addr, reg_addr32, new_value);
301
302 return 0;
303}
304#else
305unsigned int I2cWriteReg(unsigned char dev_id, unsigned char addr, unsigned char val)
306{
307 if (IS_PRINT)
308 pr_info("I2C Write@%x [%x]=%x\n", dev_id, addr, val);
309
310 writew((dev_id << 1), ADDR_I2C_SLAVE_ADDR);
311 writew(2, ADDR_I2C_TRANSFER_LEN);
312
313 /* ADDITIONAL CONTROL */
314 writew(0x1, REG_I2C_TRANSAC_LEN);
315 writew(0x1303, REG_I2C_HTIMING);
316 writew(0x13C3, REG_I2C_LTIMING);
317
318 writew(addr, ADDR_I2C_DATA_PORT);
319 writew(val, ADDR_I2C_DATA_PORT);
320
321 writew(REG_I2C_START_BIT, ADDR_I2C_START);
322
323 while ((readw(ADDR_I2C_START) & REG_I2C_START_BIT))
324 ;
325
326 return PHY_TRUE;
327}
328
329unsigned int I2cReadReg(unsigned char dev_id, unsigned char addr, unsigned char *data)
330{
331 if (IS_PRINT)
332 pr_info("I2C Read@%x [%x]\n", dev_id, addr);
333
334 writew((dev_id << 1), ADDR_I2C_SLAVE_ADDR);
335 writew(1, ADDR_I2C_TRANSFER_LEN);
336
337 /* ADDITIONAL CONTROL */
338 writew(0x1, REG_I2C_TRANSAC_LEN);
339 writew(0x1303, REG_I2C_HTIMING);
340 writew(0x13C3, REG_I2C_LTIMING);
341
342 writew(addr, ADDR_I2C_DATA_PORT);
343 writew(REG_I2C_START_BIT, ADDR_I2C_START);
344
345 while ((readw(ADDR_I2C_START) & REG_I2C_START_BIT))
346 ;
347
348 writew((dev_id << 1) | I2C_READ_BIT, ADDR_I2C_SLAVE_ADDR);
349 writew(1, ADDR_I2C_TRANSFER_LEN);
350
351 /* ADDITIONAL CONTROL */
352 writew(0x1, REG_I2C_TRANSAC_LEN);
353 writew(0x1303, REG_I2C_HTIMING);
354 writew(0x13C3, REG_I2C_LTIMING);
355
356 writew(REG_I2C_START_BIT, ADDR_I2C_START);
357
358 while ((readw(ADDR_I2C_START) & REG_I2C_START_BIT))
359 ;
360
361 *data = readw(ADDR_I2C_DATA_PORT);
362
363 if (IS_PRINT)
364 pr_info("I2C Read [%x]=%x\n", addr, *data);
365
366 return PHY_TRUE; /* !!(unsigned int)*data; */
367}
368
369void _U3_Write_Bank(unsigned int bankValue)
370{
371 I2cWriteReg(U3_PHY_I2C_DEV, U3_PHY_PAGE, bankValue);
372}
373
374unsigned int _U3Write_Reg(unsigned int address, unsigned int value)
375{
376 I2cWriteReg(U3_PHY_I2C_DEV, address, value);
377 return PHY_TRUE;
378}
379
380unsigned int _U3Read_Reg(unsigned int address)
381{
382 char *pu1Buf;
383 unsigned int ret;
384
385 pu1Buf = kmalloc(1, GFP_NOIO);
386 ret = I2cReadReg(U3_PHY_I2C_DEV, address, pu1Buf);
387 if (ret == PHY_FALSE) {
388 pr_err("Read failed\n");
389 return PHY_FALSE;
390 }
391 ret = (char)pu1Buf[0];
392 kfree(pu1Buf);
393 return ret;
394
395}
396
397unsigned int U3PhyWriteReg32(unsigned int addr, unsigned int data)
398{
399 unsigned int bank;
400 unsigned int addr8;
401 unsigned int data_0, data_1, data_2, data_3;
402
403 bank = (addr >> 16) & 0xff;
404 addr8 = addr & 0xff;
405 data_0 = data & 0xff;
406 data_1 = (data >> 8) & 0xff;
407 data_2 = (data >> 16) & 0xff;
408 data_3 = (data >> 24) & 0xff;
409
410 pr_info("addr: %x, data: %x\n", addr8, data);
411 _U3_Write_Bank(bank);
412 pr_info("addr: %x, data: %x\n", addr8, data_0);
413 _U3Write_Reg(addr8, data_0);
414 pr_info("addr: %x, data: %x\n", addr8 + 1, data_1);
415 _U3Write_Reg(addr8 + 1, data_1);
416 pr_info("addr: %x, data: %x\n", addr8 + 2, data_2);
417 _U3Write_Reg(addr8 + 2, data_2);
418 pr_info("addr: %x, data: %x\n", addr8 + 3, data_3);
419 _U3Write_Reg(addr8 + 3, data_3);
420
421 return 0;
422}
423
424unsigned int U3PhyReadReg32(unsigned int addr)
425{
426 unsigned int bank;
427 unsigned int addr8;
428 unsigned int data;
429
430 bank = (addr >> 16) & 0xff;
431 addr8 = addr & 0xff;
432
433 _U3_Write_Bank(bank);
434 data = _U3Read_Reg(addr8);
435 data |= (_U3Read_Reg(addr8 + 1) << 8);
436 data |= (_U3Read_Reg(addr8 + 2) << 16);
437 data |= (_U3Read_Reg(addr8 + 3) << 24);
438
439 return data;
440}
441
442unsigned int U3PhyWriteReg8(unsigned int addr, unsigned char data)
443{
444 unsigned int bank;
445 unsigned int addr8;
446
447 bank = (addr >> 16) & 0xff;
448 addr8 = addr & 0xff;
449 _U3_Write_Bank(bank);
450 _U3Write_Reg(addr8, data);
451
452 pr_debug("addr: %x, data: %x\n", addr8, data);
453
454 return PHY_TRUE;
455}
456
457unsigned char U3PhyReadReg8(unsigned int addr)
458{
459 unsigned int bank;
460 unsigned int addr8;
461 unsigned int data;
462
463 bank = (addr >> 16) & 0xff;
464 addr8 = addr & 0xff;
465 _U3_Write_Bank(bank);
466 data = _U3Read_Reg(addr8);
467
468 return data;
469}
470
471unsigned int U3PhyWriteField8(phys_addr_t addr, unsigned int offset, unsigned int mask, unsigned int value)
472{
473 char cur_value;
474 char new_value;
475
476 cur_value = U3PhyReadReg8((u3phy_addr_t) addr);
477 new_value = (cur_value & (~mask)) | ((value << offset) & mask);
478
479 mb(); /* avoid context switch */
480 /**/ U3PhyWriteReg8((u3phy_addr_t) addr, new_value);
481
482 mb(); /* avoid context switch */
483 /**/ return PHY_TRUE;
484}
485
486unsigned int U3PhyWriteField32(phys_addr_t addr, unsigned int offset, unsigned int mask, unsigned int value)
487{
488 unsigned int cur_value;
489 unsigned int new_value;
490
491 cur_value = U3PhyReadReg32((u3phy_addr_t) addr);
492 new_value = (cur_value & (~mask)) | ((value << offset) & mask);
493
494 mb(); /* avoid context switch */
495 /**/ U3PhyWriteReg32((u3phy_addr_t) addr, new_value);
496
497 mb(); /* avoid context switch */
498 /**/ return PHY_TRUE;
499}
500
501unsigned int U3PhyReadField8(phys_addr_t addr, unsigned int offset, unsigned int mask)
502{
503 return (U3PhyReadReg8((u3phy_addr_t) addr) & mask) >> offset;
504}
505
506unsigned int U3PhyReadField32(phys_addr_t addr, unsigned int offset, unsigned int mask)
507{
508
509 return (U3PhyReadReg32((u3phy_addr_t) addr) & mask) >> offset;
510}
511#endif
512
513/* ------------------------ SUB BOARD INIT API ------------------------------ */
514
515unsigned int ssusb_read_phy_version(struct fpga_u3phy *u3phy,
516 struct fpga_phy_instance *instance)
517{
518 u32 version;
519#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
520 void __iomem *i2c = instance->i2c_base;
521
522
523 phy_writeb(i2c, 0x60, 0xff, SSUSB_PHY_VERSION_BANK);
524 version = phy_readl(i2c, 0x60, SSUSB_PHY_VERSION_ADDR);
525#else
526 version = U3PhyReadReg32(0x2000e4);
527#endif
528 dev_info(u3phy->dev, "ssusb phy version: %x\n", version);
529
530 return version;
531}
532
533static int a60931_u3phy_init(struct fpga_u3phy *u3phy,
534 struct fpga_phy_instance *instance)
535{
536#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
537 void __iomem *i2c = instance->i2c_base;
538 dev_info(u3phy->dev, "%s\n", __func__);
539
540 /* 0xFC[31:24], Change bank address to 0 */
541 phy_writeb(i2c, 0x60, 0xff, 0x0);
542 /* 0x14[14:12], RG_USB20_HSTX_SRCTRL, set U2 slew rate as 4 */
543 phy_writelmsk(i2c, 0x60, 0x14, 12, GENMASK(14, 12), 0x4);
544 /* 0x18[23:23], RG_USB20_BC11_SW_EN, Disable BC 1.1 */
545 phy_writelmsk(i2c, 0x60, 0x18, 23, BIT(23), 0x0);
546 /* 0x68[18:18], force_suspendm = 0 */
547 phy_writelmsk(i2c, 0x60, 0x68, 18, BIT(18), 0x0);
548 /* 0xFC[31:24], Change bank address to 0x30 */
549 phy_writeb(i2c, 0x60, 0xff, 0x30);
550 /* 0x04[29:29], RG_VUSB10_ON, SSUSB 1.0V power ON */
551 phy_writelmsk(i2c, 0x60, 0x04, 29, BIT(29), 0x1);
552 /* 0x04[25:21], RG_SSUSB_XTAL_TOP_RESERVE */
553 phy_writelmsk(i2c, 0x60, 0x04, 21, GENMASK(25, 21), 0x11);
554 /* 0xFC[31:24], Change bank address to 0x40 */
555 phy_writeb(i2c, 0x60, 0xff, 0x40);
556 /* 0x38[15:0], DA_SSUSB_PLL_SSC_DELTA1 */
557 /* fine tune SSC delta1 to let SSC min average ~0ppm */
558 phy_writelmsk(i2c, 0x60, 0x38, 0, GENMASK(15, 0)<<0, 0x47);
559 /* 0x40[31:16], DA_SSUSB_PLL_SSC_DELTA */
560 /* fine tune SSC delta to let SSC min average ~0ppm */
561 phy_writelmsk(i2c, 0x60, 0x40, 16, GENMASK(31, 16), 0x44);
562 /* 0xFC[31:24], Change bank address to 0x30 */
563 phy_writeb(i2c, 0x60, 0xff, 0x30);
564 /* 0x14[15:0], RG_SSUSB_PLL_SSC_PRD */
565 /* fine tune SSC PRD to let SSC freq average 31.5KHz */
566 phy_writelmsk(i2c, 0x60, 0x14, 0, GENMASK(15, 0), 0x190);
567 /* 0xFC[31:24], Change bank address to 0x70 */
568 phy_writeb(i2c, 0x70, 0xff, 0x70);
569 /* 0x88[3:2], Pipe reset, clk driving current */
570 phy_writelmsk(i2c, 0x70, 0x88, 2, GENMASK(3, 2), 0x1);
571 /* 0x88[5:4], Data lane 0 driving current */
572 phy_writelmsk(i2c, 0x70, 0x88, 4, GENMASK(5, 4), 0x1);
573 /* 0x88[7:6], Data lane 1 driving current */
574 phy_writelmsk(i2c, 0x70, 0x88, 6, GENMASK(7, 6), 0x1);
575 /* 0x88[9:8], Data lane 2 driving current */
576 phy_writelmsk(i2c, 0x70, 0x88, 8, GENMASK(9, 8), 0x1);
577 /* 0x88[11:10], Data lane 3 driving current */
578 phy_writelmsk(i2c, 0x70, 0x88, 10, GENMASK(11, 10), 0x1);
579 /* 0x9C[4:0], rg_ssusb_ckphase, PCLK phase 0x00~0x1F */
580 phy_writelmsk(i2c, 0x70, 0x9c, 0, GENMASK(4, 0), 0x19);
581
582 /* Set INTR & TX/RX Impedance */
583
584 /* 0xFC[31:24], Change bank address to 0x30 */
585 phy_writeb(i2c, 0x60, 0xff, 0x30);
586 /* 0x00[26:26], RG_SSUSB_INTR_EN */
587 phy_writelmsk(i2c, 0x60, 0x00, 26, BIT(26), 0x1);
588 /* 0x00[15:10], RG_SSUSB_IEXT_INTR_CTRL, Set Iext R selection */
589 phy_writelmsk(i2c, 0x60, 0x00, 10, GENMASK(15, 10), 0x26);
590 /* 0xFC[31:24], Change bank address to 0x10 */
591 phy_writeb(i2c, 0x60, 0xff, 0x10);
592 /* 0x10[31:31], rg_ssusb_force_tx_impsel, enable */
593 phy_writelmsk(i2c, 0x60, 0x10, 31, BIT(31), 0x1);
594 /* 0x10[28:24], rg_ssusb_tx_impsel, Set TX Impedance */
595 phy_writelmsk(i2c, 0x60, 0x10, 24, GENMASK(28, 24), 0x10);
596 /* 0x14[31:31], rg_ssusb_force_rx_impsel, enable */
597 phy_writelmsk(i2c, 0x60, 0x14, 31, BIT(31), 0x1);
598 /* 0x14[28:24], rg_ssusb_rx_impsel, Set RX Impedance */
599 phy_writelmsk(i2c, 0x60, 0x14, 24, GENMASK(28, 24), 0x10);
600 /* 0xFC[31:24], Change bank address to 0x00 */
601 phy_writeb(i2c, 0x60, 0xff, 0x00);
602 /* 0x00[05:05], RG_USB20_INTR_EN, U2 INTR_EN */
603 phy_writelmsk(i2c, 0x60, 0x00, 5, BIT(5), 0x1);
604 /* 0x04[23:19], RG_USB20_INTR_CAL, Set Iext R selection */
605 phy_writelmsk(i2c, 0x60, 0x04, 19, GENMASK(23, 19), 0x14);
606#else
607 dev_info(u3phy->dev, "%s\n", __func__);
608
609 /*
610 //U2PHY inital
611 I2C 0x60 0xFC[31:24] 0x00 RW //Change bank address to 0x00
612 I2C 0x60 0x00[00:00] 0x01 RW RG_SIFSLV_BGR_EN //USB20_BGR_EN
613 I2C 0x60 0x00[05:05] 0x01 RW RG_USB20_INTR_EN //RG_USB20_INTR_EN
614 I2C 0x60 0x04[23:19] 0x10 RW RG_USB20_INTR_CAL //RG_USB20_INTR_CAL
615 I2C 0x60 0x18[23:23] 0x00 RW RG_USB20_BC11_SW_EN //RG_USB20_BC11_SW_EN, Disable BC 1.1
616 I2C 0x60 0x68[18:18] 0x00 RW force_suspendm //force_suspendm = 0
617 I2C 0x60 0x68[03:03] 0x01 RW RG_SUSPENDM //RG_SUSPENDM when force_suspendm = 1
618 //U2PHY patch
619 I2C 0x60 0x14[14:12] 0x04 RW RG_USB20_HSTX_SRCTRL
620 I2C 0x60 0x18[03:00] 0x03 RW RG_USB20_SQTH
621 */
622 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u2phy_reg_a->usbphyacr0),
623 A60931_RG_SIFSLV_BGR_EN_OFST, A60931_RG_SIFSLV_BGR_EN, 0x1);
624 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u2phy_reg_a->usbphyacr0),
625 A60931_RG_USB20_INTR_EN_OFST, A60931_RG_USB20_INTR_EN, 0x1);
626 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u2phy_reg_a->usbphyacr1),
627 A60931_RG_USB20_INTR_CAL_OFST, A60931_RG_USB20_INTR_CAL, 0x10);
628 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u2phy_reg_a->usbphyacr6),
629 A60931_RG_USB20_BC11_SW_EN_OFST, A60931_RG_USB20_BC11_SW_EN, 0x0);
630 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u2phy_reg_a->u2phydtm0),
631 A60931_FORCE_SUSPENDM_OFST, A60931_FORCE_SUSPENDM, 0x0);
632 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u2phy_reg_a->u2phydtm0),
633 A60931_RG_SUSPENDM_OFST, A60931_RG_SUSPENDM, 0x1);
634 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u2phy_reg_a->usbphyacr5),
635 A60931_RG_USB20_HSTX_SRCTRL_OFST, A60931_RG_USB20_HSTX_SRCTRL, 0x4);
636 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u2phy_reg_a->usbphyacr6),
637 A60931_RG_USB20_SQTH_OFST, A60931_RG_USB20_SQTH, 0x3);
638
639 /*
640 //USB 3.0
641 //TPHY Init
642 I2C 0x60 0xFC[31:24] 0x30 RW //Change bank address to 0x30
643 I2C 0x60 0x18[24:24] 0x01 RW RG_SSUSB_LN0_CDR_RESERVE //AVDD10 source select
644 I2C 0x60 0xFC[31:24] 0x40 RW //Change bank address to 0x40
645 I2C 0x60 0x60[13:12] 0x02 RW RG_SSUSB_LFPS_DEGLITCH_U3 //
646
647 I2C 0x60 0xFC[31:24] 0x30 RW //Change bank address to 0x30
648 I2C 0x60 0x04[29:29] 0x01 RW RG_VUSB10_ON //SSUSB 1.0V power ON
649 I2C 0x60 0x04[25:21] 0x11 RW RG_SSUSB_XTAL_TOP_RESERVE //RG_SSUSB_XTAL_TOP_RESERVE<15:11> =10001
650
651 I2C 0x60 0xFC[31:24] 0x40 RW //Change bank address to 0x40
652 I2C 0x60 0x38[15:00] 0x47 RW DA_SSUSB_PLL_SSC_DELTA1 //fine tune SSC delta1 to let SSC min average ~0ppm
653 I2C 0x60 0x40[31:16] 0x44 RW DA_SSUSB_PLL_SSC_DELTA //fine tune SSC delta to let SSC min average ~0ppm
654 I2C 0x60 0xFC[31:24] 0x30 RW //Change bank address to 0x30
655 I2C 0x60 0x14[15:00] 0x190 RW RG_SSUSB_PLL_SSC_PRD //fine tune SSC PRD to let SSC freq average 31.5KHz
656
657 //I2C 0x60 0xFC[31:24] 0x10 RW //Change bank address to 0x10
658 //I2C 0x60 0x08[22:22] 0x00 RW rg_ssusb_p3_entry //disable ssusb_p3_entry to work around resume from P3
659 //I2C 0x60 0x08[23:23] 0x01 RW rg_ssusb_p3_entry_sel //force disable ssusb_p3_entry to work around resume from P3
660 //I2C 0x60 0xFC[31:24] 0x60 RW //Change bank address to 0x60
661 //I2C 0x60 0x14[24:24] 0x00 RW rg_ssusb_p3_bias_pwd //disable ssusb_p3_bias_pwd to work around resume from P3
662 */
663 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phya_reg_a->reg6),
664 A60931_RG_SSUSB_LN0_CDR_RESERVE_OFST, A60931_RG_SSUSB_LN0_CDR_RESERVE, 0x1);
665 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phya_da_reg_a->reg32),
666 A60931_RG_SSUSB_LFPS_DEGLITCH_U3_OFST,
667 A60931_RG_SSUSB_LFPS_DEGLITCH_U3, 0x02);
668 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phya_reg_a->reg1),
669 A60931_RG_VUSB10_ON_OFST, A60931_RG_VUSB10_ON, 0x1);
670 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phya_reg_a->reg1),
671 A60931_RG_SSUSB_XTAL_TOP_RESERVE_OFST,
672 A60931_RG_SSUSB_XTAL_TOP_RESERVE, 0x11);
673 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phya_da_reg_a->reg19),
674 A60931_RG_SSUSB_PLL_SSC_DELTA1_U3_OFST,
675 A60931_RG_SSUSB_PLL_SSC_DELTA1_U3, 0x47);
676 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phya_da_reg_a->reg21),
677 A60931_RG_SSUSB_PLL_SSC_DELTA_U3_OFST,
678 A60931_RG_SSUSB_PLL_SSC_DELTA_U3, 0x44);
679 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phya_reg_a->reg7),
680 A60931_RG_SSUSB_PLL_SSC_PRD_OFST, A60931_RG_SSUSB_PLL_SSC_PRD, 0x190);
681
682 /*
683 //Set INTR & TX/RX Impedance
684 I2C 0x60 0xFC[31:24] 0x30 RW //Change bank address to 0x30
685 I2C 0x60 0x00[26:26] 0x01 RW RG_SSUSB_INTR_EN //INTR_EN
686 I2C 0x60 0x00[15:10] 0x28 RW RG_SSUSB_IEXT_INTR_CTRL //Set Iext R selection
687 I2C 0x60 0xFC[31:24] 0x10 RW //Change bank address to 0x10
688 I2C 0x60 0x10[31:31] 0x01 RW rg_ssusb_force_tx_impsel //Force da_ssusb_tx_impsel enable
689 I2C 0x60 0x10[28:24] 0x11 RW rg_ssusb_tx_impsel //Set TX Impedance
690 I2C 0x60 0x14[31:31] 0x01 RW rg_ssusb_force_rx_impsel //Force da_ssusb_rx_impsel enable
691 I2C 0x60 0x14[28:24] 0x10 RW rg_ssusb_rx_impsel //Set RX Impedance
692 I2C 0x60 0xFC[31:24] 0x00 RW //Change bank address to 0x00
693 I2C 0x60 0x00[05:05] 0x01 RW RG_USB20_INTR_EN //U2 INTR_EN
694 I2C 0x60 0x04[23:19] 0x13 RW RG_USB20_INTR_CAL //Set Iext R selection
695 */
696 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phya_reg_a->reg0),
697 A60931_RG_SSUSB_INTR_EN_OFST, A60931_RG_SSUSB_INTR_EN, 0x1);
698 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phya_reg_a->reg0),
699 A60931_RG_SSUSB_IEXT_INTR_CTRL_OFST, A60931_RG_SSUSB_IEXT_INTR_CTRL, 0x28);
700 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phyd_reg_a->phyd_impcal0),
701 A60931_RG_SSUSB_FORCE_TX_IMPSEL_OFST, A60931_RG_SSUSB_FORCE_TX_IMPSEL, 0x1);
702 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phyd_reg_a->phyd_impcal0),
703 A60931_RG_SSUSB_TX_IMPSEL_OFST, A60931_RG_SSUSB_TX_IMPSEL, 0x11);
704 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phyd_reg_a->phyd_impcal1),
705 A60931_RG_SSUSB_FORCE_RX_IMPSEL_OFST, A60931_RG_SSUSB_FORCE_RX_IMPSEL, 0x1);
706 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phyd_reg_a->phyd_impcal1),
707 A60931_RG_SSUSB_RX_IMPSEL_OFST, A60931_RG_SSUSB_RX_IMPSEL, 0x10);
708 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u2phy_reg_a->usbphyacr0),
709 A60931_RG_USB20_INTR_EN_OFST, A60931_RG_USB20_INTR_EN, 0x1);
710 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u2phy_reg_a->usbphyacr1),
711 A60931_RG_USB20_INTR_CAL_OFST, A60931_RG_USB20_INTR_CAL, 0x13);
712
713 /*
714 //RX_DET timing patch
715 I2C 0x60 0xFC[31:24] 0x20 RW
716 I2C 0x60 0x28[08:00] 0x50 RW rg_ssusb_rxdet_stb1_set
717 I2C 0x60 0x28[17:09] 0x10 RW rg_ssusb_rxdet_stb2_set
718 I2C 0x60 0x2C[08:00] 0x10 RW rg_ssusb_rxdet_stb2_set_p3
719 I2C 0x60 0xFC[31:24] 0x30 RW
720 I2C 0x60 0x1C[11:10] 0x02 RW RG_SSUSB_RXDET_VTHSEL_L
721 */
722 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phyd_bank2_reg_a->b2_phyd_rxdet1),
723 A60931_RG_SSUSB_RXDET_STB1_SET_OFST, A60931_RG_SSUSB_RXDET_STB1_SET, 0x50);
724 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phyd_bank2_reg_a->b2_phyd_rxdet1),
725 A60931_RG_SSUSB_RXDET_STB2_SET_OFST, A60931_RG_SSUSB_RXDET_STB2_SET, 0x10);
726 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phyd_bank2_reg_a->b2_phyd_rxdet2),
727 A60931_RG_SSUSB_RXDET_STB2_SET_P3_OFST, A60931_RG_SSUSB_RXDET_STB2_SET_P3, 0x10);
728 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_u3phya_reg_a->reg7),
729 A60931_RG_SSUSB_RXDET_VTHSEL_L_OFST, A60931_RG_SSUSB_RXDET_VTHSEL_L, 0x2);
730
731 /*
732 //Adjust pipe_clk phase for FPGA
733 I2C 0x70 0xFC[31:24] 0x70 RW //Change bank address to 0x70
734 I2C 0x70 0x88[03:02] 0x01 RW //Pipe reset, clk driving current
735 I2C 0x70 0x88[05:04] 0x01 RW //Data lane 0 driving current
736 I2C 0x70 0x88[07:06] 0x01 RW //Data lane 1 driving current
737 I2C 0x70 0x88[09:08] 0x01 RW //Data lane 2 driving current
738 I2C 0x70 0x88[11:10] 0x01 RW //Data lane 3 driving current
739 I2C 0x70 0x9C[04:00] 0x03 RW rg_ssusb_ckphase //PCLK phase 0x00~0x1F <-- adjust timing
740 */
741 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_sifslv_fm_reg_a->reserve6), (2), (0x3<<2), 0x1);
742 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_sifslv_fm_reg_a->reserve6), (4), (0x3<<4), 0x1);
743 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_sifslv_fm_reg_a->reserve6), (6), (0x3<<6), 0x1);
744 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_sifslv_fm_reg_a->reserve6), (8), (0x3<<8), 0x1);
745 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_sifslv_fm_reg_a->reserve6), (10), (0x3<<10), 0x1);
746 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_sifslv_fm_reg_a->reserve11), (0), (0x1f<<0), 0x3);
747#endif
748 return 0;
749}
750
751static void a60931_u3phy_set_pclk(struct fpga_u3phy *u3phy,
752 struct fpga_phy_instance *instance, int pclk)
753{
754#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
755 void __iomem *i2c = instance->i2c_base;
756
757 phy_writeb(i2c, 0x70, 0xff, 0x70);
758 phy_writelmsk(i2c, 0x70, 0x9c, 0, GENMASK(4, 0), pclk);
759#else
760 U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.a60931_sifslv_fm_reg_a->reserve11), (0), (0x1f<<0), pclk);
761#endif
762}
763
764static int a60810_u3phy_init(struct fpga_u3phy *u3phy,
765 struct fpga_phy_instance *instance)
766{
767#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
768 void __iomem *i2c = instance->i2c_base;
769 dev_info(u3phy->dev, "%s\n", __func__);
770
771 phy_writeb(i2c, 0x60, 0xFF, 0x00);
772 phy_writeb(i2c, 0x60, 0x05, 0x55);
773 phy_writeb(i2c, 0x60, 0x18, 0x84);
774
775 phy_writeb(i2c, 0x60, 0xFF, 0x10);
776 phy_writeb(i2c, 0x60, 0x0A, 0x84);
777
778 phy_writeb(i2c, 0x60, 0xFF, 0x40);
779 phy_writeb(i2c, 0x60, 0x38, 0x46);
780 phy_writeb(i2c, 0x60, 0x42, 0x40);
781 phy_writeb(i2c, 0x60, 0x08, 0xAB);
782 phy_writeb(i2c, 0x60, 0x09, 0x0C);
783 phy_writeb(i2c, 0x60, 0x0C, 0x71);
784 phy_writeb(i2c, 0x60, 0x0E, 0x4F);
785 phy_writeb(i2c, 0x60, 0x10, 0xE1);
786 phy_writeb(i2c, 0x60, 0x14, 0x5F);
787
788 phy_writeb(i2c, 0x60, 0xFF, 0x60);
789 phy_writeb(i2c, 0x60, 0x14, 0x03);
790
791 phy_writeb(i2c, 0x60, 0xFF, 0x00);
792 phy_writeb(i2c, 0x60, 0x6A, 0x04);
793 phy_writeb(i2c, 0x60, 0x68, 0x08);
794 phy_writeb(i2c, 0x60, 0x6C, 0x26);
795 phy_writeb(i2c, 0x60, 0x6D, 0x36);
796#else
797 dev_info(u3phy->dev, "%s\n", __func__);
798
799 /* BANK 0x00 */
800 /* for U2 hS eye diagram */
801 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_u2phy_reg_a->usbphyacr1)
802 , A60810_RG_USB20_TERM_VREF_SEL_OFST, A60810_RG_USB20_TERM_VREF_SEL,
803 0x05);
804 /* for U2 hS eye diagram */
805 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_u2phy_reg_a->usbphyacr1)
806 , A60810_RG_USB20_VRT_VREF_SEL_OFST, A60810_RG_USB20_VRT_VREF_SEL, 0x05);
807 /* for U2 sensititvity */
808 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_u2phy_reg_a->usbphyacr6)
809 , A60810_RG_USB20_SQTH_OFST, A60810_RG_USB20_SQTH, 0x04);
810
811 /* BANK 0x10 */
812 /* disable ssusb_p3_entry to work around resume from P3 bug */
813 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_u3phyd_reg_a->phyd_lfps0)
814 , A60810_RG_SSUSB_P3_ENTRY_OFST, A60810_RG_SSUSB_P3_ENTRY, 0x00);
815 /* force disable ssusb_p3_entry to work around resume from P3 bug */
816 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_u3phyd_reg_a->phyd_lfps0)
817 , A60810_RG_SSUSB_P3_ENTRY_SEL_OFST, A60810_RG_SSUSB_P3_ENTRY_SEL, 0x01);
818
819
820 /* BANK 0x40 */
821 /* fine tune SSC delta1 to let SSC min average ~0ppm */
822 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_u3phya_da_reg_a->reg19)
823 , A60810_RG_SSUSB_PLL_SSC_DELTA1_U3_OFST,
824 A60810_RG_SSUSB_PLL_SSC_DELTA1_U3, 0x46);
825 /* U3PhyWriteField32(((phys_addr_t)(uintptr_t)&instance->info.u3phya_da_reg_a->reg19) */
826 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_u3phya_da_reg_a->reg21)
827 , A60810_RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST,
828 A60810_RG_SSUSB_PLL_SSC_DELTA1_PE1H, 0x40);
829
830
831 /* fine tune SSC delta to let SSC min average ~0ppm */
832
833 /* Fine tune SYSPLL to improve phase noise */
834 /* I2C 60 0x08[01:00] 0x03 RW RG_SSUSB_PLL_BC_U3 */
835 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_u3phya_da_reg_a->reg4)
836 , A60810_RG_SSUSB_PLL_BC_U3_OFST, A60810_RG_SSUSB_PLL_BC_U3, 0x3);
837 /* I2C 60 0x08[12:10] 0x03 RW RG_SSUSB_PLL_DIVEN_U3 */
838 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_u3phya_da_reg_a->reg4)
839 , A60810_RG_SSUSB_PLL_DIVEN_U3_OFST, A60810_RG_SSUSB_PLL_DIVEN_U3, 0x3);
840 /* I2C 60 0x0C[03:00] 0x01 RW RG_SSUSB_PLL_IC_U3 */
841 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_u3phya_da_reg_a->reg5)
842 , A60810_RG_SSUSB_PLL_IC_U3_OFST, A60810_RG_SSUSB_PLL_IC_U3, 0x1);
843 /* I2C 60 0x0C[23:22] 0x01 RW RG_SSUSB_PLL_BR_U3 */
844 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_u3phya_da_reg_a->reg5)
845 , A60810_RG_SSUSB_PLL_BR_U3_OFST, A60810_RG_SSUSB_PLL_BR_U3, 0x1);
846 /* I2C 60 0x10[03:00] 0x01 RW RG_SSUSB_PLL_IR_U3 */
847 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_u3phya_da_reg_a->reg6)
848 , A60810_RG_SSUSB_PLL_IR_U3_OFST, A60810_RG_SSUSB_PLL_IR_U3, 0x1);
849 /* I2C 60 0x14[03:00] 0x0F RW RG_SSUSB_PLL_BP_U3 */
850 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_u3phya_da_reg_a->reg7)
851/* // , A60810_RG_SSUSB_PLL_BP_U3, A60810_RG_SSUSB_PLL_BP_U3, 0xF); */
852 , A60810_RG_SSUSB_PLL_BP_U3_OFST, A60810_RG_SSUSB_PLL_BP_U3, 0x0f);
853
854 /* BANK 0x60 */
855 /* force xtal pwd mode enable */
856 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_spllc_reg_a->u3d_xtalctl_2)
857 , A60810_RG_SSUSB_FORCE_XTAL_PWD_OFST, A60810_RG_SSUSB_FORCE_XTAL_PWD,
858 0x1);
859 /* force bias pwd mode enable */
860 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_spllc_reg_a->u3d_xtalctl_2)
861 , A60810_RG_SSUSB_FORCE_BIAS_PWD_OFST, A60810_RG_SSUSB_FORCE_BIAS_PWD,
862 0x1);
863 /* force xtal pwd mode off to work around xtal drv de */
864 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_spllc_reg_a->u3d_xtalctl_2)
865 , A60810_RG_SSUSB_XTAL_PWD_OFST, A60810_RG_SSUSB_XTAL_PWD, 0x0);
866 /* force bias pwd mode off to work around xtal drv de */
867 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_spllc_reg_a->u3d_xtalctl_2)
868 , A60810_RG_SSUSB_BIAS_PWD_OFST, A60810_RG_SSUSB_BIAS_PWD, 0x0);
869
870 /* ******** test chip settings *********** */
871 /* BANK 0x00 */
872 /* slew rate setting */
873 U3PhyWriteField32(((phys_addr_t)(uintptr_t) &instance->info.a60810_u2phy_reg_a->usbphyacr5)
874 , A60810_RG_USB20_HSTX_SRCTRL_OFST, A60810_RG_USB20_HSTX_SRCTRL, 0x4);
875
876 /* BANK 0x50 */
877
878 /* Write Phase Scan Result */
879 /* PIPE setting BANK5 */
880 /* PIPE drv = 2 */
881 U3PhyWriteReg8(((phys_addr_t)(uintptr_t) &instance->info.a60810_sifslv_chip_reg_a->gpio_ctla) + 2, 0x10);
882 /* PIPE phase */
883 /* U3PhyWriteReg8(((phys_addr_t)(uintptr_t)&instance->info.sifslv_chip_reg_a->gpio_ctla)+3, 0xdc); */
884 U3PhyWriteReg8(((phys_addr_t)(uintptr_t) &instance->info.a60810_sifslv_chip_reg_a->gpio_ctla) + 3, 0x24);
885#endif
886 return 0;
887}
888
889/* --------------------------- PHY DRIVER API ------------------------------- */
890
891static int fpga_phy_init(struct phy *phy)
892{
893 struct fpga_phy_instance *instance = phy_get_drvdata(phy);
894 struct fpga_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
895
896 switch (instance->chip_version) {
897 case PHY_TEST_CHIP_A60931:
898 #ifndef CONFIG_U3_PHY_GPIO_SUPPORT
899 instance->info.a60931_u2phy_reg_a = (struct a60931_u2phy_reg_a *)0x0;
900 instance->info.a60931_u3phyd_reg_a = (struct a60931_u3phyd_reg_a *)0x100000;
901 instance->info.a60931_u3phyd_bank2_reg_a = (struct a60931_u3phyd_bank2_reg_a *)0x200000;
902 instance->info.a60931_u3phya_reg_a = (struct a60931_u3phya_reg_a*)0x300000;
903 instance->info.a60931_u3phya_da_reg_a = (struct a60931_u3phya_da_reg_a *)0x400000;
904 instance->info.a60931_sifslv_chip_reg_a = (struct a60931_sifslv_chip_reg_a *)0x500000;
905 instance->info.a60931_spllc_reg_a = (struct a60931_spllc_reg_a *)0x600000;
906 instance->info.a60931_sifslv_fm_reg_a = (struct a60931_sifslv_fm_reg_a *)0xf00000;
907 #endif
908
909 a60931_u3phy_init(u3phy, instance);
910 a60931_u3phy_set_pclk(u3phy, instance, instance->u3_pclk);
911 break;
912 case PHY_TEST_CHIP_A60810:
913 #ifndef CONFIG_U3_PHY_GPIO_SUPPORT
914 instance->info.a60810_u2phy_reg_a = (struct a60810_u2phy_reg_a *)0x0;
915 instance->info.a60810_u3phyd_reg_a = (struct a60810_u3phyd_reg_a *)0x100000;
916 instance->info.a60810_u3phyd_bank2_reg_a = (struct a60810_u3phyd_bank2_reg_a *)0x200000;
917 instance->info.a60810_u3phya_reg_a = (struct a60810_u3phya_reg_a*)0x300000;
918 instance->info.a60810_u3phya_da_reg_a = (struct a60810_u3phya_da_reg_a *)0x400000;
919 instance->info.a60810_sifslv_chip_reg_a = (struct a60810_sifslv_chip_reg_a *)0x500000;
920 instance->info.a60810_spllc_reg_a = (struct a60810_spllc_reg_a *)0x600000;
921 instance->info.a60810_sifslv_fm_reg_a = (struct a60810_sifslv_fm_reg_a *)0xf00000;
922 #endif
923
924 a60810_u3phy_init(u3phy, instance);
925 break;
926 default:
927 dev_err(u3phy->dev, "%s: incompatible PHY type:0x%x\n", __func__, instance->chip_version);
928 return -EINVAL;
929 }
930
931 return 0;
932}
933
934int fpga_phy_set_pclk(struct phy *phy, int pclk)
935{
936 struct fpga_phy_instance *instance = phy_get_drvdata(phy);
937 struct fpga_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
938 if (pclk < 0) pclk = instance->u3_pclk;
939
940 switch (instance->chip_version) {
941 case PHY_TEST_CHIP_A60931:
942 a60931_u3phy_set_pclk(u3phy, instance, pclk);
943 break;
944 case PHY_TEST_CHIP_A60810:
945 /* nothing to do */
946 break;
947 default:
948 dev_err(u3phy->dev, "%s: incompatible PHY type:0x%x\n", __func__, instance->chip_version);
949 return -EINVAL;
950 }
951
952 return 0;
953}
954
955static struct phy *fpga_phy_xlate(struct device *dev,
956 struct of_phandle_args *args)
957{
958 struct fpga_u3phy *u3phy = dev_get_drvdata(dev);
959 struct fpga_phy_instance *instance = NULL;
960 struct device_node *phy_np = args->np;
961 int index;
962
963 if (args->args_count != 1) {
964 dev_err(dev, "invalid number of cells in 'phy' property\n");
965 return ERR_PTR(-EINVAL);
966 }
967
968 for (index = 0; index < u3phy->nphys; index++)
969 if (phy_np == u3phy->phys[index]->phy->dev.of_node) {
970 instance = u3phy->phys[index];
971 break;
972 }
973
974 if (!instance) {
975 dev_err(dev, "failed to find appropriate phy\n");
976 return ERR_PTR(-EINVAL);
977 }
978
979 instance->type = args->args[0];
980 if (!(instance->type == PHY_TYPE_USB2 ||
981 instance->type == PHY_TYPE_USB3)) {
982 dev_err(dev, "unsupported device type: %d\n", instance->type);
983 return ERR_PTR(-EINVAL);
984 }
985
986 return instance->phy;
987}
988
989static const struct phy_ops fpga_u3phy_ops = {
990 .init = fpga_phy_init,
991 .owner = THIS_MODULE,
992};
993
994static const struct of_device_id fpga_u3phy_id_table[] = {
995 { .compatible = "mediatek,fpga-u3phy", },
996 { },
997};
998MODULE_DEVICE_TABLE(of, fpga_u3phy_id_table);
999
1000static void dbg_write_reg(struct fpga_phy_instance *instance, const char *buf)
1001{
1002 struct device *dev = instance->dev;
1003 u32 i2c_addr = 0;
1004 u32 addr = 0;
1005 u32 value = 0;
1006 u32 old_val;
1007 u32 new_val;
1008 u32 param;
1009
1010 param = sscanf(buf, "%*s 0x%x 0x%x 0x%x", &i2c_addr, &addr, &value);
1011 dev_info(dev, "params-%d (i2c_addr:%#x, addr:%#x, value:%#x)\n",
1012 param, i2c_addr, addr, value);
1013#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
1014 old_val = phy_readb(instance->i2c_base, i2c_addr, addr);
1015 phy_writeb(instance->i2c_base, i2c_addr, addr, value);
1016 new_val = phy_readb(instance->i2c_base, i2c_addr, addr);
1017#else
1018 old_val = U3PhyReadReg8(addr);
1019 U3PhyWriteReg8(addr, value);
1020 new_val = U3PhyReadReg8(addr);
1021#endif
1022 dev_info(dev, "0x%2.2x: 0x%2.2x --> 0x%2.2x\n",
1023 addr, old_val, new_val);
1024
1025}
1026
1027static void dbg_read_reg(struct fpga_phy_instance *instance, const char *buf)
1028{
1029 struct device *dev = instance->dev;
1030 u32 i2c_addr = 0;
1031 u32 addr = 0;
1032 u32 value = 0;
1033 u32 param;
1034
1035 param = sscanf(buf, "%*s 0x%x 0x%x", &i2c_addr, &addr);
1036 dev_info(dev, "params-%d (i2c_addr: %#x, addr: %#x)\n",
1037 param, i2c_addr, addr);
1038
1039#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
1040 value = phy_readb(instance->i2c_base, i2c_addr, addr);
1041#else
1042 value = U3PhyReadReg8(addr);
1043#endif
1044 dev_info(dev, "0x%2.2x: 0x%2.2x\n", addr, value);
1045}
1046
1047static void dbg_set_pclk(struct fpga_phy_instance *instance, const char *buf)
1048{
1049 struct device *dev = instance->dev;
1050 int pclk;
1051 u32 param;
1052 param = sscanf(buf, "%*s 0x%x", &pclk);
1053 dev_info(dev, "params-%d (pclk: %#x)\n",param, pclk);
1054 fpga_phy_set_pclk(instance->phy, pclk);
1055}
1056
1057static int phy_reg_show(struct seq_file *sf, void *unused)
1058{
1059 struct fpga_phy_instance *instance = sf->private;
1060
1061 seq_printf(sf, "usage: %x\n(echo r[w] i2c_addr reg [value])(HEX)\n"
1062 "e.g. echo r 0x60 0xff > reg\n",
1063 instance->chip_version);
1064
1065 return 0;
1066}
1067
1068static int phy_reg_open(struct inode *inode, struct file *file)
1069{
1070 return single_open(file, phy_reg_show, inode->i_private);
1071}
1072
1073static ssize_t phy_reg_write(struct file *file,
1074 const char __user *ubuf, size_t count, loff_t *ppos)
1075{
1076 struct seq_file *sf = file->private_data;
1077 struct fpga_phy_instance *instance = sf->private;
1078 char buf[128];
1079
1080 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
1081 return -EFAULT;
1082
1083 switch (buf[0]) {
1084 case 'w':
1085 dbg_write_reg(instance, buf);
1086 break;
1087 case 'r':
1088 dbg_read_reg(instance, buf);
1089 break;
1090 case 'p':
1091 dbg_set_pclk(instance, buf);
1092 break;
1093 default:
1094 dev_err(instance->dev, "No such cmd\n");
1095 }
1096
1097 return count;
1098}
1099
1100static const struct file_operations phy_reg_fops = {
1101 .open = phy_reg_open,
1102 .write = phy_reg_write,
1103 .read = seq_read,
1104 .llseek = seq_lseek,
1105 .release = single_release,
1106};
1107
1108static void create_debugfs_interface(struct fpga_u3phy *u3phy,
1109 struct fpga_phy_instance *instance)
1110{
1111 struct dentry *root;
1112
1113 root = debugfs_create_dir(instance->name, u3phy->dbg_root);
1114 if (!root) {
1115 dev_err(u3phy->dev, "create debugfs root failed\n");
1116 return;
1117 }
1118 instance->dbg = root;
1119
1120 debugfs_create_file("reg", 0644, root, instance, &phy_reg_fops);
1121}
1122
1123static int fpga_u3phy_probe(struct platform_device *pdev)
1124{
1125 struct device *dev = &pdev->dev;
1126 struct device_node *np = dev->of_node;
1127 struct device_node *child_np;
1128 struct phy_provider *provider;
1129 struct fpga_u3phy *u3phy;
1130 u32 ippc;
1131 int index;
1132 int ret;
1133
1134 dev_info(dev, "%s\n", __func__);
1135 u3phy = devm_kzalloc(dev, sizeof(*u3phy), GFP_KERNEL);
1136 if (!u3phy)
1137 return -ENOMEM;
1138
1139 u3phy->dbg_root = debugfs_create_dir("fpga_phy", NULL);
1140 if (!u3phy->dbg_root)
1141 return -ENODEV;
1142
1143 u3phy->nphys = of_get_child_count(np);
1144 u3phy->phys = devm_kcalloc(dev, u3phy->nphys,
1145 sizeof(*u3phy->phys), GFP_KERNEL);
1146 if (!u3phy->phys)
1147 return -ENOMEM;
1148
1149 u3phy->dev = dev;
1150 platform_set_drvdata(pdev, u3phy);
1151
1152 ret = of_property_read_u32(np, "mediatek,ippc", &ippc);
1153 if (ret) {
1154 dev_err(dev, "Failed to parse ippc value\n");
1155 return ret;
1156 }
1157 u3phy->ippc_base = ioremap(ippc, SSUSB_IPPC_LEN);
1158
1159 if (!u3phy->ippc_base) {
1160 dev_err(dev, "could not ioremap ippc regs\n");
1161 return -ENOMEM;
1162 }
1163
1164#ifndef CONFIG_U3_PHY_GPIO_SUPPORT
1165 if (!of_property_read_u32(np, "fpga_i2c_physical_base",
1166 (u32 *) &i2c_physical_base))
1167 dev_info(dev, "%s, i2c_physical_base:%x (dtsi)\n"
1168 , __func__, i2c_physical_base);
1169 else {
1170 dev_err(dev, "no fpga_i2c_physical_base defined in dts.\n");
1171 return -ENODEV;
1172 }
1173 i2c_base = ioremap(i2c_physical_base, 0x1000);
1174 if (!(i2c_base)) {
1175 dev_err(dev, "Can't remap I2C BASE\n");
1176 }
1177 dev_info(dev, "I2C BASE=0x%lx, %x\n", (uintptr_t) (i2c_base), i2c_physical_base);
1178#endif
1179
1180 index = 0;
1181 for_each_child_of_node(np, child_np) {
1182 struct fpga_phy_instance *instance;
1183 struct phy *phy;
1184
1185 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
1186
1187
1188 if (!instance) {
1189 ret = -ENOMEM;
1190 goto put_child;
1191 }
1192
1193 u3phy->phys[index] = instance;
1194
1195 phy = devm_phy_create(dev, child_np, &fpga_u3phy_ops);
1196 if (IS_ERR(phy)) {
1197 dev_err(dev, "failed to create phy\n");
1198 ret = PTR_ERR(phy);
1199 goto put_child;
1200 }
1201
1202 of_property_read_u32(child_np, "port",
1203 &instance->port);
1204 of_property_read_u32(child_np, "pclk_phase",
1205 &instance->u3_pclk);
1206 of_property_read_u32(child_np, "chip-id",
1207 &instance->chip_id);
1208
1209#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
1210 instance->i2c_base = u3phy->ippc_base +
1211 SSUSB_FPGA_I2C_PORT_OFFSET(instance->port);
1212#endif
1213 instance->phy = phy;
1214 instance->chip_version= ssusb_read_phy_version(u3phy, instance);
1215 if (instance->chip_version) {
1216 if (instance->chip_version != PHY_TEST_CHIP_NONAME)
1217 /* this chip has a correct chip version */
1218 instance->chip_id = instance->chip_version;
1219 else if(instance->chip_id != instance->chip_version) {
1220 dev_warn(dev, "WARN: this test chip maybe uses a wrong chip id\n"
1221 "use dts chip_id:%x\n", instance->chip_id);
1222 }
1223 } else {
1224 dev_warn(dev, "ERROR: maybe phy DTB not connected or powered?\n");
1225 }
1226 sprintf(instance->name, "%x", instance->chip_id);
1227 instance->index = index;
1228 instance->dev = dev;
1229 phy_set_drvdata(phy, instance);
1230 create_debugfs_interface(u3phy, instance);
1231 index++;
1232 if (instance->chip_version)
1233 dev_info(dev, "sub-board: %s, port:%d, u3_pclk: 0x%x\n",
1234 instance->name, instance->port, instance->u3_pclk);
1235 }
1236
1237 provider = devm_of_phy_provider_register(dev, fpga_phy_xlate);
1238
1239 return PTR_ERR_OR_ZERO(provider);
1240put_child:
1241 of_node_put(child_np);
1242 return ret;
1243}
1244
1245static struct platform_driver fpga_u3phy_driver = {
1246 .probe = fpga_u3phy_probe,
1247 .driver = {
1248 .name = "fpga-u3phy",
1249 .of_match_table = fpga_u3phy_id_table,
1250 },
1251};
1252
1253module_platform_driver(fpga_u3phy_driver);
1254
1255MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
1256MODULE_DESCRIPTION("MediaTek FPGA USB PHY driver");
1257MODULE_LICENSE("GPL v2");